[PATCH] D108598: [ARC] Add codegen for the readcyclecounter intrinsic along with disassembly for associated instructions

[Thomas Johnson via Phabricator via llvm-commits]

thomasjohns updated this revision to Diff 368366.
thomasjohns added a comment.

Separate S12 and U6 single operand decoding into different methods. Check legality of i64 in ARCISelLowering.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108598/new/

https://reviews.llvm.org/D108598

Files:
  llvm/lib/Target/ARC/ARCISelLowering.cpp
  llvm/lib/Target/ARC/ARCISelLowering.h
  llvm/lib/Target/ARC/ARCInstrFormats.td
  llvm/lib/Target/ARC/ARCInstrInfo.td
  llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp
  llvm/test/CodeGen/ARC/intrinsics.ll
  llvm/test/MC/Disassembler/ARC/ldst.txt

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D108598.368366.patch
Type: text/x-patch
Size: 9997 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210824/873601e2/attachment.bin>