[llvm] 2bf4eee - [GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 24 02:12:48 PDT 2021
Author: Petar Avramovic
Date: 2021-08-24T11:09:56+02:00
New Revision: 2bf4eeeeb60daba9534dd55088067fcf5a65f86b
URL: https://github.com/llvm/llvm-project/commit/2bf4eeeeb60daba9534dd55088067fcf5a65f86b
DIFF: https://github.com/llvm/llvm-project/commit/2bf4eeeeb60daba9534dd55088067fcf5a65f86b.diff
LOG: [GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
When Src and Dst used in buildAnyExtOrTrunc or buildSExtOrTrunc
have the same type (creates COPY) use Src register directly or
use replaceRegOrBuildCopy instead.
Differential Revision: https://reviews.llvm.org/D108306
Added:
Modified:
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz-zero-undef.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-divrem.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-isnan.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-memcpy-et-al.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptr-add.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-or.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-cmp.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner.mir
llvm/test/CodeGen/AArch64/GlobalISel/retry-artifact-combine.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-concat-vectors.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/image_ls_mipmap_zero.a16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def-s1025.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptr-add.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrmask.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sadde.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-local.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-private.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssube.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uadde.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usube.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-local.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-private.mir
llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir
llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-casts.mir
llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-control-flow.mir
llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-exts.mir
llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/fcmp.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_split_because_of_memsize_or_align.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll
llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll
llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir
llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll
llvm/test/CodeGen/X86/GlobalISel/shl-scalar.ll
llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fcmp.mir
llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir
llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir
llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
index 06dbd9d93b25c..ead26f12842e9 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
@@ -54,7 +54,8 @@ class LegalizationArtifactCombiner {
bool tryCombineAnyExt(MachineInstr &MI,
SmallVectorImpl<MachineInstr *> &DeadInsts,
- SmallVectorImpl<Register> &UpdatedDefs) {
+ SmallVectorImpl<Register> &UpdatedDefs,
+ GISelObserverWrapper &Observer) {
assert(MI.getOpcode() == TargetOpcode::G_ANYEXT);
Builder.setInstrAndDebugLoc(MI);
@@ -65,7 +66,11 @@ class LegalizationArtifactCombiner {
Register TruncSrc;
if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
- Builder.buildAnyExtOrTrunc(DstReg, TruncSrc);
+ if (MRI.getType(DstReg) == MRI.getType(TruncSrc))
+ replaceRegOrBuildCopy(DstReg, TruncSrc, MRI, Builder, UpdatedDefs,
+ Observer);
+ else
+ Builder.buildAnyExtOrTrunc(DstReg, TruncSrc);
UpdatedDefs.push_back(DstReg);
markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
return true;
@@ -125,9 +130,11 @@ class LegalizationArtifactCombiner {
APInt MaskVal = APInt::getAllOnesValue(SrcTy.getScalarSizeInBits());
auto Mask = Builder.buildConstant(
DstTy, MaskVal.zext(DstTy.getScalarSizeInBits()));
- auto Extended = SextSrc ? Builder.buildSExtOrTrunc(DstTy, SextSrc) :
- Builder.buildAnyExtOrTrunc(DstTy, TruncSrc);
- Builder.buildAnd(DstReg, Extended, Mask);
+ if (SextSrc && (DstTy != MRI.getType(SextSrc)))
+ SextSrc = Builder.buildSExtOrTrunc(DstTy, SextSrc).getReg(0);
+ if (TruncSrc && (DstTy != MRI.getType(TruncSrc)))
+ TruncSrc = Builder.buildAnyExtOrTrunc(DstTy, TruncSrc).getReg(0);
+ Builder.buildAnd(DstReg, SextSrc ? SextSrc : TruncSrc, Mask);
markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
return true;
}
@@ -178,9 +185,9 @@ class LegalizationArtifactCombiner {
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
LLT SrcTy = MRI.getType(SrcReg);
uint64_t SizeInBits = SrcTy.getScalarSizeInBits();
- Builder.buildInstr(
- TargetOpcode::G_SEXT_INREG, {DstReg},
- {Builder.buildAnyExtOrTrunc(DstTy, TruncSrc), SizeInBits});
+ if (DstTy != MRI.getType(TruncSrc))
+ TruncSrc = Builder.buildAnyExtOrTrunc(DstTy, TruncSrc).getReg(0);
+ Builder.buildSExtInReg(DstReg, TruncSrc, SizeInBits);
markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
return true;
}
@@ -1078,7 +1085,7 @@ class LegalizationArtifactCombiner {
default:
return false;
case TargetOpcode::G_ANYEXT:
- Changed = tryCombineAnyExt(MI, DeadInsts, UpdatedDefs);
+ Changed = tryCombineAnyExt(MI, DeadInsts, UpdatedDefs, WrapperObserver);
break;
case TargetOpcode::G_ZEXT:
Changed = tryCombineZExt(MI, DeadInsts, UpdatedDefs, WrapperObserver);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
index 13cb5191a690f..0308874c74b25 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
@@ -329,7 +329,7 @@ define i32 @fetch_and_nand(i32* %p) #0 {
; CHECK-NOLSE-O0-NEXT: str x0, [sp, #16] ; 8-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: ldr w8, [x0]
; CHECK-NOLSE-O0-NEXT: str w8, [sp, #28] ; 4-byte Folded Spill
-; CHECK-NOLSE-O0-NEXT: b LBB6_1
+; CHECK-NOLSE-O0-NEXT: b LBB6_1
; CHECK-NOLSE-O0-NEXT: LBB6_1: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ; Child Loop BB6_2 Depth 2
@@ -540,7 +540,7 @@ define i32 @fetch_and_or(i32* %p) #0 {
; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB8_1
-; CHECK-NOLSE-O0-NEXT: LBB8_5
+; CHECK-NOLSE-O0-NEXT: b LBB8_5
; CHECK-NOLSE-O0-NEXT: LBB8_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
@@ -1649,7 +1649,7 @@ define i8 @atomicrmw_or_i8(i8* %ptr, i8 %rhs) {
; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB31_1
-; CHECK-NOLSE-O0-NEXT: b LBB31_5
+; CHECK-NOLSE-O0-NEXT: b LBB31_5
; CHECK-NOLSE-O0-NEXT: LBB31_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
@@ -1765,8 +1765,7 @@ define i8 @atomicrmw_min_i8(i8* %ptr, i8 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: sxtb w9, w10
-; CHECK-NOLSE-O0-NEXT: mov w12, w8
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w12, sxtb
+; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, sxtb
; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, le
; CHECK-NOLSE-O0-NEXT: LBB33_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB33_1 Depth=1
@@ -1836,8 +1835,7 @@ define i8 @atomicrmw_max_i8(i8* %ptr, i8 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: sxtb w9, w10
-; CHECK-NOLSE-O0-NEXT: mov w12, w8
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w12, sxtb
+; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, sxtb
; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, gt
; CHECK-NOLSE-O0-NEXT: LBB34_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB34_1 Depth=1
@@ -1907,8 +1905,7 @@ define i8 @atomicrmw_umin_i8(i8* %ptr, i8 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: and w9, w10, #0xff
-; CHECK-NOLSE-O0-NEXT: mov w12, w8
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w12, uxtb
+; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, uxtb
; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, ls
; CHECK-NOLSE-O0-NEXT: LBB35_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB35_1 Depth=1
@@ -1928,7 +1925,7 @@ define i8 @atomicrmw_umin_i8(i8* %ptr, i8 %rhs) {
; CHECK-NOLSE-O0-NEXT: cset w8, eq
; CHECK-NOLSE-O0-NEXT: str w9, [sp, #28] ; 4-byte Folded Spill
; CHECK-NOLSE-O0-NEXT: tbz w8, #0, LBB35_1
-; CHECK-NOLSE-O0-NEXT: b LBB35_5
+; CHECK-NOLSE-O0-NEXT: b LBB35_5
; CHECK-NOLSE-O0-NEXT: LBB35_5: ; %atomicrmw.end
; CHECK-NOLSE-O0-NEXT: ldr w0, [sp, #12] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: add sp, sp, #32
@@ -1978,8 +1975,7 @@ define i8 @atomicrmw_umax_i8(i8* %ptr, i8 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: ldr w8, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: and w9, w10, #0xff
-; CHECK-NOLSE-O0-NEXT: mov w12, w8
-; CHECK-NOLSE-O0-NEXT: subs w9, w9, w12, uxtb
+; CHECK-NOLSE-O0-NEXT: subs w9, w9, w8, uxtb
; CHECK-NOLSE-O0-NEXT: csel w12, w10, w8, hi
; CHECK-NOLSE-O0-NEXT: LBB36_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB36_1 Depth=1
@@ -2448,8 +2444,7 @@ define i16 @atomicrmw_min_i16(i16* %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: sxth w10, w8
-; CHECK-NOLSE-O0-NEXT: mov w12, w9
-; CHECK-NOLSE-O0-NEXT: subs w10, w10, w12, sxth
+; CHECK-NOLSE-O0-NEXT: subs w10, w10, w9, sxth
; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, le
; CHECK-NOLSE-O0-NEXT: LBB43_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB43_1 Depth=1
@@ -2519,8 +2514,7 @@ define i16 @atomicrmw_max_i16(i16* %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: sxth w10, w8
-; CHECK-NOLSE-O0-NEXT: mov w12, w9
-; CHECK-NOLSE-O0-NEXT: subs w10, w10, w12, sxth
+; CHECK-NOLSE-O0-NEXT: subs w10, w10, w9, sxth
; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, gt
; CHECK-NOLSE-O0-NEXT: LBB44_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB44_1 Depth=1
@@ -2590,8 +2584,7 @@ define i16 @atomicrmw_umin_i16(i16* %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: uxth w10, w8
-; CHECK-NOLSE-O0-NEXT: mov w12, w9
-; CHECK-NOLSE-O0-NEXT: subs w10, w10, w12, uxth
+; CHECK-NOLSE-O0-NEXT: subs w10, w10, w9, uxth
; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, ls
; CHECK-NOLSE-O0-NEXT: LBB45_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB45_1 Depth=1
@@ -2661,8 +2654,7 @@ define i16 @atomicrmw_umax_i16(i16* %ptr, i16 %rhs) {
; CHECK-NOLSE-O0-NEXT: ldr x11, [sp, #16] ; 8-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: ldr w9, [sp, #24] ; 4-byte Folded Reload
; CHECK-NOLSE-O0-NEXT: uxth w10, w8
-; CHECK-NOLSE-O0-NEXT: mov w12, w9
-; CHECK-NOLSE-O0-NEXT: subs w10, w10, w12, uxth
+; CHECK-NOLSE-O0-NEXT: subs w10, w10, w9, uxth
; CHECK-NOLSE-O0-NEXT: csel w12, w8, w9, hi
; CHECK-NOLSE-O0-NEXT: LBB46_2: ; %atomicrmw.start
; CHECK-NOLSE-O0-NEXT: ; Parent Loop BB46_1 Depth=1
@@ -2729,10 +2721,9 @@ define { i8, i1 } @cmpxchg_i8(i8* %ptr, i8 %desired, i8 %new) {
; CHECK-NOLSE-O0-LABEL: cmpxchg_i8:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: mov x9, x0
-; CHECK-NOLSE-O0-NEXT: mov w10, w1
; CHECK-NOLSE-O0-NEXT: LBB47_1: ; =>This Inner Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ldaxrb w0, [x9]
-; CHECK-NOLSE-O0-NEXT: cmp w0, w10, uxtb
+; CHECK-NOLSE-O0-NEXT: cmp w0, w1, uxtb
; CHECK-NOLSE-O0-NEXT: b.ne LBB47_3
; CHECK-NOLSE-O0-NEXT: ; %bb.2: ; in Loop: Header=BB47_1 Depth=1
; CHECK-NOLSE-O0-NEXT: stlxrb w8, w2, [x9]
@@ -2796,10 +2787,9 @@ define { i16, i1 } @cmpxchg_i16(i16* %ptr, i16 %desired, i16 %new) {
; CHECK-NOLSE-O0-LABEL: cmpxchg_i16:
; CHECK-NOLSE-O0: ; %bb.0:
; CHECK-NOLSE-O0-NEXT: mov x9, x0
-; CHECK-NOLSE-O0-NEXT: mov w10, w1
; CHECK-NOLSE-O0-NEXT: LBB48_1: ; =>This Inner Loop Header: Depth=1
; CHECK-NOLSE-O0-NEXT: ldaxrh w0, [x9]
-; CHECK-NOLSE-O0-NEXT: cmp w0, w10, uxth
+; CHECK-NOLSE-O0-NEXT: cmp w0, w1, uxth
; CHECK-NOLSE-O0-NEXT: b.ne LBB48_3
; CHECK-NOLSE-O0-NEXT: ; %bb.2: ; in Loop: Header=BB48_1 Depth=1
; CHECK-NOLSE-O0-NEXT: stlxrh w8, w2, [x9]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
index 5196cc0b26e7f..3fc713c35e45a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
@@ -10,10 +10,8 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; CHECK: $w0 = COPY [[COPY2]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK: $x0 = COPY [[COPY3]](s64)
+ ; CHECK: $w0 = COPY [[AND]](s32)
+ ; CHECK: $x0 = COPY [[COPY]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64)
@@ -71,10 +69,9 @@ body: |
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64)
; CHECK: G_STORE [[COPY2]](s64), %ptr(p0) :: (store (s64), align 16)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
- ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C3]](s64)
+ ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C3]](s64)
; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C2]](s64)
- ; CHECK: G_STORE [[COPY3]](s32), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 8, align 8)
+ ; CHECK: G_STORE [[TRUNC]](s32), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 8, align 8)
; CHECK: G_STORE [[LSHR2]](s32), [[PTR_ADD3]](p0) :: (store (s8) into unknown-address + 10, align 2)
%ptr:_(p0) = COPY $x0
%a:_(s88) = G_LOAD %ptr(p0) :: (load (s88))
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir
index 367bd131c5217..f34766642623b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir
@@ -20,8 +20,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: (load store monotonic (s8) on %ir.addr)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ATOMICRMW_ADD]](s32)
- ; CHECK: $w0 = COPY [[COPY1]](s32)
+ ; CHECK: $w0 = COPY [[ATOMICRMW_ADD]](s32)
%0:_(p0) = COPY $x0
%1:_(s8) = G_CONSTANT i8 1
%2:_(s8) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic (s8) on %ir.addr)
@@ -39,8 +38,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[ATOMICRMW_ADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_ADD [[COPY]](p0), [[C]] :: (load store monotonic (s16) on %ir.addr)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ATOMICRMW_ADD]](s32)
- ; CHECK: $w0 = COPY [[COPY1]](s32)
+ ; CHECK: $w0 = COPY [[ATOMICRMW_ADD]](s32)
%0:_(p0) = COPY $x0
%1:_(s16) = G_CONSTANT i16 1
%2:_(s16) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic (s16) on %ir.addr)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
index e15ad817e921d..ab8e33ddbcf7e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
@@ -12,12 +12,10 @@ body: |
; CHECK-LABEL: name: bswap_s16
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
+ ; CHECK: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s64)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $w0 = COPY [[COPY2]](s32)
+ ; CHECK: $w0 = COPY [[LSHR]](s32)
; CHECK: RET_ReallyLR implicit $w0
%1:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %1(s32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
index d9c0982500349..ed4d688f27c8d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
@@ -8,20 +8,17 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY]](s64), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; CHECK: $w0 = COPY [[COPY2]](s32)
+ ; CHECK: $w0 = COPY [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; CHECK: $w0 = COPY [[COPY3]](s32)
+ ; CHECK: $w0 = COPY [[ICMP1]](s32)
; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
; CHECK: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[INTTOPTR]](p0), [[INTTOPTR]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
- ; CHECK: $w0 = COPY [[COPY4]](s32)
+ ; CHECK: $w0 = COPY [[ICMP2]](s32)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x0
%2:_(s8) = G_TRUNC %0(s64)
@@ -53,9 +50,7 @@ body: |
; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[DEF]](s64), [[C1]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32)
; CHECK: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[DEF]](s64), [[C]]
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY1]]
+ ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ICMP2]], [[ICMP]]
; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[SELECT]](s32)
; CHECK: G_BRCOND [[TRUNC1]](s1), %bb.1
; CHECK: G_BR %bb.2
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir
index 8fdb39a89daa6..e0f07e1fdb845 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir
@@ -17,13 +17,12 @@ body: |
; CHECK-LABEL: name: cmpxchg_i32
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[CMP:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[CST:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic (s64) on %ir.addr)
- ; CHECK: [[SRES:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[RES]](s32), [[CMP]]
- ; CHECK: [[SRES32:%[0-9]+]]:_(s32) = COPY [[SRES]]
- ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[RES]], [[SRES32]]
- ; CHECK: $w0 = COPY [[MUL]]
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s64) on %ir.addr)
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ATOMIC_CMPXCHG]](s32), [[C]]
+ ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[ATOMIC_CMPXCHG]], [[ICMP]]
+ ; CHECK: $w0 = COPY [[MUL]](s32)
%0:_(p0) = COPY $x0
%1:_(s32) = G_CONSTANT i32 0
%2:_(s32) = G_CONSTANT i32 1
@@ -42,13 +41,13 @@ body: |
; CHECK-LABEL: name: cmpxchg_i64
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[CMP:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK: [[CST:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
- ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[CMP]], [[CST]] :: (load store monotonic (s64) on %ir.addr)
- ; CHECK: [[SRES:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[RES]](s64), [[CMP]]
- ; CHECK: [[SRES64:%[0-9]+]]:_(s64) = G_ANYEXT [[SRES]]
- ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[RES]], [[SRES64]]
- ; CHECK: $x0 = COPY [[MUL]]
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s64) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s64) on %ir.addr)
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ATOMIC_CMPXCHG]](s64), [[C]]
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
+ ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ATOMIC_CMPXCHG]], [[ANYEXT]]
+ ; CHECK: $x0 = COPY [[MUL]](s64)
%0:_(p0) = COPY $x0
%1:_(s64) = G_CONSTANT i64 0
%2:_(s64) = G_CONSTANT i64 1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir
index 4b4aff3c3ed4b..ad0d0854875e6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir
@@ -21,8 +21,7 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s8) on %ir.addr)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ATOMIC_CMPXCHG]](s32)
- ; CHECK: $w0 = COPY [[COPY1]](s32)
+ ; CHECK: $w0 = COPY [[ATOMIC_CMPXCHG]](s32)
%0:_(p0) = COPY $x0
%1:_(s8) = G_CONSTANT i8 0
%2:_(s8) = G_CONSTANT i8 1
@@ -42,8 +41,7 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p0), [[C]], [[C1]] :: (load store monotonic (s16) on %ir.addr)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ATOMIC_CMPXCHG]](s32)
- ; CHECK: $w0 = COPY [[COPY1]](s32)
+ ; CHECK: $w0 = COPY [[ATOMIC_CMPXCHG]](s32)
%0:_(p0) = COPY $x0
%1:_(s16) = G_CONSTANT i16 0
%2:_(s16) = G_CONSTANT i16 1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
index 4675776dc3490..116f59ae1d601 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
@@ -22,10 +22,9 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ADD]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: $w0 = COPY [[COPY1]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
- ; CHECK: $x0 = COPY [[COPY2]](s64)
+ ; CHECK: $w0 = COPY [[COPY]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
+ ; CHECK: $x0 = COPY [[COPY1]](s64)
%0:_(s32) = COPY $w0
%1:_(s32) = G_ADD %0, %0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
index 4748314f69f26..fc02f47011879 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
@@ -120,8 +120,7 @@ body: |
; CHECK: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlv), [[CTPOP]](<8 x s8>)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[INT]](s32)
- ; CHECK: %ext:_(s32) = COPY [[COPY]](s32)
- ; CHECK: $w0 = COPY %ext(s32)
+ ; CHECK: $w0 = COPY [[COPY]](s32)
; CHECK: RET_ReallyLR implicit $w0
%copy:_(s32) = COPY $w0
%trunc:_(s16) = G_TRUNC %copy(s32)
@@ -148,8 +147,7 @@ body: |
; CHECK: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlv), [[CTPOP]](<8 x s8>)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[INT]](s32)
- ; CHECK: %ext:_(s32) = COPY [[COPY]](s32)
- ; CHECK: $w0 = COPY %ext(s32)
+ ; CHECK: $w0 = COPY [[COPY]](s32)
; CHECK: RET_ReallyLR implicit $w0
%copy:_(s32) = COPY $w0
%trunc:_(s8) = G_TRUNC %copy(s32)
@@ -176,8 +174,7 @@ body: |
; CHECK: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlv), [[CTPOP]](<8 x s8>)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[INT]](s32)
- ; CHECK: %ext:_(s32) = COPY [[COPY]](s32)
- ; CHECK: $w0 = COPY %ext(s32)
+ ; CHECK: $w0 = COPY [[COPY]](s32)
; CHECK: RET_ReallyLR implicit $w0
%copy:_(s32) = COPY $w0
%trunc:_(s3) = G_TRUNC %copy(s32)
@@ -203,8 +200,7 @@ body: |
; CHECK: [[CTPOP:%[0-9]+]]:_(<8 x s8>) = G_CTPOP [[BITCAST]](<8 x s8>)
; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlv), [[CTPOP]](<8 x s8>)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[INT]](s32)
- ; CHECK: %ext:_(s32) = COPY [[COPY]](s32)
- ; CHECK: $w0 = COPY %ext(s32)
+ ; CHECK: $w0 = COPY [[COPY]](s32)
; CHECK: RET_ReallyLR implicit $w0
%copy:_(s32) = COPY $w0
%trunc:_(s8) = G_TRUNC %copy(s32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz-zero-undef.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz-zero-undef.mir
index 91fe31430bc9c..b823719f6e881 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz-zero-undef.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz-zero-undef.mir
@@ -16,8 +16,7 @@ body: |
; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[OR]]
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTLZ]](s32)
- ; CHECK: %ext:_(s32) = COPY [[COPY]](s32)
- ; CHECK: $w0 = COPY %ext(s32)
+ ; CHECK: $w0 = COPY [[COPY]](s32)
; CHECK: RET_ReallyLR implicit $w0
%val:_(s8) = G_IMPLICIT_DEF
%cttz:_(s8) = G_CTTZ_ZERO_UNDEF %val(s8)
@@ -40,8 +39,7 @@ body: |
; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[OR]]
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTLZ]](s32)
- ; CHECK: %ext:_(s32) = COPY [[COPY]](s32)
- ; CHECK: $w0 = COPY %ext(s32)
+ ; CHECK: $w0 = COPY [[COPY]](s32)
; CHECK: RET_ReallyLR implicit $w0
%val:_(s16) = G_IMPLICIT_DEF
%cttz:_(s16) = G_CTTZ_ZERO_UNDEF %val(s16)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir
index 95fc630751f30..418b31d061518 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-cttz.mir
@@ -16,8 +16,7 @@ body: |
; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[OR]]
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTLZ]](s32)
- ; CHECK: %ext:_(s32) = COPY [[COPY]](s32)
- ; CHECK: $w0 = COPY %ext(s32)
+ ; CHECK: $w0 = COPY [[COPY]](s32)
; CHECK: RET_ReallyLR implicit $w0
%val:_(s8) = G_IMPLICIT_DEF
%cttz:_(s8) = G_CTTZ %val(s8)
@@ -40,8 +39,7 @@ body: |
; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[OR]]
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTLZ]](s32)
- ; CHECK: %ext:_(s32) = COPY [[COPY]](s32)
- ; CHECK: $w0 = COPY %ext(s32)
+ ; CHECK: $w0 = COPY [[COPY]](s32)
; CHECK: RET_ReallyLR implicit $w0
%val:_(s16) = G_IMPLICIT_DEF
%cttz:_(s16) = G_CTTZ %val(s16)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
index 93b476f33a1a6..ae8c6851a7f39 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
@@ -12,16 +12,14 @@ body: |
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
- ; CHECK: $w0 = COPY [[COPY2]](s32)
+ ; CHECK: $w0 = COPY [[SDIV]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C]]
; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
- ; CHECK: $w0 = COPY [[COPY3]](s32)
+ ; CHECK: $w0 = COPY [[UDIV]](s32)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-divrem.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-divrem.mir
index 91a9d2234c88a..72ecb295f857f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-divrem.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-divrem.mir
@@ -54,15 +54,12 @@ body: |
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[TRUNC1]](s32)
- ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY4]], [[COPY5]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: $w0 = COPY [[COPY2]](s32)
- ; CHECK: $w1 = COPY [[COPY6]](s32)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[TRUNC1]](s32)
+ ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[COPY2]]
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
+ ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY3]], [[MUL]]
+ ; CHECK: $w0 = COPY [[SDIV]](s32)
+ ; CHECK: $w1 = COPY [[SUB]](s32)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
index c751570634e16..e4dca360375a8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
@@ -14,16 +14,12 @@ body: |
; CHECK: $w0 = COPY [[TRUNC2]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: $w0 = COPY [[TRUNC3]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK: $x0 = COPY [[COPY1]](s64)
+ ; CHECK: $x0 = COPY [[COPY]](s64)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; CHECK: $x0 = COPY [[AND]](s64)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK: $x0 = COPY [[COPY3]](s64)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY4]], 32
+ ; CHECK: $x0 = COPY [[COPY]](s64)
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; CHECK: $x0 = COPY [[SEXT_INREG]](s64)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC4]], 1
@@ -53,8 +49,8 @@ body: |
; CHECK: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[TRUNC12]](s32)
; CHECK: $x0 = COPY [[FPEXT]](s64)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; CHECK: $w0 = COPY [[COPY5]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; CHECK: $w0 = COPY [[COPY1]](s32)
; CHECK: $w0 = COPY [[C3]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: $w0 = COPY [[DEF]](s32)
@@ -117,8 +113,7 @@ body: |
; CHECK-LABEL: name: test_anyext_anyext
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: $w0 = COPY [[COPY1]](s32)
+ ; CHECK: $w0 = COPY [[COPY]](s32)
%0:_(s32) = COPY $w0
%1:_(s1) = G_TRUNC %0(s32)
%2:_(s8) = G_ANYEXT %1(s1)
@@ -134,8 +129,7 @@ body: |
; CHECK-LABEL: name: test_anyext_sext
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
; CHECK: $w0 = COPY [[SEXT_INREG]](s32)
%0:_(s32) = COPY $w0
%1:_(s1) = G_TRUNC %0(s32)
@@ -153,8 +147,7 @@ body: |
; CHECK-LABEL: name: test_anyext_zext
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: $w0 = COPY [[AND]](s32)
%0:_(s32) = COPY $w0
%1:_(s1) = G_TRUNC %0(s32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
index 1272d29c2ddc0..5fd6dc0cec026 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
@@ -28,14 +28,12 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(eq), [[COPY]](<2 x s64>), [[COPY1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY3]], [[BUILD_VECTOR]](<2 x s64>)
+ ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[ASHR]](<2 x s64>), [[COPY2]](s64)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[EVEC]](s64)
- ; CHECK: $x0 = COPY [[COPY4]](s64)
+ ; CHECK: $x0 = COPY [[EVEC]](s64)
; CHECK: RET_ReallyLR
%0:_(<2 x s64>) = COPY $q0
%1:_(<2 x s64>) = COPY $q1
@@ -56,10 +54,9 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY]](<4 x s32>), [[COPY1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY [[ICMP]](<4 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
- ; CHECK: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL [[COPY3]], [[BUILD_VECTOR]](<4 x s32>)
+ ; CHECK: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<4 x s32>)
; CHECK: [[ASHR:%[0-9]+]]:_(<4 x s32>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<4 x s32>)
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[ASHR]](<4 x s32>), [[COPY2]](s64)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[EVEC]](s32)
@@ -84,10 +81,9 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(eq), [[COPY]](<8 x s16>), [[COPY1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(<8 x s16>) = COPY [[ICMP]](<8 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16)
- ; CHECK: [[SHL:%[0-9]+]]:_(<8 x s16>) = G_SHL [[COPY3]], [[BUILD_VECTOR]](<8 x s16>)
+ ; CHECK: [[SHL:%[0-9]+]]:_(<8 x s16>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<8 x s16>)
; CHECK: [[ASHR:%[0-9]+]]:_(<8 x s16>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<8 x s16>)
; CHECK: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[ASHR]](<8 x s16>), [[COPY2]](s64)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[EVEC]](s16)
@@ -112,10 +108,9 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 7
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8)
- ; CHECK: [[SHL:%[0-9]+]]:_(<16 x s8>) = G_SHL [[COPY3]], [[BUILD_VECTOR]](<16 x s8>)
+ ; CHECK: [[SHL:%[0-9]+]]:_(<16 x s8>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<16 x s8>)
; CHECK: [[ASHR:%[0-9]+]]:_(<16 x s8>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<16 x s8>)
; CHECK: [[EVEC:%[0-9]+]]:_(s8) = G_EXTRACT_VECTOR_ELT [[ASHR]](<16 x s8>), [[COPY2]](s64)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[EVEC]](s8)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
index a95396a603704..4f9af35b2a056 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
@@ -239,8 +239,7 @@ body: |
; CHECK: liveins: $w0
; CHECK: %val:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %val(s32)
- ; CHECK: %ext:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: %ext:_(s32) = G_AND %val, [[C]]
; CHECK: $w0 = COPY %ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%val:_(s32) = COPY $w0
@@ -259,8 +258,7 @@ body: |
; CHECK: liveins: $w0
; CHECK: %val:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %val(s32)
- ; CHECK: %ext:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: %ext:_(s32) = G_AND %val, [[C]]
; CHECK: $w0 = COPY %ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%val:_(s32) = COPY $w0
@@ -278,9 +276,8 @@ body: |
; CHECK-LABEL: name: s3_from_s35
; CHECK: liveins: $w0
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY [[DEF]](s64)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF]](s64)
; CHECK: %ext:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK: $w0 = COPY %ext(s32)
; CHECK: RET_ReallyLR implicit $w0
@@ -300,8 +297,7 @@ body: |
; CHECK: liveins: $w0
; CHECK: %val:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %val(s32)
- ; CHECK: %ext:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: %ext:_(s32) = G_AND %val, [[C]]
; CHECK: $w0 = COPY %ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%val:_(s32) = COPY $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
index 6b7b6176d0166..ef86464a9682a 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
@@ -139,8 +139,7 @@ body: |
; CHECK-LABEL: name: test_fptoui_s1_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; CHECK: $w0 = COPY [[COPY1]](s32)
+ ; CHECK: $w0 = COPY [[FPTOUI]](s32)
%0:_(s32) = COPY $w0
%1:_(s1) = G_FPTOUI %0
%2:_(s32) = G_ANYEXT %1
@@ -155,8 +154,7 @@ body: |
; CHECK-LABEL: name: test_fptosi_s8_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; CHECK: $w0 = COPY [[COPY1]](s32)
+ ; CHECK: $w0 = COPY [[FPTOSI]](s32)
%0:_(s64) = COPY $x0
%1:_(s8) = G_FPTOSI %0
%2:_(s32) = G_ANYEXT %1
@@ -171,8 +169,7 @@ body: |
; CHECK-LABEL: name: test_fptoui_s8_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; CHECK: $w0 = COPY [[COPY1]](s32)
+ ; CHECK: $w0 = COPY [[FPTOUI]](s32)
%0:_(s64) = COPY $x0
%1:_(s8) = G_FPTOUI %0
%2:_(s32) = G_ANYEXT %1
@@ -187,8 +184,7 @@ body: |
; CHECK-LABEL: name: test_fptosi_s16_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; CHECK: $w0 = COPY [[COPY1]](s32)
+ ; CHECK: $w0 = COPY [[FPTOSI]](s32)
%0:_(s32) = COPY $w0
%1:_(s16) = G_FPTOSI %0
%2:_(s32) = G_ANYEXT %1
@@ -203,8 +199,7 @@ body: |
; CHECK-LABEL: name: test_fptoui_s16_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; CHECK: $w0 = COPY [[COPY1]](s32)
+ ; CHECK: $w0 = COPY [[FPTOUI]](s32)
%0:_(s32) = COPY $w0
%1:_(s16) = G_FPTOUI %0
%2:_(s32) = G_ANYEXT %1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
index ba49885723604..69715c2cef252 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
@@ -107,8 +107,7 @@ body: |
liveins: $x0
; CHECK-LABEL: name: test_freeze_s2
; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
- ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY [[DEF]](s8)
- ; CHECK: [[FREEZE:%[0-9]+]]:_(s8) = G_FREEZE [[COPY]]
+ ; CHECK: [[FREEZE:%[0-9]+]]:_(s8) = G_FREEZE [[DEF]]
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FREEZE]](s8)
; CHECK: %ext:_(s64) = G_AND [[ANYEXT]], [[C]]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
index e8f88a11511b3..6abc3fa928d4b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
@@ -193,647 +193,383 @@ body: |
; CHECK: [[ZEXT55:%[0-9]+]]:_(s32) = G_ZEXT [[UV7]](s8)
; CHECK: [[LSHR55:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT55]], [[C13]](s64)
; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C14]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C14]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s64)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C14]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[COPY4]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C14]]
+ ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C14]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C3]](s64)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
- ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY6]], [[COPY7]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C14]]
+ ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C14]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C5]](s64)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SHL2]](s32)
- ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[COPY9]], [[COPY10]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C14]]
+ ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C14]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C7]](s64)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[SHL3]](s32)
- ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[COPY12]], [[COPY13]]
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C14]]
+ ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C14]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C9]](s64)
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[SHL4]](s32)
- ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[COPY16]]
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C14]]
+ ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C14]]
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C11]](s64)
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[OR4]](s32)
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[SHL5]](s32)
- ; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[COPY18]], [[COPY19]]
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C14]]
+ ; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C14]]
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C13]](s64)
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[OR5]](s32)
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[SHL6]](s32)
- ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[COPY21]], [[COPY22]]
+ ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[OR6]](s32)
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C14]]
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C14]]
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C1]](s64)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8)
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C14]]
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[SHL7]](s32)
- ; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[COPY24]]
- ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C14]]
+ ; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[SHL7]]
+ ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C14]]
; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C3]](s64)
- ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[OR7]](s32)
- ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[SHL8]](s32)
- ; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[COPY26]], [[COPY27]]
- ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C14]]
+ ; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
+ ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C14]]
; CHECK: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C5]](s64)
- ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[OR8]](s32)
- ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[SHL9]](s32)
- ; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[COPY29]], [[COPY30]]
- ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C14]]
+ ; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[SHL9]]
+ ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C14]]
; CHECK: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C7]](s64)
- ; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[OR9]](s32)
- ; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[SHL10]](s32)
- ; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[COPY32]], [[COPY33]]
- ; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY34]], [[C14]]
+ ; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
+ ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C14]]
; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C9]](s64)
- ; CHECK: [[COPY35:%[0-9]+]]:_(s32) = COPY [[OR10]](s32)
- ; CHECK: [[COPY36:%[0-9]+]]:_(s32) = COPY [[SHL11]](s32)
- ; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[COPY35]], [[COPY36]]
- ; CHECK: [[COPY37:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY37]], [[C14]]
+ ; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
+ ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C14]]
; CHECK: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C11]](s64)
- ; CHECK: [[COPY38:%[0-9]+]]:_(s32) = COPY [[OR11]](s32)
- ; CHECK: [[COPY39:%[0-9]+]]:_(s32) = COPY [[SHL12]](s32)
- ; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[COPY38]], [[COPY39]]
- ; CHECK: [[COPY40:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY40]], [[C14]]
+ ; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR11]], [[SHL12]]
+ ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C14]]
; CHECK: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C13]](s64)
- ; CHECK: [[COPY41:%[0-9]+]]:_(s32) = COPY [[OR12]](s32)
- ; CHECK: [[COPY42:%[0-9]+]]:_(s32) = COPY [[SHL13]](s32)
- ; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[COPY41]], [[COPY42]]
+ ; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[OR13]](s32)
- ; CHECK: [[COPY43:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY43]], [[C14]]
+ ; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C14]]
; CHECK: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND16]], [[C1]](s64)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C14]]
- ; CHECK: [[COPY44:%[0-9]+]]:_(s32) = COPY [[SHL14]](s32)
- ; CHECK: [[OR14:%[0-9]+]]:_(s32) = G_OR [[AND17]], [[COPY44]]
- ; CHECK: [[COPY45:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; CHECK: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY45]], [[C14]]
+ ; CHECK: [[OR14:%[0-9]+]]:_(s32) = G_OR [[AND17]], [[SHL14]]
+ ; CHECK: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C14]]
; CHECK: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C3]](s64)
- ; CHECK: [[COPY46:%[0-9]+]]:_(s32) = COPY [[OR14]](s32)
- ; CHECK: [[COPY47:%[0-9]+]]:_(s32) = COPY [[SHL15]](s32)
- ; CHECK: [[OR15:%[0-9]+]]:_(s32) = G_OR [[COPY46]], [[COPY47]]
- ; CHECK: [[COPY48:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; CHECK: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY48]], [[C14]]
+ ; CHECK: [[OR15:%[0-9]+]]:_(s32) = G_OR [[OR14]], [[SHL15]]
+ ; CHECK: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR16]], [[C14]]
; CHECK: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C5]](s64)
- ; CHECK: [[COPY49:%[0-9]+]]:_(s32) = COPY [[OR15]](s32)
- ; CHECK: [[COPY50:%[0-9]+]]:_(s32) = COPY [[SHL16]](s32)
- ; CHECK: [[OR16:%[0-9]+]]:_(s32) = G_OR [[COPY49]], [[COPY50]]
- ; CHECK: [[COPY51:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; CHECK: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY51]], [[C14]]
+ ; CHECK: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
+ ; CHECK: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LSHR17]], [[C14]]
; CHECK: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND20]], [[C7]](s64)
- ; CHECK: [[COPY52:%[0-9]+]]:_(s32) = COPY [[OR16]](s32)
- ; CHECK: [[COPY53:%[0-9]+]]:_(s32) = COPY [[SHL17]](s32)
- ; CHECK: [[OR17:%[0-9]+]]:_(s32) = G_OR [[COPY52]], [[COPY53]]
- ; CHECK: [[COPY54:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; CHECK: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY54]], [[C14]]
+ ; CHECK: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
+ ; CHECK: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LSHR18]], [[C14]]
; CHECK: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C9]](s64)
- ; CHECK: [[COPY55:%[0-9]+]]:_(s32) = COPY [[OR17]](s32)
- ; CHECK: [[COPY56:%[0-9]+]]:_(s32) = COPY [[SHL18]](s32)
- ; CHECK: [[OR18:%[0-9]+]]:_(s32) = G_OR [[COPY55]], [[COPY56]]
- ; CHECK: [[COPY57:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; CHECK: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY57]], [[C14]]
+ ; CHECK: [[OR18:%[0-9]+]]:_(s32) = G_OR [[OR17]], [[SHL18]]
+ ; CHECK: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR19]], [[C14]]
; CHECK: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C11]](s64)
- ; CHECK: [[COPY58:%[0-9]+]]:_(s32) = COPY [[OR18]](s32)
- ; CHECK: [[COPY59:%[0-9]+]]:_(s32) = COPY [[SHL19]](s32)
- ; CHECK: [[OR19:%[0-9]+]]:_(s32) = G_OR [[COPY58]], [[COPY59]]
- ; CHECK: [[COPY60:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; CHECK: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY60]], [[C14]]
+ ; CHECK: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
+ ; CHECK: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR20]], [[C14]]
; CHECK: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C13]](s64)
- ; CHECK: [[COPY61:%[0-9]+]]:_(s32) = COPY [[OR19]](s32)
- ; CHECK: [[COPY62:%[0-9]+]]:_(s32) = COPY [[SHL20]](s32)
- ; CHECK: [[OR20:%[0-9]+]]:_(s32) = G_OR [[COPY61]], [[COPY62]]
+ ; CHECK: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR20]](s32)
- ; CHECK: [[COPY63:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; CHECK: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY63]], [[C14]]
+ ; CHECK: [[AND24:%[0-9]+]]:_(s32) = G_AND [[LSHR21]], [[C14]]
; CHECK: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C1]](s64)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
; CHECK: [[AND25:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C14]]
- ; CHECK: [[COPY64:%[0-9]+]]:_(s32) = COPY [[SHL21]](s32)
- ; CHECK: [[OR21:%[0-9]+]]:_(s32) = G_OR [[AND25]], [[COPY64]]
- ; CHECK: [[COPY65:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; CHECK: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY65]], [[C14]]
+ ; CHECK: [[OR21:%[0-9]+]]:_(s32) = G_OR [[AND25]], [[SHL21]]
+ ; CHECK: [[AND26:%[0-9]+]]:_(s32) = G_AND [[LSHR22]], [[C14]]
; CHECK: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C3]](s64)
- ; CHECK: [[COPY66:%[0-9]+]]:_(s32) = COPY [[OR21]](s32)
- ; CHECK: [[COPY67:%[0-9]+]]:_(s32) = COPY [[SHL22]](s32)
- ; CHECK: [[OR22:%[0-9]+]]:_(s32) = G_OR [[COPY66]], [[COPY67]]
- ; CHECK: [[COPY68:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; CHECK: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY68]], [[C14]]
+ ; CHECK: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
+ ; CHECK: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LSHR23]], [[C14]]
; CHECK: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[C5]](s64)
- ; CHECK: [[COPY69:%[0-9]+]]:_(s32) = COPY [[OR22]](s32)
- ; CHECK: [[COPY70:%[0-9]+]]:_(s32) = COPY [[SHL23]](s32)
- ; CHECK: [[OR23:%[0-9]+]]:_(s32) = G_OR [[COPY69]], [[COPY70]]
- ; CHECK: [[COPY71:%[0-9]+]]:_(s32) = COPY [[LSHR24]](s32)
- ; CHECK: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY71]], [[C14]]
+ ; CHECK: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
+ ; CHECK: [[AND28:%[0-9]+]]:_(s32) = G_AND [[LSHR24]], [[C14]]
; CHECK: [[SHL24:%[0-9]+]]:_(s32) = G_SHL [[AND28]], [[C7]](s64)
- ; CHECK: [[COPY72:%[0-9]+]]:_(s32) = COPY [[OR23]](s32)
- ; CHECK: [[COPY73:%[0-9]+]]:_(s32) = COPY [[SHL24]](s32)
- ; CHECK: [[OR24:%[0-9]+]]:_(s32) = G_OR [[COPY72]], [[COPY73]]
- ; CHECK: [[COPY74:%[0-9]+]]:_(s32) = COPY [[LSHR25]](s32)
- ; CHECK: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY74]], [[C14]]
+ ; CHECK: [[OR24:%[0-9]+]]:_(s32) = G_OR [[OR23]], [[SHL24]]
+ ; CHECK: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LSHR25]], [[C14]]
; CHECK: [[SHL25:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[C9]](s64)
- ; CHECK: [[COPY75:%[0-9]+]]:_(s32) = COPY [[OR24]](s32)
- ; CHECK: [[COPY76:%[0-9]+]]:_(s32) = COPY [[SHL25]](s32)
- ; CHECK: [[OR25:%[0-9]+]]:_(s32) = G_OR [[COPY75]], [[COPY76]]
- ; CHECK: [[COPY77:%[0-9]+]]:_(s32) = COPY [[LSHR26]](s32)
- ; CHECK: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY77]], [[C14]]
+ ; CHECK: [[OR25:%[0-9]+]]:_(s32) = G_OR [[OR24]], [[SHL25]]
+ ; CHECK: [[AND30:%[0-9]+]]:_(s32) = G_AND [[LSHR26]], [[C14]]
; CHECK: [[SHL26:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[C11]](s64)
- ; CHECK: [[COPY78:%[0-9]+]]:_(s32) = COPY [[OR25]](s32)
- ; CHECK: [[COPY79:%[0-9]+]]:_(s32) = COPY [[SHL26]](s32)
- ; CHECK: [[OR26:%[0-9]+]]:_(s32) = G_OR [[COPY78]], [[COPY79]]
- ; CHECK: [[COPY80:%[0-9]+]]:_(s32) = COPY [[LSHR27]](s32)
- ; CHECK: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY80]], [[C14]]
+ ; CHECK: [[OR26:%[0-9]+]]:_(s32) = G_OR [[OR25]], [[SHL26]]
+ ; CHECK: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LSHR27]], [[C14]]
; CHECK: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C13]](s64)
- ; CHECK: [[COPY81:%[0-9]+]]:_(s32) = COPY [[OR26]](s32)
- ; CHECK: [[COPY82:%[0-9]+]]:_(s32) = COPY [[SHL27]](s32)
- ; CHECK: [[OR27:%[0-9]+]]:_(s32) = G_OR [[COPY81]], [[COPY82]]
+ ; CHECK: [[OR27:%[0-9]+]]:_(s32) = G_OR [[OR26]], [[SHL27]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[OR27]](s32)
- ; CHECK: [[COPY83:%[0-9]+]]:_(s32) = COPY [[LSHR28]](s32)
- ; CHECK: [[AND32:%[0-9]+]]:_(s32) = G_AND [[COPY83]], [[C14]]
+ ; CHECK: [[AND32:%[0-9]+]]:_(s32) = G_AND [[LSHR28]], [[C14]]
; CHECK: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[AND32]], [[C1]](s64)
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
; CHECK: [[AND33:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C14]]
- ; CHECK: [[COPY84:%[0-9]+]]:_(s32) = COPY [[SHL28]](s32)
- ; CHECK: [[OR28:%[0-9]+]]:_(s32) = G_OR [[AND33]], [[COPY84]]
- ; CHECK: [[COPY85:%[0-9]+]]:_(s32) = COPY [[LSHR29]](s32)
- ; CHECK: [[AND34:%[0-9]+]]:_(s32) = G_AND [[COPY85]], [[C14]]
+ ; CHECK: [[OR28:%[0-9]+]]:_(s32) = G_OR [[AND33]], [[SHL28]]
+ ; CHECK: [[AND34:%[0-9]+]]:_(s32) = G_AND [[LSHR29]], [[C14]]
; CHECK: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[AND34]], [[C3]](s64)
- ; CHECK: [[COPY86:%[0-9]+]]:_(s32) = COPY [[OR28]](s32)
- ; CHECK: [[COPY87:%[0-9]+]]:_(s32) = COPY [[SHL29]](s32)
- ; CHECK: [[OR29:%[0-9]+]]:_(s32) = G_OR [[COPY86]], [[COPY87]]
- ; CHECK: [[COPY88:%[0-9]+]]:_(s32) = COPY [[LSHR30]](s32)
- ; CHECK: [[AND35:%[0-9]+]]:_(s32) = G_AND [[COPY88]], [[C14]]
+ ; CHECK: [[OR29:%[0-9]+]]:_(s32) = G_OR [[OR28]], [[SHL29]]
+ ; CHECK: [[AND35:%[0-9]+]]:_(s32) = G_AND [[LSHR30]], [[C14]]
; CHECK: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[AND35]], [[C5]](s64)
- ; CHECK: [[COPY89:%[0-9]+]]:_(s32) = COPY [[OR29]](s32)
- ; CHECK: [[COPY90:%[0-9]+]]:_(s32) = COPY [[SHL30]](s32)
- ; CHECK: [[OR30:%[0-9]+]]:_(s32) = G_OR [[COPY89]], [[COPY90]]
- ; CHECK: [[COPY91:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
- ; CHECK: [[AND36:%[0-9]+]]:_(s32) = G_AND [[COPY91]], [[C14]]
+ ; CHECK: [[OR30:%[0-9]+]]:_(s32) = G_OR [[OR29]], [[SHL30]]
+ ; CHECK: [[AND36:%[0-9]+]]:_(s32) = G_AND [[LSHR31]], [[C14]]
; CHECK: [[SHL31:%[0-9]+]]:_(s32) = G_SHL [[AND36]], [[C7]](s64)
- ; CHECK: [[COPY92:%[0-9]+]]:_(s32) = COPY [[OR30]](s32)
- ; CHECK: [[COPY93:%[0-9]+]]:_(s32) = COPY [[SHL31]](s32)
- ; CHECK: [[OR31:%[0-9]+]]:_(s32) = G_OR [[COPY92]], [[COPY93]]
- ; CHECK: [[COPY94:%[0-9]+]]:_(s32) = COPY [[LSHR32]](s32)
- ; CHECK: [[AND37:%[0-9]+]]:_(s32) = G_AND [[COPY94]], [[C14]]
+ ; CHECK: [[OR31:%[0-9]+]]:_(s32) = G_OR [[OR30]], [[SHL31]]
+ ; CHECK: [[AND37:%[0-9]+]]:_(s32) = G_AND [[LSHR32]], [[C14]]
; CHECK: [[SHL32:%[0-9]+]]:_(s32) = G_SHL [[AND37]], [[C9]](s64)
- ; CHECK: [[COPY95:%[0-9]+]]:_(s32) = COPY [[OR31]](s32)
- ; CHECK: [[COPY96:%[0-9]+]]:_(s32) = COPY [[SHL32]](s32)
- ; CHECK: [[OR32:%[0-9]+]]:_(s32) = G_OR [[COPY95]], [[COPY96]]
- ; CHECK: [[COPY97:%[0-9]+]]:_(s32) = COPY [[LSHR33]](s32)
- ; CHECK: [[AND38:%[0-9]+]]:_(s32) = G_AND [[COPY97]], [[C14]]
+ ; CHECK: [[OR32:%[0-9]+]]:_(s32) = G_OR [[OR31]], [[SHL32]]
+ ; CHECK: [[AND38:%[0-9]+]]:_(s32) = G_AND [[LSHR33]], [[C14]]
; CHECK: [[SHL33:%[0-9]+]]:_(s32) = G_SHL [[AND38]], [[C11]](s64)
- ; CHECK: [[COPY98:%[0-9]+]]:_(s32) = COPY [[OR32]](s32)
- ; CHECK: [[COPY99:%[0-9]+]]:_(s32) = COPY [[SHL33]](s32)
- ; CHECK: [[OR33:%[0-9]+]]:_(s32) = G_OR [[COPY98]], [[COPY99]]
- ; CHECK: [[COPY100:%[0-9]+]]:_(s32) = COPY [[LSHR34]](s32)
- ; CHECK: [[AND39:%[0-9]+]]:_(s32) = G_AND [[COPY100]], [[C14]]
+ ; CHECK: [[OR33:%[0-9]+]]:_(s32) = G_OR [[OR32]], [[SHL33]]
+ ; CHECK: [[AND39:%[0-9]+]]:_(s32) = G_AND [[LSHR34]], [[C14]]
; CHECK: [[SHL34:%[0-9]+]]:_(s32) = G_SHL [[AND39]], [[C13]](s64)
- ; CHECK: [[COPY101:%[0-9]+]]:_(s32) = COPY [[OR33]](s32)
- ; CHECK: [[COPY102:%[0-9]+]]:_(s32) = COPY [[SHL34]](s32)
- ; CHECK: [[OR34:%[0-9]+]]:_(s32) = G_OR [[COPY101]], [[COPY102]]
+ ; CHECK: [[OR34:%[0-9]+]]:_(s32) = G_OR [[OR33]], [[SHL34]]
; CHECK: [[TRUNC4:%[0-9]+]]:_(s8) = G_TRUNC [[OR34]](s32)
- ; CHECK: [[COPY103:%[0-9]+]]:_(s32) = COPY [[LSHR35]](s32)
- ; CHECK: [[AND40:%[0-9]+]]:_(s32) = G_AND [[COPY103]], [[C14]]
+ ; CHECK: [[AND40:%[0-9]+]]:_(s32) = G_AND [[LSHR35]], [[C14]]
; CHECK: [[SHL35:%[0-9]+]]:_(s32) = G_SHL [[AND40]], [[C1]](s64)
; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)
; CHECK: [[AND41:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C14]]
- ; CHECK: [[COPY104:%[0-9]+]]:_(s32) = COPY [[SHL35]](s32)
- ; CHECK: [[OR35:%[0-9]+]]:_(s32) = G_OR [[AND41]], [[COPY104]]
- ; CHECK: [[COPY105:%[0-9]+]]:_(s32) = COPY [[LSHR36]](s32)
- ; CHECK: [[AND42:%[0-9]+]]:_(s32) = G_AND [[COPY105]], [[C14]]
+ ; CHECK: [[OR35:%[0-9]+]]:_(s32) = G_OR [[AND41]], [[SHL35]]
+ ; CHECK: [[AND42:%[0-9]+]]:_(s32) = G_AND [[LSHR36]], [[C14]]
; CHECK: [[SHL36:%[0-9]+]]:_(s32) = G_SHL [[AND42]], [[C3]](s64)
- ; CHECK: [[COPY106:%[0-9]+]]:_(s32) = COPY [[OR35]](s32)
- ; CHECK: [[COPY107:%[0-9]+]]:_(s32) = COPY [[SHL36]](s32)
- ; CHECK: [[OR36:%[0-9]+]]:_(s32) = G_OR [[COPY106]], [[COPY107]]
- ; CHECK: [[COPY108:%[0-9]+]]:_(s32) = COPY [[LSHR37]](s32)
- ; CHECK: [[AND43:%[0-9]+]]:_(s32) = G_AND [[COPY108]], [[C14]]
+ ; CHECK: [[OR36:%[0-9]+]]:_(s32) = G_OR [[OR35]], [[SHL36]]
+ ; CHECK: [[AND43:%[0-9]+]]:_(s32) = G_AND [[LSHR37]], [[C14]]
; CHECK: [[SHL37:%[0-9]+]]:_(s32) = G_SHL [[AND43]], [[C5]](s64)
- ; CHECK: [[COPY109:%[0-9]+]]:_(s32) = COPY [[OR36]](s32)
- ; CHECK: [[COPY110:%[0-9]+]]:_(s32) = COPY [[SHL37]](s32)
- ; CHECK: [[OR37:%[0-9]+]]:_(s32) = G_OR [[COPY109]], [[COPY110]]
- ; CHECK: [[COPY111:%[0-9]+]]:_(s32) = COPY [[LSHR38]](s32)
- ; CHECK: [[AND44:%[0-9]+]]:_(s32) = G_AND [[COPY111]], [[C14]]
+ ; CHECK: [[OR37:%[0-9]+]]:_(s32) = G_OR [[OR36]], [[SHL37]]
+ ; CHECK: [[AND44:%[0-9]+]]:_(s32) = G_AND [[LSHR38]], [[C14]]
; CHECK: [[SHL38:%[0-9]+]]:_(s32) = G_SHL [[AND44]], [[C7]](s64)
- ; CHECK: [[COPY112:%[0-9]+]]:_(s32) = COPY [[OR37]](s32)
- ; CHECK: [[COPY113:%[0-9]+]]:_(s32) = COPY [[SHL38]](s32)
- ; CHECK: [[OR38:%[0-9]+]]:_(s32) = G_OR [[COPY112]], [[COPY113]]
- ; CHECK: [[COPY114:%[0-9]+]]:_(s32) = COPY [[LSHR39]](s32)
- ; CHECK: [[AND45:%[0-9]+]]:_(s32) = G_AND [[COPY114]], [[C14]]
+ ; CHECK: [[OR38:%[0-9]+]]:_(s32) = G_OR [[OR37]], [[SHL38]]
+ ; CHECK: [[AND45:%[0-9]+]]:_(s32) = G_AND [[LSHR39]], [[C14]]
; CHECK: [[SHL39:%[0-9]+]]:_(s32) = G_SHL [[AND45]], [[C9]](s64)
- ; CHECK: [[COPY115:%[0-9]+]]:_(s32) = COPY [[OR38]](s32)
- ; CHECK: [[COPY116:%[0-9]+]]:_(s32) = COPY [[SHL39]](s32)
- ; CHECK: [[OR39:%[0-9]+]]:_(s32) = G_OR [[COPY115]], [[COPY116]]
- ; CHECK: [[COPY117:%[0-9]+]]:_(s32) = COPY [[LSHR40]](s32)
- ; CHECK: [[AND46:%[0-9]+]]:_(s32) = G_AND [[COPY117]], [[C14]]
+ ; CHECK: [[OR39:%[0-9]+]]:_(s32) = G_OR [[OR38]], [[SHL39]]
+ ; CHECK: [[AND46:%[0-9]+]]:_(s32) = G_AND [[LSHR40]], [[C14]]
; CHECK: [[SHL40:%[0-9]+]]:_(s32) = G_SHL [[AND46]], [[C11]](s64)
- ; CHECK: [[COPY118:%[0-9]+]]:_(s32) = COPY [[OR39]](s32)
- ; CHECK: [[COPY119:%[0-9]+]]:_(s32) = COPY [[SHL40]](s32)
- ; CHECK: [[OR40:%[0-9]+]]:_(s32) = G_OR [[COPY118]], [[COPY119]]
- ; CHECK: [[COPY120:%[0-9]+]]:_(s32) = COPY [[LSHR41]](s32)
- ; CHECK: [[AND47:%[0-9]+]]:_(s32) = G_AND [[COPY120]], [[C14]]
+ ; CHECK: [[OR40:%[0-9]+]]:_(s32) = G_OR [[OR39]], [[SHL40]]
+ ; CHECK: [[AND47:%[0-9]+]]:_(s32) = G_AND [[LSHR41]], [[C14]]
; CHECK: [[SHL41:%[0-9]+]]:_(s32) = G_SHL [[AND47]], [[C13]](s64)
- ; CHECK: [[COPY121:%[0-9]+]]:_(s32) = COPY [[OR40]](s32)
- ; CHECK: [[COPY122:%[0-9]+]]:_(s32) = COPY [[SHL41]](s32)
- ; CHECK: [[OR41:%[0-9]+]]:_(s32) = G_OR [[COPY121]], [[COPY122]]
+ ; CHECK: [[OR41:%[0-9]+]]:_(s32) = G_OR [[OR40]], [[SHL41]]
; CHECK: [[TRUNC5:%[0-9]+]]:_(s8) = G_TRUNC [[OR41]](s32)
- ; CHECK: [[COPY123:%[0-9]+]]:_(s32) = COPY [[LSHR42]](s32)
- ; CHECK: [[AND48:%[0-9]+]]:_(s32) = G_AND [[COPY123]], [[C14]]
+ ; CHECK: [[AND48:%[0-9]+]]:_(s32) = G_AND [[LSHR42]], [[C14]]
; CHECK: [[SHL42:%[0-9]+]]:_(s32) = G_SHL [[AND48]], [[C1]](s64)
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
; CHECK: [[AND49:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[C14]]
- ; CHECK: [[COPY124:%[0-9]+]]:_(s32) = COPY [[SHL42]](s32)
- ; CHECK: [[OR42:%[0-9]+]]:_(s32) = G_OR [[AND49]], [[COPY124]]
- ; CHECK: [[COPY125:%[0-9]+]]:_(s32) = COPY [[LSHR43]](s32)
- ; CHECK: [[AND50:%[0-9]+]]:_(s32) = G_AND [[COPY125]], [[C14]]
+ ; CHECK: [[OR42:%[0-9]+]]:_(s32) = G_OR [[AND49]], [[SHL42]]
+ ; CHECK: [[AND50:%[0-9]+]]:_(s32) = G_AND [[LSHR43]], [[C14]]
; CHECK: [[SHL43:%[0-9]+]]:_(s32) = G_SHL [[AND50]], [[C3]](s64)
- ; CHECK: [[COPY126:%[0-9]+]]:_(s32) = COPY [[OR42]](s32)
- ; CHECK: [[COPY127:%[0-9]+]]:_(s32) = COPY [[SHL43]](s32)
- ; CHECK: [[OR43:%[0-9]+]]:_(s32) = G_OR [[COPY126]], [[COPY127]]
- ; CHECK: [[COPY128:%[0-9]+]]:_(s32) = COPY [[LSHR44]](s32)
- ; CHECK: [[AND51:%[0-9]+]]:_(s32) = G_AND [[COPY128]], [[C14]]
+ ; CHECK: [[OR43:%[0-9]+]]:_(s32) = G_OR [[OR42]], [[SHL43]]
+ ; CHECK: [[AND51:%[0-9]+]]:_(s32) = G_AND [[LSHR44]], [[C14]]
; CHECK: [[SHL44:%[0-9]+]]:_(s32) = G_SHL [[AND51]], [[C5]](s64)
- ; CHECK: [[COPY129:%[0-9]+]]:_(s32) = COPY [[OR43]](s32)
- ; CHECK: [[COPY130:%[0-9]+]]:_(s32) = COPY [[SHL44]](s32)
- ; CHECK: [[OR44:%[0-9]+]]:_(s32) = G_OR [[COPY129]], [[COPY130]]
- ; CHECK: [[COPY131:%[0-9]+]]:_(s32) = COPY [[LSHR45]](s32)
- ; CHECK: [[AND52:%[0-9]+]]:_(s32) = G_AND [[COPY131]], [[C14]]
+ ; CHECK: [[OR44:%[0-9]+]]:_(s32) = G_OR [[OR43]], [[SHL44]]
+ ; CHECK: [[AND52:%[0-9]+]]:_(s32) = G_AND [[LSHR45]], [[C14]]
; CHECK: [[SHL45:%[0-9]+]]:_(s32) = G_SHL [[AND52]], [[C7]](s64)
- ; CHECK: [[COPY132:%[0-9]+]]:_(s32) = COPY [[OR44]](s32)
- ; CHECK: [[COPY133:%[0-9]+]]:_(s32) = COPY [[SHL45]](s32)
- ; CHECK: [[OR45:%[0-9]+]]:_(s32) = G_OR [[COPY132]], [[COPY133]]
- ; CHECK: [[COPY134:%[0-9]+]]:_(s32) = COPY [[LSHR46]](s32)
- ; CHECK: [[AND53:%[0-9]+]]:_(s32) = G_AND [[COPY134]], [[C14]]
+ ; CHECK: [[OR45:%[0-9]+]]:_(s32) = G_OR [[OR44]], [[SHL45]]
+ ; CHECK: [[AND53:%[0-9]+]]:_(s32) = G_AND [[LSHR46]], [[C14]]
; CHECK: [[SHL46:%[0-9]+]]:_(s32) = G_SHL [[AND53]], [[C9]](s64)
- ; CHECK: [[COPY135:%[0-9]+]]:_(s32) = COPY [[OR45]](s32)
- ; CHECK: [[COPY136:%[0-9]+]]:_(s32) = COPY [[SHL46]](s32)
- ; CHECK: [[OR46:%[0-9]+]]:_(s32) = G_OR [[COPY135]], [[COPY136]]
- ; CHECK: [[COPY137:%[0-9]+]]:_(s32) = COPY [[LSHR47]](s32)
- ; CHECK: [[AND54:%[0-9]+]]:_(s32) = G_AND [[COPY137]], [[C14]]
+ ; CHECK: [[OR46:%[0-9]+]]:_(s32) = G_OR [[OR45]], [[SHL46]]
+ ; CHECK: [[AND54:%[0-9]+]]:_(s32) = G_AND [[LSHR47]], [[C14]]
; CHECK: [[SHL47:%[0-9]+]]:_(s32) = G_SHL [[AND54]], [[C11]](s64)
- ; CHECK: [[COPY138:%[0-9]+]]:_(s32) = COPY [[OR46]](s32)
- ; CHECK: [[COPY139:%[0-9]+]]:_(s32) = COPY [[SHL47]](s32)
- ; CHECK: [[OR47:%[0-9]+]]:_(s32) = G_OR [[COPY138]], [[COPY139]]
- ; CHECK: [[COPY140:%[0-9]+]]:_(s32) = COPY [[LSHR48]](s32)
- ; CHECK: [[AND55:%[0-9]+]]:_(s32) = G_AND [[COPY140]], [[C14]]
+ ; CHECK: [[OR47:%[0-9]+]]:_(s32) = G_OR [[OR46]], [[SHL47]]
+ ; CHECK: [[AND55:%[0-9]+]]:_(s32) = G_AND [[LSHR48]], [[C14]]
; CHECK: [[SHL48:%[0-9]+]]:_(s32) = G_SHL [[AND55]], [[C13]](s64)
- ; CHECK: [[COPY141:%[0-9]+]]:_(s32) = COPY [[OR47]](s32)
- ; CHECK: [[COPY142:%[0-9]+]]:_(s32) = COPY [[SHL48]](s32)
- ; CHECK: [[OR48:%[0-9]+]]:_(s32) = G_OR [[COPY141]], [[COPY142]]
+ ; CHECK: [[OR48:%[0-9]+]]:_(s32) = G_OR [[OR47]], [[SHL48]]
; CHECK: [[TRUNC6:%[0-9]+]]:_(s8) = G_TRUNC [[OR48]](s32)
- ; CHECK: [[COPY143:%[0-9]+]]:_(s32) = COPY [[LSHR49]](s32)
- ; CHECK: [[AND56:%[0-9]+]]:_(s32) = G_AND [[COPY143]], [[C14]]
+ ; CHECK: [[AND56:%[0-9]+]]:_(s32) = G_AND [[LSHR49]], [[C14]]
; CHECK: [[SHL49:%[0-9]+]]:_(s32) = G_SHL [[AND56]], [[C1]](s64)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
; CHECK: [[AND57:%[0-9]+]]:_(s32) = G_AND [[ANYEXT7]], [[C14]]
- ; CHECK: [[COPY144:%[0-9]+]]:_(s32) = COPY [[SHL49]](s32)
- ; CHECK: [[OR49:%[0-9]+]]:_(s32) = G_OR [[AND57]], [[COPY144]]
- ; CHECK: [[COPY145:%[0-9]+]]:_(s32) = COPY [[LSHR50]](s32)
- ; CHECK: [[AND58:%[0-9]+]]:_(s32) = G_AND [[COPY145]], [[C14]]
+ ; CHECK: [[OR49:%[0-9]+]]:_(s32) = G_OR [[AND57]], [[SHL49]]
+ ; CHECK: [[AND58:%[0-9]+]]:_(s32) = G_AND [[LSHR50]], [[C14]]
; CHECK: [[SHL50:%[0-9]+]]:_(s32) = G_SHL [[AND58]], [[C3]](s64)
- ; CHECK: [[COPY146:%[0-9]+]]:_(s32) = COPY [[OR49]](s32)
- ; CHECK: [[COPY147:%[0-9]+]]:_(s32) = COPY [[SHL50]](s32)
- ; CHECK: [[OR50:%[0-9]+]]:_(s32) = G_OR [[COPY146]], [[COPY147]]
- ; CHECK: [[COPY148:%[0-9]+]]:_(s32) = COPY [[LSHR51]](s32)
- ; CHECK: [[AND59:%[0-9]+]]:_(s32) = G_AND [[COPY148]], [[C14]]
+ ; CHECK: [[OR50:%[0-9]+]]:_(s32) = G_OR [[OR49]], [[SHL50]]
+ ; CHECK: [[AND59:%[0-9]+]]:_(s32) = G_AND [[LSHR51]], [[C14]]
; CHECK: [[SHL51:%[0-9]+]]:_(s32) = G_SHL [[AND59]], [[C5]](s64)
- ; CHECK: [[COPY149:%[0-9]+]]:_(s32) = COPY [[OR50]](s32)
- ; CHECK: [[COPY150:%[0-9]+]]:_(s32) = COPY [[SHL51]](s32)
- ; CHECK: [[OR51:%[0-9]+]]:_(s32) = G_OR [[COPY149]], [[COPY150]]
- ; CHECK: [[COPY151:%[0-9]+]]:_(s32) = COPY [[LSHR52]](s32)
- ; CHECK: [[AND60:%[0-9]+]]:_(s32) = G_AND [[COPY151]], [[C14]]
+ ; CHECK: [[OR51:%[0-9]+]]:_(s32) = G_OR [[OR50]], [[SHL51]]
+ ; CHECK: [[AND60:%[0-9]+]]:_(s32) = G_AND [[LSHR52]], [[C14]]
; CHECK: [[SHL52:%[0-9]+]]:_(s32) = G_SHL [[AND60]], [[C7]](s64)
- ; CHECK: [[COPY152:%[0-9]+]]:_(s32) = COPY [[OR51]](s32)
- ; CHECK: [[COPY153:%[0-9]+]]:_(s32) = COPY [[SHL52]](s32)
- ; CHECK: [[OR52:%[0-9]+]]:_(s32) = G_OR [[COPY152]], [[COPY153]]
- ; CHECK: [[COPY154:%[0-9]+]]:_(s32) = COPY [[LSHR53]](s32)
- ; CHECK: [[AND61:%[0-9]+]]:_(s32) = G_AND [[COPY154]], [[C14]]
+ ; CHECK: [[OR52:%[0-9]+]]:_(s32) = G_OR [[OR51]], [[SHL52]]
+ ; CHECK: [[AND61:%[0-9]+]]:_(s32) = G_AND [[LSHR53]], [[C14]]
; CHECK: [[SHL53:%[0-9]+]]:_(s32) = G_SHL [[AND61]], [[C9]](s64)
- ; CHECK: [[COPY155:%[0-9]+]]:_(s32) = COPY [[OR52]](s32)
- ; CHECK: [[COPY156:%[0-9]+]]:_(s32) = COPY [[SHL53]](s32)
- ; CHECK: [[OR53:%[0-9]+]]:_(s32) = G_OR [[COPY155]], [[COPY156]]
- ; CHECK: [[COPY157:%[0-9]+]]:_(s32) = COPY [[LSHR54]](s32)
- ; CHECK: [[AND62:%[0-9]+]]:_(s32) = G_AND [[COPY157]], [[C14]]
+ ; CHECK: [[OR53:%[0-9]+]]:_(s32) = G_OR [[OR52]], [[SHL53]]
+ ; CHECK: [[AND62:%[0-9]+]]:_(s32) = G_AND [[LSHR54]], [[C14]]
; CHECK: [[SHL54:%[0-9]+]]:_(s32) = G_SHL [[AND62]], [[C11]](s64)
- ; CHECK: [[COPY158:%[0-9]+]]:_(s32) = COPY [[OR53]](s32)
- ; CHECK: [[COPY159:%[0-9]+]]:_(s32) = COPY [[SHL54]](s32)
- ; CHECK: [[OR54:%[0-9]+]]:_(s32) = G_OR [[COPY158]], [[COPY159]]
- ; CHECK: [[COPY160:%[0-9]+]]:_(s32) = COPY [[LSHR55]](s32)
- ; CHECK: [[AND63:%[0-9]+]]:_(s32) = G_AND [[COPY160]], [[C14]]
+ ; CHECK: [[OR54:%[0-9]+]]:_(s32) = G_OR [[OR53]], [[SHL54]]
+ ; CHECK: [[AND63:%[0-9]+]]:_(s32) = G_AND [[LSHR55]], [[C14]]
; CHECK: [[SHL55:%[0-9]+]]:_(s32) = G_SHL [[AND63]], [[C13]](s64)
- ; CHECK: [[COPY161:%[0-9]+]]:_(s32) = COPY [[OR54]](s32)
- ; CHECK: [[COPY162:%[0-9]+]]:_(s32) = COPY [[SHL55]](s32)
- ; CHECK: [[OR55:%[0-9]+]]:_(s32) = G_OR [[COPY161]], [[COPY162]]
+ ; CHECK: [[OR55:%[0-9]+]]:_(s32) = G_OR [[OR54]], [[SHL55]]
; CHECK: [[TRUNC7:%[0-9]+]]:_(s8) = G_TRUNC [[OR55]](s32)
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[TRUNC]](s8), [[TRUNC1]](s8), [[TRUNC2]](s8), [[TRUNC3]](s8), [[TRUNC4]](s8), [[TRUNC5]](s8), [[TRUNC6]](s8), [[TRUNC7]](s8)
; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[COPY163:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL56:%[0-9]+]]:_(s32) = G_SHL [[COPY163]], [[C1]](s64)
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL56:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C1]](s64)
; CHECK: [[TRUNC8:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64)
; CHECK: [[AND64:%[0-9]+]]:_(s32) = G_AND [[TRUNC8]], [[C14]]
- ; CHECK: [[COPY164:%[0-9]+]]:_(s32) = COPY [[SHL56]](s32)
- ; CHECK: [[OR56:%[0-9]+]]:_(s32) = G_OR [[AND64]], [[COPY164]]
- ; CHECK: [[COPY165:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL57:%[0-9]+]]:_(s32) = G_SHL [[COPY165]], [[C3]](s64)
- ; CHECK: [[COPY166:%[0-9]+]]:_(s32) = COPY [[OR56]](s32)
- ; CHECK: [[COPY167:%[0-9]+]]:_(s32) = COPY [[SHL57]](s32)
- ; CHECK: [[OR57:%[0-9]+]]:_(s32) = G_OR [[COPY166]], [[COPY167]]
- ; CHECK: [[COPY168:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL58:%[0-9]+]]:_(s32) = G_SHL [[COPY168]], [[C5]](s64)
- ; CHECK: [[COPY169:%[0-9]+]]:_(s32) = COPY [[OR57]](s32)
- ; CHECK: [[COPY170:%[0-9]+]]:_(s32) = COPY [[SHL58]](s32)
- ; CHECK: [[OR58:%[0-9]+]]:_(s32) = G_OR [[COPY169]], [[COPY170]]
- ; CHECK: [[COPY171:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL59:%[0-9]+]]:_(s32) = G_SHL [[COPY171]], [[C7]](s64)
- ; CHECK: [[COPY172:%[0-9]+]]:_(s32) = COPY [[OR58]](s32)
- ; CHECK: [[COPY173:%[0-9]+]]:_(s32) = COPY [[SHL59]](s32)
- ; CHECK: [[OR59:%[0-9]+]]:_(s32) = G_OR [[COPY172]], [[COPY173]]
- ; CHECK: [[COPY174:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL60:%[0-9]+]]:_(s32) = G_SHL [[COPY174]], [[C9]](s64)
- ; CHECK: [[COPY175:%[0-9]+]]:_(s32) = COPY [[OR59]](s32)
- ; CHECK: [[COPY176:%[0-9]+]]:_(s32) = COPY [[SHL60]](s32)
- ; CHECK: [[OR60:%[0-9]+]]:_(s32) = G_OR [[COPY175]], [[COPY176]]
- ; CHECK: [[COPY177:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL61:%[0-9]+]]:_(s32) = G_SHL [[COPY177]], [[C11]](s64)
- ; CHECK: [[COPY178:%[0-9]+]]:_(s32) = COPY [[OR60]](s32)
- ; CHECK: [[COPY179:%[0-9]+]]:_(s32) = COPY [[SHL61]](s32)
- ; CHECK: [[OR61:%[0-9]+]]:_(s32) = G_OR [[COPY178]], [[COPY179]]
- ; CHECK: [[COPY180:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL62:%[0-9]+]]:_(s32) = G_SHL [[COPY180]], [[C13]](s64)
- ; CHECK: [[COPY181:%[0-9]+]]:_(s32) = COPY [[OR61]](s32)
- ; CHECK: [[COPY182:%[0-9]+]]:_(s32) = COPY [[SHL62]](s32)
- ; CHECK: [[OR62:%[0-9]+]]:_(s32) = G_OR [[COPY181]], [[COPY182]]
+ ; CHECK: [[OR56:%[0-9]+]]:_(s32) = G_OR [[AND64]], [[SHL56]]
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL57:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C3]](s64)
+ ; CHECK: [[OR57:%[0-9]+]]:_(s32) = G_OR [[OR56]], [[SHL57]]
+ ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL58:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C5]](s64)
+ ; CHECK: [[OR58:%[0-9]+]]:_(s32) = G_OR [[OR57]], [[SHL58]]
+ ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL59:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C7]](s64)
+ ; CHECK: [[OR59:%[0-9]+]]:_(s32) = G_OR [[OR58]], [[SHL59]]
+ ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL60:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C9]](s64)
+ ; CHECK: [[OR60:%[0-9]+]]:_(s32) = G_OR [[OR59]], [[SHL60]]
+ ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL61:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C11]](s64)
+ ; CHECK: [[OR61:%[0-9]+]]:_(s32) = G_OR [[OR60]], [[SHL61]]
+ ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL62:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C13]](s64)
+ ; CHECK: [[OR62:%[0-9]+]]:_(s32) = G_OR [[OR61]], [[SHL62]]
; CHECK: [[TRUNC9:%[0-9]+]]:_(s8) = G_TRUNC [[OR62]](s32)
- ; CHECK: [[COPY183:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL63:%[0-9]+]]:_(s32) = G_SHL [[COPY183]], [[C1]](s64)
- ; CHECK: [[COPY184:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[COPY185:%[0-9]+]]:_(s32) = COPY [[SHL63]](s32)
- ; CHECK: [[OR63:%[0-9]+]]:_(s32) = G_OR [[COPY184]], [[COPY185]]
- ; CHECK: [[COPY186:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL64:%[0-9]+]]:_(s32) = G_SHL [[COPY186]], [[C3]](s64)
- ; CHECK: [[COPY187:%[0-9]+]]:_(s32) = COPY [[OR63]](s32)
- ; CHECK: [[COPY188:%[0-9]+]]:_(s32) = COPY [[SHL64]](s32)
- ; CHECK: [[OR64:%[0-9]+]]:_(s32) = G_OR [[COPY187]], [[COPY188]]
- ; CHECK: [[COPY189:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL65:%[0-9]+]]:_(s32) = G_SHL [[COPY189]], [[C5]](s64)
- ; CHECK: [[COPY190:%[0-9]+]]:_(s32) = COPY [[OR64]](s32)
- ; CHECK: [[COPY191:%[0-9]+]]:_(s32) = COPY [[SHL65]](s32)
- ; CHECK: [[OR65:%[0-9]+]]:_(s32) = G_OR [[COPY190]], [[COPY191]]
- ; CHECK: [[COPY192:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL66:%[0-9]+]]:_(s32) = G_SHL [[COPY192]], [[C7]](s64)
- ; CHECK: [[COPY193:%[0-9]+]]:_(s32) = COPY [[OR65]](s32)
- ; CHECK: [[COPY194:%[0-9]+]]:_(s32) = COPY [[SHL66]](s32)
- ; CHECK: [[OR66:%[0-9]+]]:_(s32) = G_OR [[COPY193]], [[COPY194]]
- ; CHECK: [[COPY195:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL67:%[0-9]+]]:_(s32) = G_SHL [[COPY195]], [[C9]](s64)
- ; CHECK: [[COPY196:%[0-9]+]]:_(s32) = COPY [[OR66]](s32)
- ; CHECK: [[COPY197:%[0-9]+]]:_(s32) = COPY [[SHL67]](s32)
- ; CHECK: [[OR67:%[0-9]+]]:_(s32) = G_OR [[COPY196]], [[COPY197]]
- ; CHECK: [[COPY198:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL68:%[0-9]+]]:_(s32) = G_SHL [[COPY198]], [[C11]](s64)
- ; CHECK: [[COPY199:%[0-9]+]]:_(s32) = COPY [[OR67]](s32)
- ; CHECK: [[COPY200:%[0-9]+]]:_(s32) = COPY [[SHL68]](s32)
- ; CHECK: [[OR68:%[0-9]+]]:_(s32) = G_OR [[COPY199]], [[COPY200]]
- ; CHECK: [[COPY201:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL69:%[0-9]+]]:_(s32) = G_SHL [[COPY201]], [[C13]](s64)
- ; CHECK: [[COPY202:%[0-9]+]]:_(s32) = COPY [[OR68]](s32)
- ; CHECK: [[COPY203:%[0-9]+]]:_(s32) = COPY [[SHL69]](s32)
- ; CHECK: [[OR69:%[0-9]+]]:_(s32) = G_OR [[COPY202]], [[COPY203]]
+ ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL63:%[0-9]+]]:_(s32) = G_SHL [[COPY10]], [[C1]](s64)
+ ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[OR63:%[0-9]+]]:_(s32) = G_OR [[COPY11]], [[SHL63]]
+ ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL64:%[0-9]+]]:_(s32) = G_SHL [[COPY12]], [[C3]](s64)
+ ; CHECK: [[OR64:%[0-9]+]]:_(s32) = G_OR [[OR63]], [[SHL64]]
+ ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL65:%[0-9]+]]:_(s32) = G_SHL [[COPY13]], [[C5]](s64)
+ ; CHECK: [[OR65:%[0-9]+]]:_(s32) = G_OR [[OR64]], [[SHL65]]
+ ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL66:%[0-9]+]]:_(s32) = G_SHL [[COPY14]], [[C7]](s64)
+ ; CHECK: [[OR66:%[0-9]+]]:_(s32) = G_OR [[OR65]], [[SHL66]]
+ ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL67:%[0-9]+]]:_(s32) = G_SHL [[COPY15]], [[C9]](s64)
+ ; CHECK: [[OR67:%[0-9]+]]:_(s32) = G_OR [[OR66]], [[SHL67]]
+ ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL68:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C11]](s64)
+ ; CHECK: [[OR68:%[0-9]+]]:_(s32) = G_OR [[OR67]], [[SHL68]]
+ ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL69:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C13]](s64)
+ ; CHECK: [[OR69:%[0-9]+]]:_(s32) = G_OR [[OR68]], [[SHL69]]
; CHECK: [[TRUNC10:%[0-9]+]]:_(s8) = G_TRUNC [[OR69]](s32)
- ; CHECK: [[COPY204:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL70:%[0-9]+]]:_(s32) = G_SHL [[COPY204]], [[C1]](s64)
- ; CHECK: [[COPY205:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[COPY206:%[0-9]+]]:_(s32) = COPY [[SHL70]](s32)
- ; CHECK: [[OR70:%[0-9]+]]:_(s32) = G_OR [[COPY205]], [[COPY206]]
- ; CHECK: [[COPY207:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL71:%[0-9]+]]:_(s32) = G_SHL [[COPY207]], [[C3]](s64)
- ; CHECK: [[COPY208:%[0-9]+]]:_(s32) = COPY [[OR70]](s32)
- ; CHECK: [[COPY209:%[0-9]+]]:_(s32) = COPY [[SHL71]](s32)
- ; CHECK: [[OR71:%[0-9]+]]:_(s32) = G_OR [[COPY208]], [[COPY209]]
- ; CHECK: [[COPY210:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL72:%[0-9]+]]:_(s32) = G_SHL [[COPY210]], [[C5]](s64)
- ; CHECK: [[COPY211:%[0-9]+]]:_(s32) = COPY [[OR71]](s32)
- ; CHECK: [[COPY212:%[0-9]+]]:_(s32) = COPY [[SHL72]](s32)
- ; CHECK: [[OR72:%[0-9]+]]:_(s32) = G_OR [[COPY211]], [[COPY212]]
- ; CHECK: [[COPY213:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL73:%[0-9]+]]:_(s32) = G_SHL [[COPY213]], [[C7]](s64)
- ; CHECK: [[COPY214:%[0-9]+]]:_(s32) = COPY [[OR72]](s32)
- ; CHECK: [[COPY215:%[0-9]+]]:_(s32) = COPY [[SHL73]](s32)
- ; CHECK: [[OR73:%[0-9]+]]:_(s32) = G_OR [[COPY214]], [[COPY215]]
- ; CHECK: [[COPY216:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL74:%[0-9]+]]:_(s32) = G_SHL [[COPY216]], [[C9]](s64)
- ; CHECK: [[COPY217:%[0-9]+]]:_(s32) = COPY [[OR73]](s32)
- ; CHECK: [[COPY218:%[0-9]+]]:_(s32) = COPY [[SHL74]](s32)
- ; CHECK: [[OR74:%[0-9]+]]:_(s32) = G_OR [[COPY217]], [[COPY218]]
- ; CHECK: [[COPY219:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL75:%[0-9]+]]:_(s32) = G_SHL [[COPY219]], [[C11]](s64)
- ; CHECK: [[COPY220:%[0-9]+]]:_(s32) = COPY [[OR74]](s32)
- ; CHECK: [[COPY221:%[0-9]+]]:_(s32) = COPY [[SHL75]](s32)
- ; CHECK: [[OR75:%[0-9]+]]:_(s32) = G_OR [[COPY220]], [[COPY221]]
- ; CHECK: [[COPY222:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL76:%[0-9]+]]:_(s32) = G_SHL [[COPY222]], [[C13]](s64)
- ; CHECK: [[COPY223:%[0-9]+]]:_(s32) = COPY [[OR75]](s32)
- ; CHECK: [[COPY224:%[0-9]+]]:_(s32) = COPY [[SHL76]](s32)
- ; CHECK: [[OR76:%[0-9]+]]:_(s32) = G_OR [[COPY223]], [[COPY224]]
+ ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL70:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C1]](s64)
+ ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[OR70:%[0-9]+]]:_(s32) = G_OR [[COPY19]], [[SHL70]]
+ ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL71:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C3]](s64)
+ ; CHECK: [[OR71:%[0-9]+]]:_(s32) = G_OR [[OR70]], [[SHL71]]
+ ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL72:%[0-9]+]]:_(s32) = G_SHL [[COPY21]], [[C5]](s64)
+ ; CHECK: [[OR72:%[0-9]+]]:_(s32) = G_OR [[OR71]], [[SHL72]]
+ ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL73:%[0-9]+]]:_(s32) = G_SHL [[COPY22]], [[C7]](s64)
+ ; CHECK: [[OR73:%[0-9]+]]:_(s32) = G_OR [[OR72]], [[SHL73]]
+ ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL74:%[0-9]+]]:_(s32) = G_SHL [[COPY23]], [[C9]](s64)
+ ; CHECK: [[OR74:%[0-9]+]]:_(s32) = G_OR [[OR73]], [[SHL74]]
+ ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL75:%[0-9]+]]:_(s32) = G_SHL [[COPY24]], [[C11]](s64)
+ ; CHECK: [[OR75:%[0-9]+]]:_(s32) = G_OR [[OR74]], [[SHL75]]
+ ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL76:%[0-9]+]]:_(s32) = G_SHL [[COPY25]], [[C13]](s64)
+ ; CHECK: [[OR76:%[0-9]+]]:_(s32) = G_OR [[OR75]], [[SHL76]]
; CHECK: [[TRUNC11:%[0-9]+]]:_(s8) = G_TRUNC [[OR76]](s32)
- ; CHECK: [[COPY225:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL77:%[0-9]+]]:_(s32) = G_SHL [[COPY225]], [[C1]](s64)
- ; CHECK: [[COPY226:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[COPY227:%[0-9]+]]:_(s32) = COPY [[SHL77]](s32)
- ; CHECK: [[OR77:%[0-9]+]]:_(s32) = G_OR [[COPY226]], [[COPY227]]
- ; CHECK: [[COPY228:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL78:%[0-9]+]]:_(s32) = G_SHL [[COPY228]], [[C3]](s64)
- ; CHECK: [[COPY229:%[0-9]+]]:_(s32) = COPY [[OR77]](s32)
- ; CHECK: [[COPY230:%[0-9]+]]:_(s32) = COPY [[SHL78]](s32)
- ; CHECK: [[OR78:%[0-9]+]]:_(s32) = G_OR [[COPY229]], [[COPY230]]
- ; CHECK: [[COPY231:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL79:%[0-9]+]]:_(s32) = G_SHL [[COPY231]], [[C5]](s64)
- ; CHECK: [[COPY232:%[0-9]+]]:_(s32) = COPY [[OR78]](s32)
- ; CHECK: [[COPY233:%[0-9]+]]:_(s32) = COPY [[SHL79]](s32)
- ; CHECK: [[OR79:%[0-9]+]]:_(s32) = G_OR [[COPY232]], [[COPY233]]
- ; CHECK: [[COPY234:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL80:%[0-9]+]]:_(s32) = G_SHL [[COPY234]], [[C7]](s64)
- ; CHECK: [[COPY235:%[0-9]+]]:_(s32) = COPY [[OR79]](s32)
- ; CHECK: [[COPY236:%[0-9]+]]:_(s32) = COPY [[SHL80]](s32)
- ; CHECK: [[OR80:%[0-9]+]]:_(s32) = G_OR [[COPY235]], [[COPY236]]
- ; CHECK: [[COPY237:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL81:%[0-9]+]]:_(s32) = G_SHL [[COPY237]], [[C9]](s64)
- ; CHECK: [[COPY238:%[0-9]+]]:_(s32) = COPY [[OR80]](s32)
- ; CHECK: [[COPY239:%[0-9]+]]:_(s32) = COPY [[SHL81]](s32)
- ; CHECK: [[OR81:%[0-9]+]]:_(s32) = G_OR [[COPY238]], [[COPY239]]
- ; CHECK: [[COPY240:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL82:%[0-9]+]]:_(s32) = G_SHL [[COPY240]], [[C11]](s64)
- ; CHECK: [[COPY241:%[0-9]+]]:_(s32) = COPY [[OR81]](s32)
- ; CHECK: [[COPY242:%[0-9]+]]:_(s32) = COPY [[SHL82]](s32)
- ; CHECK: [[OR82:%[0-9]+]]:_(s32) = G_OR [[COPY241]], [[COPY242]]
- ; CHECK: [[COPY243:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL83:%[0-9]+]]:_(s32) = G_SHL [[COPY243]], [[C13]](s64)
- ; CHECK: [[COPY244:%[0-9]+]]:_(s32) = COPY [[OR82]](s32)
- ; CHECK: [[COPY245:%[0-9]+]]:_(s32) = COPY [[SHL83]](s32)
- ; CHECK: [[OR83:%[0-9]+]]:_(s32) = G_OR [[COPY244]], [[COPY245]]
+ ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL77:%[0-9]+]]:_(s32) = G_SHL [[COPY26]], [[C1]](s64)
+ ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[OR77:%[0-9]+]]:_(s32) = G_OR [[COPY27]], [[SHL77]]
+ ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL78:%[0-9]+]]:_(s32) = G_SHL [[COPY28]], [[C3]](s64)
+ ; CHECK: [[OR78:%[0-9]+]]:_(s32) = G_OR [[OR77]], [[SHL78]]
+ ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL79:%[0-9]+]]:_(s32) = G_SHL [[COPY29]], [[C5]](s64)
+ ; CHECK: [[OR79:%[0-9]+]]:_(s32) = G_OR [[OR78]], [[SHL79]]
+ ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL80:%[0-9]+]]:_(s32) = G_SHL [[COPY30]], [[C7]](s64)
+ ; CHECK: [[OR80:%[0-9]+]]:_(s32) = G_OR [[OR79]], [[SHL80]]
+ ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL81:%[0-9]+]]:_(s32) = G_SHL [[COPY31]], [[C9]](s64)
+ ; CHECK: [[OR81:%[0-9]+]]:_(s32) = G_OR [[OR80]], [[SHL81]]
+ ; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL82:%[0-9]+]]:_(s32) = G_SHL [[COPY32]], [[C11]](s64)
+ ; CHECK: [[OR82:%[0-9]+]]:_(s32) = G_OR [[OR81]], [[SHL82]]
+ ; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL83:%[0-9]+]]:_(s32) = G_SHL [[COPY33]], [[C13]](s64)
+ ; CHECK: [[OR83:%[0-9]+]]:_(s32) = G_OR [[OR82]], [[SHL83]]
; CHECK: [[TRUNC12:%[0-9]+]]:_(s8) = G_TRUNC [[OR83]](s32)
- ; CHECK: [[COPY246:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL84:%[0-9]+]]:_(s32) = G_SHL [[COPY246]], [[C1]](s64)
- ; CHECK: [[COPY247:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[COPY248:%[0-9]+]]:_(s32) = COPY [[SHL84]](s32)
- ; CHECK: [[OR84:%[0-9]+]]:_(s32) = G_OR [[COPY247]], [[COPY248]]
- ; CHECK: [[COPY249:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL85:%[0-9]+]]:_(s32) = G_SHL [[COPY249]], [[C3]](s64)
- ; CHECK: [[COPY250:%[0-9]+]]:_(s32) = COPY [[OR84]](s32)
- ; CHECK: [[COPY251:%[0-9]+]]:_(s32) = COPY [[SHL85]](s32)
- ; CHECK: [[OR85:%[0-9]+]]:_(s32) = G_OR [[COPY250]], [[COPY251]]
- ; CHECK: [[COPY252:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL86:%[0-9]+]]:_(s32) = G_SHL [[COPY252]], [[C5]](s64)
- ; CHECK: [[COPY253:%[0-9]+]]:_(s32) = COPY [[OR85]](s32)
- ; CHECK: [[COPY254:%[0-9]+]]:_(s32) = COPY [[SHL86]](s32)
- ; CHECK: [[OR86:%[0-9]+]]:_(s32) = G_OR [[COPY253]], [[COPY254]]
- ; CHECK: [[COPY255:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL87:%[0-9]+]]:_(s32) = G_SHL [[COPY255]], [[C7]](s64)
- ; CHECK: [[COPY256:%[0-9]+]]:_(s32) = COPY [[OR86]](s32)
- ; CHECK: [[COPY257:%[0-9]+]]:_(s32) = COPY [[SHL87]](s32)
- ; CHECK: [[OR87:%[0-9]+]]:_(s32) = G_OR [[COPY256]], [[COPY257]]
- ; CHECK: [[COPY258:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL88:%[0-9]+]]:_(s32) = G_SHL [[COPY258]], [[C9]](s64)
- ; CHECK: [[COPY259:%[0-9]+]]:_(s32) = COPY [[OR87]](s32)
- ; CHECK: [[COPY260:%[0-9]+]]:_(s32) = COPY [[SHL88]](s32)
- ; CHECK: [[OR88:%[0-9]+]]:_(s32) = G_OR [[COPY259]], [[COPY260]]
- ; CHECK: [[COPY261:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL89:%[0-9]+]]:_(s32) = G_SHL [[COPY261]], [[C11]](s64)
- ; CHECK: [[COPY262:%[0-9]+]]:_(s32) = COPY [[OR88]](s32)
- ; CHECK: [[COPY263:%[0-9]+]]:_(s32) = COPY [[SHL89]](s32)
- ; CHECK: [[OR89:%[0-9]+]]:_(s32) = G_OR [[COPY262]], [[COPY263]]
- ; CHECK: [[COPY264:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL90:%[0-9]+]]:_(s32) = G_SHL [[COPY264]], [[C13]](s64)
- ; CHECK: [[COPY265:%[0-9]+]]:_(s32) = COPY [[OR89]](s32)
- ; CHECK: [[COPY266:%[0-9]+]]:_(s32) = COPY [[SHL90]](s32)
- ; CHECK: [[OR90:%[0-9]+]]:_(s32) = G_OR [[COPY265]], [[COPY266]]
+ ; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL84:%[0-9]+]]:_(s32) = G_SHL [[COPY34]], [[C1]](s64)
+ ; CHECK: [[COPY35:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[OR84:%[0-9]+]]:_(s32) = G_OR [[COPY35]], [[SHL84]]
+ ; CHECK: [[COPY36:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL85:%[0-9]+]]:_(s32) = G_SHL [[COPY36]], [[C3]](s64)
+ ; CHECK: [[OR85:%[0-9]+]]:_(s32) = G_OR [[OR84]], [[SHL85]]
+ ; CHECK: [[COPY37:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL86:%[0-9]+]]:_(s32) = G_SHL [[COPY37]], [[C5]](s64)
+ ; CHECK: [[OR86:%[0-9]+]]:_(s32) = G_OR [[OR85]], [[SHL86]]
+ ; CHECK: [[COPY38:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL87:%[0-9]+]]:_(s32) = G_SHL [[COPY38]], [[C7]](s64)
+ ; CHECK: [[OR87:%[0-9]+]]:_(s32) = G_OR [[OR86]], [[SHL87]]
+ ; CHECK: [[COPY39:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL88:%[0-9]+]]:_(s32) = G_SHL [[COPY39]], [[C9]](s64)
+ ; CHECK: [[OR88:%[0-9]+]]:_(s32) = G_OR [[OR87]], [[SHL88]]
+ ; CHECK: [[COPY40:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL89:%[0-9]+]]:_(s32) = G_SHL [[COPY40]], [[C11]](s64)
+ ; CHECK: [[OR89:%[0-9]+]]:_(s32) = G_OR [[OR88]], [[SHL89]]
+ ; CHECK: [[COPY41:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL90:%[0-9]+]]:_(s32) = G_SHL [[COPY41]], [[C13]](s64)
+ ; CHECK: [[OR90:%[0-9]+]]:_(s32) = G_OR [[OR89]], [[SHL90]]
; CHECK: [[TRUNC13:%[0-9]+]]:_(s8) = G_TRUNC [[OR90]](s32)
- ; CHECK: [[COPY267:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL91:%[0-9]+]]:_(s32) = G_SHL [[COPY267]], [[C1]](s64)
- ; CHECK: [[COPY268:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[COPY269:%[0-9]+]]:_(s32) = COPY [[SHL91]](s32)
- ; CHECK: [[OR91:%[0-9]+]]:_(s32) = G_OR [[COPY268]], [[COPY269]]
- ; CHECK: [[COPY270:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL92:%[0-9]+]]:_(s32) = G_SHL [[COPY270]], [[C3]](s64)
- ; CHECK: [[COPY271:%[0-9]+]]:_(s32) = COPY [[OR91]](s32)
- ; CHECK: [[COPY272:%[0-9]+]]:_(s32) = COPY [[SHL92]](s32)
- ; CHECK: [[OR92:%[0-9]+]]:_(s32) = G_OR [[COPY271]], [[COPY272]]
- ; CHECK: [[COPY273:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL93:%[0-9]+]]:_(s32) = G_SHL [[COPY273]], [[C5]](s64)
- ; CHECK: [[COPY274:%[0-9]+]]:_(s32) = COPY [[OR92]](s32)
- ; CHECK: [[COPY275:%[0-9]+]]:_(s32) = COPY [[SHL93]](s32)
- ; CHECK: [[OR93:%[0-9]+]]:_(s32) = G_OR [[COPY274]], [[COPY275]]
- ; CHECK: [[COPY276:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL94:%[0-9]+]]:_(s32) = G_SHL [[COPY276]], [[C7]](s64)
- ; CHECK: [[COPY277:%[0-9]+]]:_(s32) = COPY [[OR93]](s32)
- ; CHECK: [[COPY278:%[0-9]+]]:_(s32) = COPY [[SHL94]](s32)
- ; CHECK: [[OR94:%[0-9]+]]:_(s32) = G_OR [[COPY277]], [[COPY278]]
- ; CHECK: [[COPY279:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL95:%[0-9]+]]:_(s32) = G_SHL [[COPY279]], [[C9]](s64)
- ; CHECK: [[COPY280:%[0-9]+]]:_(s32) = COPY [[OR94]](s32)
- ; CHECK: [[COPY281:%[0-9]+]]:_(s32) = COPY [[SHL95]](s32)
- ; CHECK: [[OR95:%[0-9]+]]:_(s32) = G_OR [[COPY280]], [[COPY281]]
- ; CHECK: [[COPY282:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL96:%[0-9]+]]:_(s32) = G_SHL [[COPY282]], [[C11]](s64)
- ; CHECK: [[COPY283:%[0-9]+]]:_(s32) = COPY [[OR95]](s32)
- ; CHECK: [[COPY284:%[0-9]+]]:_(s32) = COPY [[SHL96]](s32)
- ; CHECK: [[OR96:%[0-9]+]]:_(s32) = G_OR [[COPY283]], [[COPY284]]
- ; CHECK: [[COPY285:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL97:%[0-9]+]]:_(s32) = G_SHL [[COPY285]], [[C13]](s64)
- ; CHECK: [[COPY286:%[0-9]+]]:_(s32) = COPY [[OR96]](s32)
- ; CHECK: [[COPY287:%[0-9]+]]:_(s32) = COPY [[SHL97]](s32)
- ; CHECK: [[OR97:%[0-9]+]]:_(s32) = G_OR [[COPY286]], [[COPY287]]
+ ; CHECK: [[COPY42:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL91:%[0-9]+]]:_(s32) = G_SHL [[COPY42]], [[C1]](s64)
+ ; CHECK: [[COPY43:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[OR91:%[0-9]+]]:_(s32) = G_OR [[COPY43]], [[SHL91]]
+ ; CHECK: [[COPY44:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL92:%[0-9]+]]:_(s32) = G_SHL [[COPY44]], [[C3]](s64)
+ ; CHECK: [[OR92:%[0-9]+]]:_(s32) = G_OR [[OR91]], [[SHL92]]
+ ; CHECK: [[COPY45:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL93:%[0-9]+]]:_(s32) = G_SHL [[COPY45]], [[C5]](s64)
+ ; CHECK: [[OR93:%[0-9]+]]:_(s32) = G_OR [[OR92]], [[SHL93]]
+ ; CHECK: [[COPY46:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL94:%[0-9]+]]:_(s32) = G_SHL [[COPY46]], [[C7]](s64)
+ ; CHECK: [[OR94:%[0-9]+]]:_(s32) = G_OR [[OR93]], [[SHL94]]
+ ; CHECK: [[COPY47:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL95:%[0-9]+]]:_(s32) = G_SHL [[COPY47]], [[C9]](s64)
+ ; CHECK: [[OR95:%[0-9]+]]:_(s32) = G_OR [[OR94]], [[SHL95]]
+ ; CHECK: [[COPY48:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL96:%[0-9]+]]:_(s32) = G_SHL [[COPY48]], [[C11]](s64)
+ ; CHECK: [[OR96:%[0-9]+]]:_(s32) = G_OR [[OR95]], [[SHL96]]
+ ; CHECK: [[COPY49:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL97:%[0-9]+]]:_(s32) = G_SHL [[COPY49]], [[C13]](s64)
+ ; CHECK: [[OR97:%[0-9]+]]:_(s32) = G_OR [[OR96]], [[SHL97]]
; CHECK: [[TRUNC14:%[0-9]+]]:_(s8) = G_TRUNC [[OR97]](s32)
- ; CHECK: [[COPY288:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL98:%[0-9]+]]:_(s32) = G_SHL [[COPY288]], [[C1]](s64)
- ; CHECK: [[COPY289:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[COPY290:%[0-9]+]]:_(s32) = COPY [[SHL98]](s32)
- ; CHECK: [[OR98:%[0-9]+]]:_(s32) = G_OR [[COPY289]], [[COPY290]]
- ; CHECK: [[COPY291:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL99:%[0-9]+]]:_(s32) = G_SHL [[COPY291]], [[C3]](s64)
- ; CHECK: [[COPY292:%[0-9]+]]:_(s32) = COPY [[OR98]](s32)
- ; CHECK: [[COPY293:%[0-9]+]]:_(s32) = COPY [[SHL99]](s32)
- ; CHECK: [[OR99:%[0-9]+]]:_(s32) = G_OR [[COPY292]], [[COPY293]]
- ; CHECK: [[COPY294:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL100:%[0-9]+]]:_(s32) = G_SHL [[COPY294]], [[C5]](s64)
- ; CHECK: [[COPY295:%[0-9]+]]:_(s32) = COPY [[OR99]](s32)
- ; CHECK: [[COPY296:%[0-9]+]]:_(s32) = COPY [[SHL100]](s32)
- ; CHECK: [[OR100:%[0-9]+]]:_(s32) = G_OR [[COPY295]], [[COPY296]]
- ; CHECK: [[COPY297:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL101:%[0-9]+]]:_(s32) = G_SHL [[COPY297]], [[C7]](s64)
- ; CHECK: [[COPY298:%[0-9]+]]:_(s32) = COPY [[OR100]](s32)
- ; CHECK: [[COPY299:%[0-9]+]]:_(s32) = COPY [[SHL101]](s32)
- ; CHECK: [[OR101:%[0-9]+]]:_(s32) = G_OR [[COPY298]], [[COPY299]]
- ; CHECK: [[COPY300:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL102:%[0-9]+]]:_(s32) = G_SHL [[COPY300]], [[C9]](s64)
- ; CHECK: [[COPY301:%[0-9]+]]:_(s32) = COPY [[OR101]](s32)
- ; CHECK: [[COPY302:%[0-9]+]]:_(s32) = COPY [[SHL102]](s32)
- ; CHECK: [[OR102:%[0-9]+]]:_(s32) = G_OR [[COPY301]], [[COPY302]]
- ; CHECK: [[COPY303:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL103:%[0-9]+]]:_(s32) = G_SHL [[COPY303]], [[C11]](s64)
- ; CHECK: [[COPY304:%[0-9]+]]:_(s32) = COPY [[OR102]](s32)
- ; CHECK: [[COPY305:%[0-9]+]]:_(s32) = COPY [[SHL103]](s32)
- ; CHECK: [[OR103:%[0-9]+]]:_(s32) = G_OR [[COPY304]], [[COPY305]]
- ; CHECK: [[COPY306:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL104:%[0-9]+]]:_(s32) = G_SHL [[COPY306]], [[C13]](s64)
- ; CHECK: [[COPY307:%[0-9]+]]:_(s32) = COPY [[OR103]](s32)
- ; CHECK: [[COPY308:%[0-9]+]]:_(s32) = COPY [[SHL104]](s32)
- ; CHECK: [[OR104:%[0-9]+]]:_(s32) = G_OR [[COPY307]], [[COPY308]]
+ ; CHECK: [[COPY50:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL98:%[0-9]+]]:_(s32) = G_SHL [[COPY50]], [[C1]](s64)
+ ; CHECK: [[COPY51:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[OR98:%[0-9]+]]:_(s32) = G_OR [[COPY51]], [[SHL98]]
+ ; CHECK: [[COPY52:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL99:%[0-9]+]]:_(s32) = G_SHL [[COPY52]], [[C3]](s64)
+ ; CHECK: [[OR99:%[0-9]+]]:_(s32) = G_OR [[OR98]], [[SHL99]]
+ ; CHECK: [[COPY53:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL100:%[0-9]+]]:_(s32) = G_SHL [[COPY53]], [[C5]](s64)
+ ; CHECK: [[OR100:%[0-9]+]]:_(s32) = G_OR [[OR99]], [[SHL100]]
+ ; CHECK: [[COPY54:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL101:%[0-9]+]]:_(s32) = G_SHL [[COPY54]], [[C7]](s64)
+ ; CHECK: [[OR101:%[0-9]+]]:_(s32) = G_OR [[OR100]], [[SHL101]]
+ ; CHECK: [[COPY55:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL102:%[0-9]+]]:_(s32) = G_SHL [[COPY55]], [[C9]](s64)
+ ; CHECK: [[OR102:%[0-9]+]]:_(s32) = G_OR [[OR101]], [[SHL102]]
+ ; CHECK: [[COPY56:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL103:%[0-9]+]]:_(s32) = G_SHL [[COPY56]], [[C11]](s64)
+ ; CHECK: [[OR103:%[0-9]+]]:_(s32) = G_OR [[OR102]], [[SHL103]]
+ ; CHECK: [[COPY57:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL104:%[0-9]+]]:_(s32) = G_SHL [[COPY57]], [[C13]](s64)
+ ; CHECK: [[OR104:%[0-9]+]]:_(s32) = G_OR [[OR103]], [[SHL104]]
; CHECK: [[TRUNC15:%[0-9]+]]:_(s8) = G_TRUNC [[OR104]](s32)
; CHECK: [[SHL105:%[0-9]+]]:_(s32) = G_SHL [[C15]], [[C1]](s64)
- ; CHECK: [[COPY309:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[COPY310:%[0-9]+]]:_(s32) = COPY [[SHL105]](s32)
- ; CHECK: [[OR105:%[0-9]+]]:_(s32) = G_OR [[COPY309]], [[COPY310]]
- ; CHECK: [[COPY311:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL106:%[0-9]+]]:_(s32) = G_SHL [[COPY311]], [[C3]](s64)
- ; CHECK: [[COPY312:%[0-9]+]]:_(s32) = COPY [[OR105]](s32)
- ; CHECK: [[COPY313:%[0-9]+]]:_(s32) = COPY [[SHL106]](s32)
- ; CHECK: [[OR106:%[0-9]+]]:_(s32) = G_OR [[COPY312]], [[COPY313]]
- ; CHECK: [[COPY314:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL107:%[0-9]+]]:_(s32) = G_SHL [[COPY314]], [[C5]](s64)
- ; CHECK: [[COPY315:%[0-9]+]]:_(s32) = COPY [[OR106]](s32)
- ; CHECK: [[COPY316:%[0-9]+]]:_(s32) = COPY [[SHL107]](s32)
- ; CHECK: [[OR107:%[0-9]+]]:_(s32) = G_OR [[COPY315]], [[COPY316]]
- ; CHECK: [[COPY317:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL108:%[0-9]+]]:_(s32) = G_SHL [[COPY317]], [[C7]](s64)
- ; CHECK: [[COPY318:%[0-9]+]]:_(s32) = COPY [[OR107]](s32)
- ; CHECK: [[COPY319:%[0-9]+]]:_(s32) = COPY [[SHL108]](s32)
- ; CHECK: [[OR108:%[0-9]+]]:_(s32) = G_OR [[COPY318]], [[COPY319]]
- ; CHECK: [[COPY320:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL109:%[0-9]+]]:_(s32) = G_SHL [[COPY320]], [[C9]](s64)
- ; CHECK: [[COPY321:%[0-9]+]]:_(s32) = COPY [[OR108]](s32)
- ; CHECK: [[COPY322:%[0-9]+]]:_(s32) = COPY [[SHL109]](s32)
- ; CHECK: [[OR109:%[0-9]+]]:_(s32) = G_OR [[COPY321]], [[COPY322]]
- ; CHECK: [[COPY323:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL110:%[0-9]+]]:_(s32) = G_SHL [[COPY323]], [[C11]](s64)
- ; CHECK: [[COPY324:%[0-9]+]]:_(s32) = COPY [[OR109]](s32)
- ; CHECK: [[COPY325:%[0-9]+]]:_(s32) = COPY [[SHL110]](s32)
- ; CHECK: [[OR110:%[0-9]+]]:_(s32) = G_OR [[COPY324]], [[COPY325]]
- ; CHECK: [[COPY326:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[SHL111:%[0-9]+]]:_(s32) = G_SHL [[COPY326]], [[C13]](s64)
- ; CHECK: [[COPY327:%[0-9]+]]:_(s32) = COPY [[OR110]](s32)
- ; CHECK: [[COPY328:%[0-9]+]]:_(s32) = COPY [[SHL111]](s32)
- ; CHECK: [[OR111:%[0-9]+]]:_(s32) = G_OR [[COPY327]], [[COPY328]]
+ ; CHECK: [[COPY58:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[OR105:%[0-9]+]]:_(s32) = G_OR [[COPY58]], [[SHL105]]
+ ; CHECK: [[COPY59:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL106:%[0-9]+]]:_(s32) = G_SHL [[COPY59]], [[C3]](s64)
+ ; CHECK: [[OR106:%[0-9]+]]:_(s32) = G_OR [[OR105]], [[SHL106]]
+ ; CHECK: [[COPY60:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL107:%[0-9]+]]:_(s32) = G_SHL [[COPY60]], [[C5]](s64)
+ ; CHECK: [[OR107:%[0-9]+]]:_(s32) = G_OR [[OR106]], [[SHL107]]
+ ; CHECK: [[COPY61:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL108:%[0-9]+]]:_(s32) = G_SHL [[COPY61]], [[C7]](s64)
+ ; CHECK: [[OR108:%[0-9]+]]:_(s32) = G_OR [[OR107]], [[SHL108]]
+ ; CHECK: [[COPY62:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL109:%[0-9]+]]:_(s32) = G_SHL [[COPY62]], [[C9]](s64)
+ ; CHECK: [[OR109:%[0-9]+]]:_(s32) = G_OR [[OR108]], [[SHL109]]
+ ; CHECK: [[COPY63:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL110:%[0-9]+]]:_(s32) = G_SHL [[COPY63]], [[C11]](s64)
+ ; CHECK: [[OR110:%[0-9]+]]:_(s32) = G_OR [[OR109]], [[SHL110]]
+ ; CHECK: [[COPY64:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; CHECK: [[SHL111:%[0-9]+]]:_(s32) = G_SHL [[COPY64]], [[C13]](s64)
+ ; CHECK: [[OR111:%[0-9]+]]:_(s32) = G_OR [[OR110]], [[SHL111]]
; CHECK: [[TRUNC16:%[0-9]+]]:_(s8) = G_TRUNC [[OR111]](s32)
; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[TRUNC9]](s8), [[TRUNC10]](s8), [[TRUNC11]](s8), [[TRUNC12]](s8), [[TRUNC13]](s8), [[TRUNC14]](s8), [[TRUNC15]](s8), [[TRUNC16]](s8)
; CHECK: $x0 = COPY [[MV]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-isnan.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-isnan.mir
index 4a9be4cedf3aa..4fedb2fe95280 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-isnan.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-isnan.mir
@@ -18,8 +18,7 @@ body: |
; CHECK: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
; CHECK: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(uno), [[FPEXT]](s32), [[FPEXT1]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
- ; CHECK: %ext:_(s32) = G_AND [[COPY]], [[C1]]
+ ; CHECK: %ext:_(s32) = G_AND [[FCMP]], [[C1]]
; CHECK: $w0 = COPY %ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%val:_(s16) = COPY $h0
@@ -43,8 +42,7 @@ body: |
; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[C]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC]](s16), [[FPTRUNC]](s16), [[FPTRUNC]](s16)
; CHECK: [[FCMP:%[0-9]+]]:_(<4 x s16>) = G_FCMP floatpred(uno), %val(<4 x s16>), [[BUILD_VECTOR]]
- ; CHECK: %ext:_(<4 x s16>) = COPY [[FCMP]](<4 x s16>)
- ; CHECK: $d0 = COPY %ext(<4 x s16>)
+ ; CHECK: $d0 = COPY [[FCMP]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%val:_(<4 x s16>) = COPY $d0
%isnan:_(<4 x s1>) = nofpexcept G_ISNAN %val(<4 x s16>)
@@ -65,16 +63,13 @@ body: |
; CHECK: %val:_(s16) = COPY $h0
; CHECK: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %val(s16)
; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[FPTOSI]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31744
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[AND]], 16
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[C1]](s32), [[SEXT_INREG]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; CHECK: %ext:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; CHECK: %ext:_(s32) = G_AND [[ICMP]], [[C2]]
; CHECK: $w0 = COPY %ext(s32)
; CHECK: RET_ReallyLR implicit $w0
%val:_(s16) = COPY $h0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
index 2af37dff5fd49..2c30761561037 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
@@ -151,8 +151,7 @@ body: |
liveins: $w0
; CHECK-LABEL: name: test_sitofp_s32_s1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[SEXT_INREG]](s32)
; CHECK: $w0 = COPY [[SITOFP]](s32)
%0:_(s32) = COPY $w0
@@ -169,8 +168,7 @@ body: |
; CHECK-LABEL: name: test_uitofp_s32_s1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
; CHECK: $w0 = COPY [[UITOFP]](s32)
%0:_(s32) = COPY $w0
@@ -186,8 +184,7 @@ body: |
liveins: $w0
; CHECK-LABEL: name: test_sitofp_s64_s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[SEXT_INREG]](s32)
; CHECK: $x0 = COPY [[SITOFP]](s64)
%0:_(s32) = COPY $w0
@@ -204,8 +201,7 @@ body: |
; CHECK-LABEL: name: test_uitofp_s64_s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32)
; CHECK: $x0 = COPY [[UITOFP]](s64)
%0:_(s32) = COPY $w0
@@ -281,8 +277,7 @@ body: |
liveins: $w0
; CHECK-LABEL: name: test_sitofp_s32_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[SEXT_INREG]](s32)
; CHECK: $w0 = COPY [[SITOFP]](s32)
%0:_(s32) = COPY $w0
@@ -299,8 +294,7 @@ body: |
; CHECK-LABEL: name: test_uitofp_s32_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
; CHECK: $w0 = COPY [[UITOFP]](s32)
%0:_(s32) = COPY $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
index b281e0ddbc327..6600344055fd6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
@@ -65,8 +65,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[AND1]](s32)
; CHECK: G_STORE [[TRUNC]](s8), [[COPY]](p0) :: (store (s8))
@@ -622,10 +621,9 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[OR3]](s64)
; CHECK: G_STORE [[COPY]](s64), %ptr(p0) :: (store (s64), align 16)
; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C1]](s64)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
- ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C3]](s64)
+ ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C3]](s64)
; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C2]](s64)
- ; CHECK: G_STORE [[COPY1]](s32), [[PTR_ADD2]](p0) :: (store (s16) into unknown-address + 8, align 8)
+ ; CHECK: G_STORE [[TRUNC]](s32), [[PTR_ADD2]](p0) :: (store (s16) into unknown-address + 8, align 8)
; CHECK: G_STORE [[LSHR1]](s32), [[PTR_ADD3]](p0) :: (store (s8) into unknown-address + 10, align 2)
; CHECK: RET_ReallyLR
%ptr:_(p0) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-memcpy-et-al.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-memcpy-et-al.mir
index 02470c7a61a21..627b98bef44a3 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-memcpy-et-al.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-memcpy-et-al.mir
@@ -97,8 +97,7 @@ body: |
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY2]](s32)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK: $x0 = COPY [[COPY]](p0)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: $w1 = COPY [[COPY3]](s32)
+ ; CHECK: $w1 = COPY [[COPY1]](s32)
; CHECK: $x2 = COPY [[ZEXT]](s64)
; CHECK: BL &memset, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1, implicit $x2
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
index e203fa05f998a..61f61e1d30e9d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
@@ -14,8 +14,7 @@ body: |
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C3]](s64)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[COPY1]]
+ ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64)
%0:_(s64) = G_CONSTANT i64 0
@@ -30,6 +29,8 @@ body: |
name: test_merge_s16_s8
body: |
bb.0:
+
+ ; This isn't legal but we don't support widening the destination type.
; CHECK-LABEL: name: test_merge_s16_s8
; CHECK: %a:_(s32) = COPY $w0
; CHECK: %b:_(s32) = COPY $w1
@@ -38,8 +39,6 @@ body: |
; CHECK: %m:_(s16) = G_MERGE_VALUES %a_t(s8), %b_t(s8)
; CHECK: %ext:_(s64) = G_ANYEXT %m(s16)
; CHECK: $x0 = COPY %ext(s64)
-
- ; This isn't legal but we don't support widening the destination type.
%a:_(s32) = COPY $w0
%b:_(s32) = COPY $w1
%a_t:_(s8) = G_TRUNC %a
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
index e237d0d778612..47330978ba7cf 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir
@@ -223,10 +223,9 @@ body: |
; CHECK: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), %vec(<2 x s64>), %vec1
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s64>)
+ ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
@@ -254,10 +253,9 @@ body: |
; CHECK: liveins: $x0, $q0, $q1
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s64>)
+ ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
@@ -266,19 +264,18 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
; CHECK: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP1]](<2 x s64>)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK: [[SHL1:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY1]], [[BUILD_VECTOR2]](<2 x s64>)
+ ; CHECK: [[SHL1:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP1]], [[BUILD_VECTOR2]](<2 x s64>)
; CHECK: [[ASHR1:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL1]], [[BUILD_VECTOR2]](<2 x s64>)
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
; CHECK: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ASHR1]], [[BUILD_VECTOR3]]
; CHECK: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ASHR1]]
; CHECK: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
; CHECK: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: G_STORE [[OR]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>), align 32)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY2]], [[C2]](s64)
+ ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CHECK: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
%vec:_(<4 x s64>) = G_IMPLICIT_DEF
%vec1:_(<4 x s64>) = G_IMPLICIT_DEF
@@ -509,10 +506,9 @@ body: |
; CHECK: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), %vec(<2 x s64>), %vec1
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s64>)
+ ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
@@ -540,10 +536,9 @@ body: |
; CHECK: liveins: $x0, $q0, $q1
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s64>)
+ ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
@@ -552,19 +547,18 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
; CHECK: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP1]](<2 x s64>)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK: [[SHL1:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY1]], [[BUILD_VECTOR2]](<2 x s64>)
+ ; CHECK: [[SHL1:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP1]], [[BUILD_VECTOR2]](<2 x s64>)
; CHECK: [[ASHR1:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL1]], [[BUILD_VECTOR2]](<2 x s64>)
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
; CHECK: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ASHR1]], [[BUILD_VECTOR3]]
; CHECK: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ASHR1]]
; CHECK: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
; CHECK: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: G_STORE [[OR]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>), align 32)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY2]], [[C2]](s64)
+ ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CHECK: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
%vec:_(<4 x s64>) = G_IMPLICIT_DEF
%vec1:_(<4 x s64>) = G_IMPLICIT_DEF
@@ -795,10 +789,9 @@ body: |
; CHECK: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), %vec(<2 x s64>), %vec1
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s64>)
+ ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
@@ -826,10 +819,9 @@ body: |
; CHECK: liveins: $x0, $q0, $q1
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s64>)
+ ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
@@ -838,19 +830,18 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
; CHECK: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP1]](<2 x s64>)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK: [[SHL1:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY1]], [[BUILD_VECTOR2]](<2 x s64>)
+ ; CHECK: [[SHL1:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP1]], [[BUILD_VECTOR2]](<2 x s64>)
; CHECK: [[ASHR1:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL1]], [[BUILD_VECTOR2]](<2 x s64>)
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
; CHECK: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ASHR1]], [[BUILD_VECTOR3]]
; CHECK: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ASHR1]]
; CHECK: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
; CHECK: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: G_STORE [[OR]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>), align 32)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY2]], [[C2]](s64)
+ ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CHECK: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
%vec:_(<4 x s64>) = G_IMPLICIT_DEF
%vec1:_(<4 x s64>) = G_IMPLICIT_DEF
@@ -1081,10 +1072,9 @@ body: |
; CHECK: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), %vec(<2 x s64>), %vec1
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s64>)
+ ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
@@ -1112,10 +1102,9 @@ body: |
; CHECK: liveins: $x0, $q0, $q1
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s64>)
+ ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
@@ -1124,19 +1113,18 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]]
; CHECK: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP1]](<2 x s64>)
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
- ; CHECK: [[SHL1:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY1]], [[BUILD_VECTOR2]](<2 x s64>)
+ ; CHECK: [[SHL1:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP1]], [[BUILD_VECTOR2]](<2 x s64>)
; CHECK: [[ASHR1:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL1]], [[BUILD_VECTOR2]](<2 x s64>)
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
; CHECK: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ASHR1]], [[BUILD_VECTOR3]]
; CHECK: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ASHR1]]
; CHECK: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]]
; CHECK: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: G_STORE [[OR]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>), align 32)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY2]], [[C2]](s64)
+ ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CHECK: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16)
%vec:_(<4 x s64>) = G_IMPLICIT_DEF
%vec1:_(<4 x s64>) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
index d674b0d12ffed..d1e95f0e74f87 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
@@ -34,8 +34,7 @@ body: |
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[MUL]], [[C]](s64)
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SMULH]](s64), [[ASHR]]
; CHECK: $x0 = COPY [[MUL]](s64)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; CHECK: $w0 = COPY [[COPY2]](s32)
+ ; CHECK: $w0 = COPY [[ICMP]](s32)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64), %3:_(s1) = G_SMULO %0, %1
@@ -56,8 +55,7 @@ body: |
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s64), [[C]]
; CHECK: $x0 = COPY [[MUL]](s64)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; CHECK: $w0 = COPY [[COPY2]](s32)
+ ; CHECK: $w0 = COPY [[ICMP]](s32)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64), %3:_(s1) = G_UMULO %0, %1
@@ -79,8 +77,7 @@ body: |
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR %mul, [[C]](s64)
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SMULH]](s32), [[ASHR]]
; CHECK: $w0 = COPY %mul(s32)
- ; CHECK: %ext_overflow:_(s32) = COPY [[ICMP]](s32)
- ; CHECK: $w0 = COPY %ext_overflow(s32)
+ ; CHECK: $w0 = COPY [[ICMP]](s32)
; CHECK: RET_ReallyLR implicit $w0
%lhs:_(s32) = COPY $w0
%rhs:_(s32) = COPY $w1
@@ -103,8 +100,7 @@ body: |
; CHECK: %mul:_(s32) = G_MUL %lhs, %rhs
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]]
; CHECK: $w0 = COPY %mul(s32)
- ; CHECK: %ext_overflow:_(s32) = COPY [[ICMP]](s32)
- ; CHECK: $w0 = COPY %ext_overflow(s32)
+ ; CHECK: $w0 = COPY [[ICMP]](s32)
; CHECK: RET_ReallyLR implicit $w0
%lhs:_(s32) = COPY $w0
%rhs:_(s32) = COPY $w1
@@ -123,23 +119,17 @@ body: |
; CHECK: %lhs_wide:_(s32) = COPY $w0
; CHECK: %rhs_wide:_(s32) = COPY $w1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %lhs_wide(s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %rhs_wide(s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND %lhs_wide, [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND %rhs_wide, [[C]]
; CHECK: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[AND1]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C1]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[MUL]](s32), [[AND2]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
- ; CHECK: %ext_mul:_(s32) = COPY [[MUL]](s32)
- ; CHECK: $w0 = COPY %ext_mul(s32)
- ; CHECK: %ext_overflow:_(s32) = COPY [[OR]](s32)
- ; CHECK: $w0 = COPY %ext_overflow(s32)
+ ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP]], [[ICMP1]]
+ ; CHECK: $w0 = COPY [[MUL]](s32)
+ ; CHECK: $w0 = COPY [[OR]](s32)
; CHECK: RET_ReallyLR implicit $w0
%lhs_wide:_(s32) = COPY $w0
%rhs_wide:_(s32) = COPY $w1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
index 6bb84fb348848..fa993e90e23e1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
@@ -20,10 +20,9 @@ body: |
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C2]](s64)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C2]](s64)
+ ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[OR]], [[C2]](s64)
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s64)
- ; CHECK: G_STORE [[COPY2]](s32), [[COPY1]](p0) :: (store (s16), align 4)
+ ; CHECK: G_STORE [[OR]](s32), [[COPY1]](p0) :: (store (s16), align 4)
; CHECK: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p0) :: (store (s8) into unknown-address + 2, align 2)
; CHECK: $w0 = COPY [[C]](s32)
; CHECK: RET_ReallyLR implicit $w0
@@ -50,12 +49,11 @@ body: |
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C1]](s64)
+ ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[C]], [[C1]](s64)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; CHECK: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store (s32), align 8)
+ ; CHECK: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s32), align 8)
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C3]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
index 799fe5f42e4a3..b9614fccaa759 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
@@ -259,16 +259,14 @@ body: |
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT]], [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[COPY]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
; CHECK: bb.2:
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C3]]
; CHECK: $w0 = COPY [[AND1]](s32)
; CHECK: RET_ReallyLR implicit $w0
bb.0:
@@ -319,13 +317,12 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK: bb.1:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[C]](s16), %bb.0, %7(s16), %bb.1
+ ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[C]](s16), %bb.0, [[PHI]](s16), %bb.1
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[COPY]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[PHI]](s16)
; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
; CHECK: bb.2:
; CHECK: $w0 = COPY [[AND]](s32)
@@ -506,12 +503,11 @@ body: |
; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[C2]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ADD1]](s32), [[C3]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[PHI]](s16)
; CHECK: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 43
; CHECK: G_BRCOND [[TRUNC3]](s1), %bb.2
; CHECK: G_BR %bb.1
; CHECK: bb.2:
- ; CHECK: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[COPY2]](s16), %bb.1, [[TRUNC1]](s16), %bb.0
+ ; CHECK: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[PHI]](s16), %bb.1, [[TRUNC1]](s16), %bb.0
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C6]]
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptr-add.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptr-add.mir
index 65dba4ce4104a..a79a4801c71cf 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptr-add.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ptr-add.mir
@@ -7,8 +7,7 @@ body: |
; CHECK-LABEL: name: test_ptr_add_small
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 8
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 8
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[SEXT_INREG]](s64)
; CHECK: $x0 = COPY [[PTR_ADD]](p0)
%0:_(p0) = COPY $x0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-or.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-or.mir
index 2ebd88a224b94..c88fbbe3e112d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-or.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-reduce-or.mir
@@ -15,8 +15,7 @@ body: |
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: $w0 = COPY [[AND]](s32)
; CHECK: RET_ReallyLR implicit $w0
%1:_(s32) = COPY $w0
@@ -41,12 +40,9 @@ body: |
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY2]]
+ ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[UV1]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C]]
; CHECK: $w0 = COPY [[AND]](s32)
; CHECK: RET_ReallyLR implicit $w0
%1:_(<2 x s32>) = COPY $d0
@@ -77,12 +73,9 @@ body: |
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
- ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY2]]
+ ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR]], [[OR1]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[OR2]], [[C]]
; CHECK: $w0 = COPY [[AND]](s32)
; CHECK: RET_ReallyLR implicit $w0
%1:_(<4 x s16>) = COPY $d0
@@ -119,18 +112,11 @@ body: |
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ANYEXT6]], [[ANYEXT7]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
- ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
- ; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[COPY4]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR4]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[OR5]](s32)
- ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[COPY6]]
+ ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR]], [[OR1]]
+ ; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[OR3]]
+ ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[OR5]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR6]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[OR6]], [[C]]
; CHECK: $w0 = COPY [[AND]](s32)
; CHECK: RET_ReallyLR implicit $w0
%1:_(<8 x s8>) = COPY $d0
@@ -182,30 +168,15 @@ body: |
; CHECK: [[ANYEXT14:%[0-9]+]]:_(s32) = G_ANYEXT [[UV14]](s8)
; CHECK: [[ANYEXT15:%[0-9]+]]:_(s32) = G_ANYEXT [[UV15]](s8)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[ANYEXT14]], [[ANYEXT15]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
- ; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
- ; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[COPY4]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR4]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[OR5]](s32)
- ; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[COPY6]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR6]](s32)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[OR7]](s32)
- ; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[COPY7]], [[COPY8]]
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[OR8]](s32)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[OR9]](s32)
- ; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[COPY9]], [[COPY10]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[OR10]](s32)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[OR11]](s32)
- ; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[COPY11]], [[COPY12]]
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[OR12]](s32)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[OR13]](s32)
- ; CHECK: [[OR14:%[0-9]+]]:_(s32) = G_OR [[COPY13]], [[COPY14]]
+ ; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR]], [[OR1]]
+ ; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[OR3]]
+ ; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[OR5]]
+ ; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[OR7]]
+ ; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[OR9]]
+ ; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[OR11]]
+ ; CHECK: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[OR13]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[OR14]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[OR14]], [[C]]
; CHECK: $w0 = COPY [[AND]](s32)
; CHECK: RET_ReallyLR implicit $w0
%1:_(<16 x s8>) = COPY $q0
@@ -259,14 +230,9 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[COPY4]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[COPY6]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
- ; CHECK: $w0 = COPY [[COPY7]](s32)
+ ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]]
+ ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[COPY2]]
+ ; CHECK: $w0 = COPY [[OR1]](s32)
; CHECK: RET_ReallyLR implicit $w0
%1:_(s32) = COPY $w0
%2:_(s32) = COPY $w1
@@ -299,11 +265,8 @@ body: |
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
- ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CHECK: $w0 = COPY [[COPY3]](s32)
+ ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR]], [[OR1]]
+ ; CHECK: $w0 = COPY [[OR2]](s32)
; CHECK: RET_ReallyLR implicit $w0
%1:_(<4 x s16>) = COPY $d0
%0:_(<4 x s8>) = G_TRUNC %1(<4 x s16>)
@@ -339,17 +302,10 @@ body: |
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ANYEXT6]], [[ANYEXT7]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
- ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
- ; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[COPY4]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR4]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[OR5]](s32)
- ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[COPY6]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR6]](s32)
- ; CHECK: $w0 = COPY [[COPY7]](s32)
+ ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR]], [[OR1]]
+ ; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[OR3]]
+ ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[OR5]]
+ ; CHECK: $w0 = COPY [[OR6]](s32)
; CHECK: RET_ReallyLR implicit $w0
%0:_(<8 x s8>) = COPY $d0
%1:_(s8) = G_VECREDUCE_OR %0(<8 x s8>)
@@ -386,17 +342,10 @@ body: |
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV8]](s8)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV9]](s8)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ANYEXT6]], [[ANYEXT7]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR4]](s32)
- ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[COPY4]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR5]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[OR6]](s32)
- ; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[COPY6]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR7]](s32)
- ; CHECK: $w0 = COPY [[COPY7]](s32)
+ ; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[OR2]]
+ ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[OR4]]
+ ; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[OR6]]
+ ; CHECK: $w0 = COPY [[OR7]](s32)
; CHECK: RET_ReallyLR implicit $w0
%0:_(<16 x s8>) = COPY $q0
%1:_(s8) = G_VECREDUCE_OR %0(<16 x s8>)
@@ -436,17 +385,10 @@ body: |
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV8]](s8)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV9]](s8)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[ANYEXT6]], [[ANYEXT7]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
- ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR4]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR5]](s32)
- ; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[COPY4]], [[COPY5]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[OR6]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR7]](s32)
- ; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[COPY6]], [[COPY7]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[OR8]](s32)
- ; CHECK: $w0 = COPY [[COPY8]](s32)
+ ; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[OR3]]
+ ; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[OR5]]
+ ; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[OR7]]
+ ; CHECK: $w0 = COPY [[OR8]](s32)
; CHECK: RET_ReallyLR implicit $w0
%1:_(<16 x s8>) = COPY $q0
%2:_(<16 x s8>) = COPY $q1
@@ -477,11 +419,8 @@ body: |
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
- ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CHECK: $w0 = COPY [[COPY3]](s32)
+ ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR]], [[OR1]]
+ ; CHECK: $w0 = COPY [[OR2]](s32)
; CHECK: RET_ReallyLR implicit $w0
%0:_(<4 x s16>) = COPY $d0
%1:_(s16) = G_VECREDUCE_OR %0(<4 x s16>)
@@ -512,11 +451,8 @@ body: |
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s16)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s16)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
- ; CHECK: $w0 = COPY [[COPY3]](s32)
+ ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[OR2]]
+ ; CHECK: $w0 = COPY [[OR3]](s32)
; CHECK: RET_ReallyLR implicit $w0
%0:_(<8 x s16>) = COPY $q0
%1:_(s16) = G_VECREDUCE_OR %0(<8 x s16>)
@@ -550,11 +486,8 @@ body: |
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s16)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s16)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ANYEXT2]], [[ANYEXT3]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
- ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR4]](s32)
- ; CHECK: $w0 = COPY [[COPY4]](s32)
+ ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[OR3]]
+ ; CHECK: $w0 = COPY [[OR4]](s32)
; CHECK: RET_ReallyLR implicit $w0
%1:_(<8 x s16>) = COPY $q0
%2:_(<8 x s16>) = COPY $q1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
index b1348e51dc9b0..ffa2b2bfdda88 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
@@ -50,14 +50,11 @@ body: |
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[TRUNC2]]
+ ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[TRUNC2]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC3]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: $w0 = COPY [[COPY4]](s32)
+ ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC3]], [[MUL]]
+ ; CHECK: $w0 = COPY [[SUB]](s32)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
index 1a1ece3507549..14a97ba60e440 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
@@ -85,8 +85,7 @@ body: |
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[SEXT_INREG]], [[SEXT_INREG1]], %carry_in
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[UADDE]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UADDE]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UADDE]], 8
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[SEXT_INREG2]]
; CHECK: %add:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: %add_ext:_(s64) = G_ANYEXT [[UADDE]](s32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
index 7015a923d4b7a..0828af4222fc6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
@@ -75,10 +75,9 @@ body: |
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[ADD]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 8
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[SEXT_INREG2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
index 8e17cebd978b4..7272d320fed59 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
@@ -63,28 +63,20 @@ body: |
; CHECK: liveins: $w0, $w1, $w2
; CHECK: %copy_1:_(s32) = COPY $w0
; CHECK: %copy_2:_(s32) = COPY $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %copy_1(s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %copy_2(s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 16
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 16
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 16
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 16
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
- ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[C2]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY5]], [[COPY6]]
- ; CHECK: %ext:_(s32) = COPY [[SELECT]](s32)
- ; CHECK: $w0 = COPY %ext(s32)
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C2]]
+ ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ADD1]], [[ADD]]
+ ; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s16) = G_TRUNC %copy_1(s32)
@@ -107,28 +99,20 @@ body: |
; CHECK: liveins: $w0, $w1, $w2
; CHECK: %copy_1:_(s32) = COPY $w0
; CHECK: %copy_2:_(s32) = COPY $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %copy_1(s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %copy_2(s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 1
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 1
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 1
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 1
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[C2]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY5]], [[COPY6]]
- ; CHECK: %ext:_(s32) = COPY [[SELECT]](s32)
- ; CHECK: $w0 = COPY %ext(s32)
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C2]]
+ ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ADD1]], [[ADD]]
+ ; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s1) = G_TRUNC %copy_1(s32)
@@ -151,28 +135,20 @@ body: |
; CHECK: liveins: $w0, $w1, $w2
; CHECK: %copy_1:_(s32) = COPY $w0
; CHECK: %copy_2:_(s32) = COPY $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %copy_1(s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 3
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %copy_2(s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 3
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 3
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 3
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 3
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 3
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 3
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 3
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[C2]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY5]], [[COPY6]]
- ; CHECK: %ext:_(s32) = COPY [[SELECT]](s32)
- ; CHECK: $w0 = COPY %ext(s32)
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C2]]
+ ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ADD1]], [[ADD]]
+ ; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s3) = G_TRUNC %copy_1(s32)
@@ -195,31 +171,20 @@ body: |
; CHECK: liveins: $x0, $x1
; CHECK: %copy_1:_(s64) = COPY $x0
; CHECK: %copy_2:_(s64) = COPY $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %copy_1(s64)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 36
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %copy_2(s64)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 36
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG %copy_1, 36
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG %copy_2, 36
; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ADD]](s64)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 36
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 36
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s64), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 35
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[ADD]](s64)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY3]], 36
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 68719476735
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[C]](s64)
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY4]], [[C1]]
- ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG3]], [[AND]](s64)
- ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
- ; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY [[ASHR]](s64)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
- ; CHECK: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[COPY5]], [[COPY6]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY [[ADD1]](s64)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s64) = COPY [[ADD]](s64)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY7]], [[COPY8]]
- ; CHECK: %ext:_(s64) = COPY [[SELECT]](s64)
- ; CHECK: $x0 = COPY %ext(s64)
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 36
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY [[C]](s64)
+ ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG3]], [[COPY]](s64)
+ ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]]
+ ; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[ADD1]], [[ADD]]
+ ; CHECK: $x0 = COPY [[SELECT]](s64)
; CHECK: RET_ReallyLR implicit $x0
%copy_1:_(s64) = COPY $x0
%x:_(s36) = G_TRUNC %copy_1(s64)
@@ -241,22 +206,19 @@ body: |
; CHECK: liveins: $q0, $q1, $x0
; CHECK: %copy_1:_(s128) = COPY $q0
; CHECK: %copy_2:_(s128) = COPY $q1
- ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY %copy_1(s128)
- ; CHECK: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY]](s128), 0
+ ; CHECK: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT %copy_1(s128), 0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY %copy_2(s128)
- ; CHECK: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY1]](s128), 0
- ; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](s128)
+ ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %copy_1(s128)
+ ; CHECK: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT %copy_2(s128), 0
+ ; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %copy_2(s128)
; CHECK: [[UADDO:%[0-9]+]]:_(s64), [[UADDO1:%[0-9]+]]:_(s1) = G_UADDO [[EXTRACT]], [[EXTRACT1]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s64)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 24
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 24
; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[SEXT_INREG]], [[SEXT_INREG1]], [[UADDO1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UADDE]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 24
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UADDE]], 24
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8), [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[UADDO]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
index 2c6ce9b5618f0..cbde294d6dfeb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
@@ -16,10 +16,9 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[COPY]](<2 x s64>), [[BUILD_VECTOR]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
- ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY2]], [[BUILD_VECTOR1]](<2 x s64>)
+ ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[ICMP]], [[BUILD_VECTOR1]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR1]](<2 x s64>)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C2]](s64), [[C2]](s64)
@@ -54,10 +53,9 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sgt), [[COPY]](<2 x s32>), [[BUILD_VECTOR]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32)
- ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s32>) = G_SHL [[COPY2]], [[BUILD_VECTOR1]](<2 x s32>)
+ ; CHECK: [[SHL:%[0-9]+]]:_(<2 x s32>) = G_SHL [[ICMP]], [[BUILD_VECTOR1]](<2 x s32>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s32>) = G_ASHR [[SHL]], [[BUILD_VECTOR1]](<2 x s32>)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C2]](s32), [[C2]](s32)
@@ -92,10 +90,9 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8)
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sgt), [[COPY]](<16 x s8>), [[BUILD_VECTOR]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
; CHECK: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 7
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8), [[C1]](s8)
- ; CHECK: [[SHL:%[0-9]+]]:_(<16 x s8>) = G_SHL [[COPY2]], [[BUILD_VECTOR1]](<16 x s8>)
+ ; CHECK: [[SHL:%[0-9]+]]:_(<16 x s8>) = G_SHL [[ICMP]], [[BUILD_VECTOR1]](<16 x s8>)
; CHECK: [[ASHR:%[0-9]+]]:_(<16 x s8>) = G_ASHR [[SHL]], [[BUILD_VECTOR1]](<16 x s8>)
; CHECK: [[C2:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<16 x s8>) = G_BUILD_VECTOR [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8), [[C2]](s8)
@@ -133,8 +130,7 @@ body: |
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32)
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ICMP]], 1
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[SEXT_INREG]](s32), [[C2]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
index ef97250744378..5efa69a114703 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
@@ -14,21 +14,18 @@ body: |
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; CHECK: $w0 = COPY [[COPY2]](s32)
+ ; CHECK: $w0 = COPY [[ASHR]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C]]
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C]]
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $w0 = COPY [[COPY3]](s32)
+ ; CHECK: $w0 = COPY [[LSHR]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[TRUNC4]], [[C]]
; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC5]], [[AND3]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; CHECK: $w0 = COPY [[COPY4]](s32)
+ ; CHECK: $w0 = COPY [[SHL]](s32)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
index 89e310cc9ecd8..be946f7a5dae4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
@@ -17,18 +17,15 @@ body: |
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC2]], [[TRUNC3]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; CHECK: $w0 = COPY [[COPY1]](s32)
+ ; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC4]], [[TRUNC5]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; CHECK: $w0 = COPY [[COPY2]](s32)
+ ; CHECK: $w0 = COPY [[SELECT1]](s32)
; CHECK: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC6]], [[TRUNC7]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SELECT2]](s32)
- ; CHECK: $w0 = COPY [[COPY3]](s32)
+ ; CHECK: $w0 = COPY [[SELECT2]](s32)
; CHECK: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC1]], [[TRUNC1]]
; CHECK: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY]]
; CHECK: $x0 = COPY [[SELECT4]](s64)
@@ -111,8 +108,7 @@ body: |
; CHECK-LABEL: name: testExtOfCopyOfTrunc
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK: $x0 = COPY [[COPY1]](s64)
+ ; CHECK: $x0 = COPY [[COPY]](s64)
; CHECK: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s1) = G_TRUNC %0(s64)
@@ -130,8 +126,7 @@ body: |
; CHECK-LABEL: name: testExtOf2CopyOfTrunc
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK: $x0 = COPY [[COPY1]](s64)
+ ; CHECK: $x0 = COPY [[COPY]](s64)
; CHECK: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s1) = G_TRUNC %0(s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
index 2acf88b64b82b..0f58438bbe6ad 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
@@ -85,8 +85,7 @@ body: |
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[SEXT_INREG]], [[SEXT_INREG1]], %carry_in
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[USUBE]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[USUBE]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[USUBE]], 8
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](s32), [[SEXT_INREG2]]
; CHECK: %sub:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: %sub_ext:_(s64) = G_ANYEXT [[USUBE]](s32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
index 7686d66acf8f2..f10f76f4b326f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
@@ -75,10 +75,9 @@ body: |
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 8
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[SUB]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 8
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[SEXT_INREG2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
index 7d1178fbf2e23..66d0ba02883ac 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
@@ -63,28 +63,20 @@ body: |
; CHECK: liveins: $w0, $w1, $w2
; CHECK: %copy_1:_(s32) = COPY $w0
; CHECK: %copy_2:_(s32) = COPY $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %copy_1(s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %copy_2(s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 16
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 16
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 16
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 16
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[C2]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY5]], [[COPY6]]
- ; CHECK: %ext:_(s32) = COPY [[SELECT]](s32)
- ; CHECK: $w0 = COPY %ext(s32)
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C2]]
+ ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ADD]], [[SUB]]
+ ; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s16) = G_TRUNC %copy_1(s32)
@@ -107,28 +99,20 @@ body: |
; CHECK: liveins: $w0, $w1, $w2
; CHECK: %copy_1:_(s32) = COPY $w0
; CHECK: %copy_2:_(s32) = COPY $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %copy_1(s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %copy_2(s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 1
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 1
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 1
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 1
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[C2]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY5]], [[COPY6]]
- ; CHECK: %ext:_(s32) = COPY [[SELECT]](s32)
- ; CHECK: $w0 = COPY %ext(s32)
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C2]]
+ ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ADD]], [[SUB]]
+ ; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s1) = G_TRUNC %copy_1(s32)
@@ -151,28 +135,20 @@ body: |
; CHECK: liveins: $w0, $w1, $w2
; CHECK: %copy_1:_(s32) = COPY $w0
; CHECK: %copy_2:_(s32) = COPY $w1
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %copy_1(s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 3
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %copy_2(s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 3
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_1, 3
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %copy_2, 3
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 3
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 3
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 2
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 3
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 3
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s64)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[C2]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY5]], [[COPY6]]
- ; CHECK: %ext:_(s32) = COPY [[SELECT]](s32)
- ; CHECK: $w0 = COPY %ext(s32)
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C2]]
+ ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[ADD]], [[SUB]]
+ ; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%copy_1:_(s32) = COPY $w0
%x:_(s3) = G_TRUNC %copy_1(s32)
@@ -195,31 +171,20 @@ body: |
; CHECK: liveins: $x0, $x1
; CHECK: %copy_1:_(s64) = COPY $x0
; CHECK: %copy_2:_(s64) = COPY $x1
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %copy_1(s64)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 36
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %copy_2(s64)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 36
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG %copy_1, 36
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG %copy_2, 36
; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[SUB]](s64)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 36
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 36
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s64), [[SEXT_INREG2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 35
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[SUB]](s64)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY3]], 36
- ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 68719476735
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[C]](s64)
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY4]], [[C1]]
- ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG3]], [[AND]](s64)
- ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
- ; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY [[ASHR]](s64)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
- ; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY5]], [[COPY6]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY [[ADD]](s64)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s64) = COPY [[SUB]](s64)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY7]], [[COPY8]]
- ; CHECK: %ext:_(s64) = COPY [[SELECT]](s64)
- ; CHECK: $x0 = COPY %ext(s64)
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SUB]], 36
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY [[C]](s64)
+ ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG3]], [[COPY]](s64)
+ ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
+ ; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]]
+ ; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[ADD]], [[SUB]]
+ ; CHECK: $x0 = COPY [[SELECT]](s64)
; CHECK: RET_ReallyLR implicit $x0
%copy_1:_(s64) = COPY $x0
%x:_(s36) = G_TRUNC %copy_1(s64)
@@ -241,22 +206,19 @@ body: |
; CHECK: liveins: $q0, $q1, $x0
; CHECK: %copy_1:_(s128) = COPY $q0
; CHECK: %copy_2:_(s128) = COPY $q1
- ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY %copy_1(s128)
- ; CHECK: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY]](s128), 0
+ ; CHECK: [[EXTRACT:%[0-9]+]]:_(s64) = G_EXTRACT %copy_1(s128), 0
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY %copy_2(s128)
- ; CHECK: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT [[COPY1]](s128), 0
- ; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](s128)
+ ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %copy_1(s128)
+ ; CHECK: [[EXTRACT1:%[0-9]+]]:_(s64) = G_EXTRACT %copy_2(s128), 0
+ ; CHECK: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES %copy_2(s128)
; CHECK: [[USUBO:%[0-9]+]]:_(s64), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[EXTRACT]], [[EXTRACT1]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[UV1]](s64)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC]], 24
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[UV3]](s64)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC1]], 24
; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[SEXT_INREG]], [[SEXT_INREG1]], [[USUBO1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[USUBE]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 24
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[USUBE]], 24
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](s32), [[SEXT_INREG2]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8), [[UV8:%[0-9]+]]:_(s8), [[UV9:%[0-9]+]]:_(s8), [[UV10:%[0-9]+]]:_(s8), [[UV11:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[USUBO]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir
index 1fa2a3a4a8e39..fee7736d629e1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir
@@ -70,20 +70,15 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[COPY5]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; CHECK: $w0 = COPY [[COPY6]](s32)
+ ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[ADD]]
+ ; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %2(s32)
@@ -111,20 +106,15 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[COPY5]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; CHECK: $w0 = COPY [[COPY6]](s32)
+ ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[ADD]]
+ ; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s8) = G_TRUNC %2(s32)
@@ -155,20 +145,15 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY5]], [[COPY6]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; CHECK: $w0 = COPY [[COPY7]](s32)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[COPY2]], [[ADD]]
+ ; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s4) = G_TRUNC %2(s32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
index 68c645a721c8c..64fae3b947fba 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
@@ -86,8 +86,7 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[AND]], [[AND1]], %carry_in
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[UADDE]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UADDE]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UADDE]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UADDE]](s32), [[AND2]]
; CHECK: %add:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: %add_ext:_(s64) = G_ANYEXT [[UADDE]](s32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
index 1ee1de9523653..657f9dbde5fd4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
@@ -76,10 +76,9 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[ADD]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir
index 37f4a0e658bf3..a420263790e14 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir
@@ -70,20 +70,15 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[COPY5]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; CHECK: $w0 = COPY [[COPY6]](s32)
+ ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[SUB]]
+ ; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %2(s32)
@@ -111,20 +106,15 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[COPY5]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; CHECK: $w0 = COPY [[COPY6]](s32)
+ ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[SUB]]
+ ; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s8) = G_TRUNC %2(s32)
@@ -152,20 +142,15 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[COPY5]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; CHECK: $w0 = COPY [[COPY6]](s32)
+ ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[C1]], [[SUB]]
+ ; CHECK: $w0 = COPY [[SELECT]](s32)
; CHECK: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s4) = G_TRUNC %2(s32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
index 7741ec1e8a151..42c5a229c58fe 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
@@ -86,8 +86,7 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[AND]], [[AND1]], %carry_in
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[USUBE]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[USUBE]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[USUBE]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[USUBE]](s32), [[AND2]]
; CHECK: %sub:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: %sub_ext:_(s64) = G_ANYEXT [[USUBE]](s32)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
index b16343bf0134c..122c31305fd2d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
@@ -76,10 +76,9 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[SUB]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[TRUNC2]](s8)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-cmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-cmp.mir
index 3ec41a3a9358c..7ab5e2ab6a12e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-cmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vector-cmp.mir
@@ -79,8 +79,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY]](<2 x s32>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>)
- ; CHECK: $d0 = COPY [[COPY2]](<2 x s32>)
+ ; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
@@ -139,8 +138,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY]](<4 x s16>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>)
- ; CHECK: $d0 = COPY [[COPY2]](<4 x s16>)
+ ; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
@@ -169,8 +167,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
- ; CHECK: $q0 = COPY [[COPY2]](<16 x s8>)
+ ; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
@@ -199,8 +196,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY]](<8 x s8>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>)
- ; CHECK: $d0 = COPY [[COPY2]](<8 x s8>)
+ ; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
@@ -289,8 +285,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(ugt), [[COPY]](<2 x s32>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>)
- ; CHECK: $d0 = COPY [[COPY2]](<2 x s32>)
+ ; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
@@ -349,8 +344,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(ugt), [[COPY]](<4 x s16>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>)
- ; CHECK: $d0 = COPY [[COPY2]](<4 x s16>)
+ ; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
@@ -379,8 +373,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(ugt), [[COPY]](<16 x s8>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
- ; CHECK: $q0 = COPY [[COPY2]](<16 x s8>)
+ ; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
@@ -409,8 +402,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(ugt), [[COPY]](<8 x s8>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>)
- ; CHECK: $d0 = COPY [[COPY2]](<8 x s8>)
+ ; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
@@ -499,8 +491,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(uge), [[COPY]](<2 x s32>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>)
- ; CHECK: $d0 = COPY [[COPY2]](<2 x s32>)
+ ; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
@@ -559,8 +550,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(uge), [[COPY]](<4 x s16>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>)
- ; CHECK: $d0 = COPY [[COPY2]](<4 x s16>)
+ ; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
@@ -589,8 +579,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(uge), [[COPY]](<16 x s8>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
- ; CHECK: $q0 = COPY [[COPY2]](<16 x s8>)
+ ; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
@@ -619,8 +608,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(uge), [[COPY]](<8 x s8>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>)
- ; CHECK: $d0 = COPY [[COPY2]](<8 x s8>)
+ ; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
@@ -709,8 +697,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(ult), [[COPY]](<2 x s32>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>)
- ; CHECK: $d0 = COPY [[COPY2]](<2 x s32>)
+ ; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
@@ -769,8 +756,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(ult), [[COPY]](<4 x s16>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>)
- ; CHECK: $d0 = COPY [[COPY2]](<4 x s16>)
+ ; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
@@ -799,8 +785,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(ult), [[COPY]](<16 x s8>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
- ; CHECK: $q0 = COPY [[COPY2]](<16 x s8>)
+ ; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
@@ -829,8 +814,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(ult), [[COPY]](<8 x s8>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>)
- ; CHECK: $d0 = COPY [[COPY2]](<8 x s8>)
+ ; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
@@ -919,8 +903,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(ule), [[COPY]](<2 x s32>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>)
- ; CHECK: $d0 = COPY [[COPY2]](<2 x s32>)
+ ; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
@@ -979,8 +962,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(ule), [[COPY]](<4 x s16>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>)
- ; CHECK: $d0 = COPY [[COPY2]](<4 x s16>)
+ ; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
@@ -1009,8 +991,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(ule), [[COPY]](<16 x s8>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
- ; CHECK: $q0 = COPY [[COPY2]](<16 x s8>)
+ ; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
@@ -1039,8 +1020,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(ule), [[COPY]](<8 x s8>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>)
- ; CHECK: $d0 = COPY [[COPY2]](<8 x s8>)
+ ; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
@@ -1129,8 +1109,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sgt), [[COPY]](<2 x s32>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>)
- ; CHECK: $d0 = COPY [[COPY2]](<2 x s32>)
+ ; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
@@ -1189,8 +1168,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(sgt), [[COPY]](<4 x s16>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>)
- ; CHECK: $d0 = COPY [[COPY2]](<4 x s16>)
+ ; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
@@ -1219,8 +1197,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sgt), [[COPY]](<16 x s8>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
- ; CHECK: $q0 = COPY [[COPY2]](<16 x s8>)
+ ; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
@@ -1249,8 +1226,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(sgt), [[COPY]](<8 x s8>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>)
- ; CHECK: $d0 = COPY [[COPY2]](<8 x s8>)
+ ; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
@@ -1339,8 +1315,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sge), [[COPY]](<2 x s32>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>)
- ; CHECK: $d0 = COPY [[COPY2]](<2 x s32>)
+ ; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
@@ -1399,8 +1374,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(sge), [[COPY]](<4 x s16>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>)
- ; CHECK: $d0 = COPY [[COPY2]](<4 x s16>)
+ ; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
@@ -1429,8 +1403,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sge), [[COPY]](<16 x s8>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
- ; CHECK: $q0 = COPY [[COPY2]](<16 x s8>)
+ ; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
@@ -1459,8 +1432,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(sge), [[COPY]](<8 x s8>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>)
- ; CHECK: $d0 = COPY [[COPY2]](<8 x s8>)
+ ; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
@@ -1549,8 +1521,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(slt), [[COPY]](<2 x s32>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>)
- ; CHECK: $d0 = COPY [[COPY2]](<2 x s32>)
+ ; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
@@ -1609,8 +1580,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(slt), [[COPY]](<4 x s16>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>)
- ; CHECK: $d0 = COPY [[COPY2]](<4 x s16>)
+ ; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
@@ -1639,8 +1609,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(slt), [[COPY]](<16 x s8>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
- ; CHECK: $q0 = COPY [[COPY2]](<16 x s8>)
+ ; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
@@ -1669,8 +1638,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(slt), [[COPY]](<8 x s8>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>)
- ; CHECK: $d0 = COPY [[COPY2]](<8 x s8>)
+ ; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
@@ -1759,8 +1727,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sle), [[COPY]](<2 x s32>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[ICMP]](<2 x s32>)
- ; CHECK: $d0 = COPY [[COPY2]](<2 x s32>)
+ ; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
@@ -1819,8 +1786,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(sle), [[COPY]](<4 x s16>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY [[ICMP]](<4 x s16>)
- ; CHECK: $d0 = COPY [[COPY2]](<4 x s16>)
+ ; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
@@ -1849,8 +1815,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sle), [[COPY]](<16 x s8>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY [[ICMP]](<16 x s8>)
- ; CHECK: $q0 = COPY [[COPY2]](<16 x s8>)
+ ; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = COPY $q1
@@ -1879,8 +1844,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(sle), [[COPY]](<8 x s8>), [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY [[ICMP]](<8 x s8>)
- ; CHECK: $d0 = COPY [[COPY2]](<8 x s8>)
+ ; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
; CHECK: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = COPY $d1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
index b4a37ccbff35c..e25e93064f811 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
@@ -19,22 +19,17 @@ body: |
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 46
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](s32), [[C1]]
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; CHECK: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[DEF1]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
+ ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ICMP]], [[DEF1]]
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -33
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[C3]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[C3]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 26
; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND2]](s32), [[C4]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY4]], [[COPY5]]
+ ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ICMP1]], [[OR]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[OR1]](s32)
; CHECK: G_BRCOND [[TRUNC]](s1), %bb.2
; CHECK: bb.2:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner.mir
index 2a08de43cd2e1..efc7e7ac6deae 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner.mir
@@ -22,11 +22,9 @@ body: |
liveins: $w0
; CHECK-LABEL: name: test_legal_const_ext
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: $w0 = COPY [[COPY2]](s32)
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]]
+ ; CHECK: $w0 = COPY [[ADD]](s32)
%0:_(s32) = COPY $w0
%1:_(s1) = G_TRUNC %0(s32)
%2:_(s1) = G_CONSTANT i1 2
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/retry-artifact-combine.mir b/llvm/test/CodeGen/AArch64/GlobalISel/retry-artifact-combine.mir
index 656806a448e83..d429c22522805 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/retry-artifact-combine.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/retry-artifact-combine.mir
@@ -9,11 +9,9 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ogt), [[COPY]](s32), [[COPY1]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; CHECK: $w0 = COPY [[COPY3]](s32)
+ ; CHECK: $w0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s1) = G_FCMP floatpred(ogt), %0(s32), %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir
index 3c86dd903a066..faf99d57a5ea7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir
@@ -9,8 +9,7 @@ body: |
; CHECK-LABEL: name: test_anyext_trunc_v2s32_to_v2s16_to_v2s32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY [[COPY]](<2 x s32>)
- ; CHECK: $vgpr0_vgpr1 = COPY [[COPY1]](<2 x s32>)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[COPY]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s16>) = G_TRUNC %0
%2:_(<2 x s32>) = G_ANYEXT %1
@@ -60,8 +59,7 @@ body: |
; CHECK-LABEL: name: test_anyext_trunc_v3s32_to_v3s16_to_v3s32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
- ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](<3 x s32>)
+ ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[COPY]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s16>) = G_TRUNC %0
%2:_(<3 x s32>) = G_ANYEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-concat-vectors.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-concat-vectors.mir
index af64874e874a4..9679bc4af52a4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-concat-vectors.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-concat-vectors.mir
@@ -20,18 +20,14 @@ body: |
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[LSHR]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR1]](s32), [[LSHR2]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[C3]](s32)
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[C3]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[SHL1:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]](<2 x s16>)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[SHL]](<2 x s16>), [[SHL1]](<2 x s16>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
index 63aabbcbb1135..79a4fb5d44614 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
@@ -418,8 +418,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
+ ; CHECK: $vgpr0 = COPY [[BITCAST]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
%2:_(<4 x s16>) = G_CONCAT_VECTORS %0, %1
@@ -440,8 +439,7 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
%2:_(<4 x s16>) = G_CONCAT_VECTORS %0, %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
index 9cc947bfc3a82..2b5ce8e3f2844 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
@@ -9,8 +9,7 @@ body: |
; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s16_to_v2s32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY [[COPY]](<2 x s32>)
- ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
@@ -53,15 +52,11 @@ body: |
; CHECK-LABEL: name: test_sext_trunc_v2s32_to_v2s8_to_v2s16
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 8
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -81,8 +76,7 @@ body: |
; CHECK-LABEL: name: test_sext_trunc_v3s32_to_v3s16_to_v3s32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
- ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
index 657b9ebee5858..69dff1a7b21fc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
@@ -14,10 +14,8 @@ body: |
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV3]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
@@ -53,10 +51,8 @@ body: |
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV3]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
@@ -223,14 +219,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 1
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 1
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 1
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 1
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 1
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV3]], 1
; CHECK: $vgpr0 = COPY [[SEXT_INREG]](s32)
; CHECK: $vgpr1 = COPY [[SEXT_INREG1]](s32)
; CHECK: $vgpr2 = COPY [[SEXT_INREG2]](s32)
@@ -534,14 +526,10 @@ body: |
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND2]](s32), [[AND3]](s32)
; CHECK: S_ENDPGM 0, implicit [[MV]](s64), implicit [[MV1]](s64)
@@ -587,39 +575,27 @@ body: |
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[LSHR]](s32), [[BITCAST1]](s32)
; CHECK: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32)
+ ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR2]](s32), [[BITCAST3]](s32), [[LSHR3]](s32)
; CHECK: [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
; CHECK: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; CHECK: [[UV8:%[0-9]+]]:_(<2 x s16>), [[UV9:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<4 x s16>)
; CHECK: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV8]](<2 x s16>)
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+ ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[BITCAST4]](s32), [[LSHR4]](s32), [[BITCAST5]](s32)
; CHECK: [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<4 x s16>)
; CHECK: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[UV10]](<2 x s16>)
; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; CHECK: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV11]](<2 x s16>)
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32)
+ ; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR6]](s32), [[BITCAST7]](s32), [[LSHR7]](s32)
; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<3 x s32>), implicit [[BUILD_VECTOR1]](<3 x s32>), implicit [[BUILD_VECTOR2]](<3 x s32>), implicit [[BUILD_VECTOR3]](<3 x s32>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<4 x s16>) = COPY $vgpr2_vgpr3
@@ -646,31 +622,19 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 8
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 8
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY12]], 8
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY13]], 8
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C]]
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG3]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C]]
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG2]], [[C]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG3]], [[C]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -708,57 +672,33 @@ body: |
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY12]], 8
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY13]], 8
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C]]
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY16]], 8
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY17]], 8
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C]]
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG3]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C]]
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG2]], [[C]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG3]], [[C]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY20]](s32)
- ; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY24]], 8
- ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY21]](s32)
- ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY25]], 8
- ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG4]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C]]
- ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG5]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C]]
+ ; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
+ ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 8
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG4]], [[C]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG5]], [[C]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[COPY22]](s32)
- ; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY28]], 8
- ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[COPY23]](s32)
- ; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY29]], 8
- ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG6]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C]]
- ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG7]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C]]
+ ; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 8
+ ; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 8
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG6]], [[C]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG7]], [[C]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C1]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CHECK: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
@@ -812,109 +752,61 @@ body: |
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr13
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr14
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr15
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY24]], 8
- ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY25]], 8
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C]]
- ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY28]], 8
- ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[COPY19]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY29]], 8
- ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C]]
- ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG3]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C]]
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG2]], [[C]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG3]], [[C]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[COPY20]](s32)
- ; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY32]], 8
- ; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[COPY21]](s32)
- ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY33]], 8
- ; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG4]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY34]], [[C]]
- ; CHECK: [[COPY35:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG5]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY35]], [[C]]
+ ; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
+ ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 8
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG4]], [[C]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG5]], [[C]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; CHECK: [[COPY36:%[0-9]+]]:_(s32) = COPY [[COPY22]](s32)
- ; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY36]], 8
- ; CHECK: [[COPY37:%[0-9]+]]:_(s32) = COPY [[COPY23]](s32)
- ; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY37]], 8
- ; CHECK: [[COPY38:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG6]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY38]], [[C]]
- ; CHECK: [[COPY39:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG7]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY39]], [[C]]
+ ; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 8
+ ; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 8
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG6]], [[C]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG7]], [[C]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C1]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CHECK: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
- ; CHECK: [[COPY40:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
- ; CHECK: [[COPY41:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; CHECK: [[COPY42:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; CHECK: [[COPY43:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
- ; CHECK: [[COPY44:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; CHECK: [[COPY45:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; CHECK: [[COPY46:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; CHECK: [[COPY47:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; CHECK: [[COPY48:%[0-9]+]]:_(s32) = COPY [[COPY40]](s32)
- ; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY48]], 8
- ; CHECK: [[COPY49:%[0-9]+]]:_(s32) = COPY [[COPY41]](s32)
- ; CHECK: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY49]], 8
- ; CHECK: [[COPY50:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG8]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY50]], [[C]]
- ; CHECK: [[COPY51:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG9]](s32)
- ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY51]], [[C]]
+ ; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 8
+ ; CHECK: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 8
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG8]], [[C]]
+ ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG9]], [[C]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C1]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; CHECK: [[COPY52:%[0-9]+]]:_(s32) = COPY [[COPY42]](s32)
- ; CHECK: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY52]], 8
- ; CHECK: [[COPY53:%[0-9]+]]:_(s32) = COPY [[COPY43]](s32)
- ; CHECK: [[SEXT_INREG11:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY53]], 8
- ; CHECK: [[COPY54:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG10]](s32)
- ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY54]], [[C]]
- ; CHECK: [[COPY55:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG11]](s32)
- ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY55]], [[C]]
+ ; CHECK: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY10]], 8
+ ; CHECK: [[SEXT_INREG11:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY11]], 8
+ ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG10]], [[C]]
+ ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG11]], [[C]]
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C1]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
- ; CHECK: [[COPY56:%[0-9]+]]:_(s32) = COPY [[COPY44]](s32)
- ; CHECK: [[SEXT_INREG12:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY56]], 8
- ; CHECK: [[COPY57:%[0-9]+]]:_(s32) = COPY [[COPY45]](s32)
- ; CHECK: [[SEXT_INREG13:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY57]], 8
- ; CHECK: [[COPY58:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG12]](s32)
- ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY58]], [[C]]
- ; CHECK: [[COPY59:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG13]](s32)
- ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY59]], [[C]]
+ ; CHECK: [[SEXT_INREG12:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY12]], 8
+ ; CHECK: [[SEXT_INREG13:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY13]], 8
+ ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG12]], [[C]]
+ ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG13]], [[C]]
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C1]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL6]]
; CHECK: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR6]](s32)
- ; CHECK: [[COPY60:%[0-9]+]]:_(s32) = COPY [[COPY46]](s32)
- ; CHECK: [[SEXT_INREG14:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY60]], 8
- ; CHECK: [[COPY61:%[0-9]+]]:_(s32) = COPY [[COPY47]](s32)
- ; CHECK: [[SEXT_INREG15:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY61]], 8
- ; CHECK: [[COPY62:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG14]](s32)
- ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY62]], [[C]]
- ; CHECK: [[COPY63:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG15]](s32)
- ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY63]], [[C]]
+ ; CHECK: [[SEXT_INREG14:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY14]], 8
+ ; CHECK: [[SEXT_INREG15:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY15]], 8
+ ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG14]], [[C]]
+ ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG15]], [[C]]
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C1]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND14]], [[SHL7]]
; CHECK: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR7]](s32)
@@ -1274,9 +1166,7 @@ body: |
; CHECK-LABEL: name: test_unmerge_values_v2s8_v4s8_trunc_v4s16
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY [[UV]](<2 x s16>)
- ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s16>) = COPY [[UV1]](<2 x s16>)
- ; CHECK: S_ENDPGM 0, implicit [[COPY1]](<2 x s16>), implicit [[COPY2]](<2 x s16>)
+ ; CHECK: S_ENDPGM 0, implicit [[UV]](<2 x s16>), implicit [[UV1]](<2 x s16>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<4 x s8>) = G_TRUNC %0
%2:_(<2 x s8>), %3:_(<2 x s8>) = G_UNMERGE_VALUES %1
@@ -1444,10 +1334,7 @@ body: |
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR2]](s32), [[BITCAST3]](s32), [[LSHR3]](s32)
; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s16), implicit [[TRUNC1]](s16), implicit [[TRUNC2]](s16), implicit [[BUILD_VECTOR]](<3 x s32>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s16>), %2:_(<3 x s16>) = G_UNMERGE_VALUES %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
index 5b62d03180f2a..701da8e0f119a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
@@ -11,8 +11,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY [[COPY]](<2 x s32>)
- ; CHECK: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY1]], [[BUILD_VECTOR]]
+ ; CHECK: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[COPY]], [[BUILD_VECTOR]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s16>) = G_TRUNC %0
@@ -74,8 +73,7 @@ body: |
; CHECK-LABEL: name: test_zext_trunc_v3s32_to_v3s16_to_v3s32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
- ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32)
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV2]](s32), [[DEF]](s32)
@@ -172,8 +170,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LOAD]], 8
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG]], [[C]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
@@ -200,10 +197,8 @@ body: |
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)
@@ -232,10 +227,8 @@ body: |
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)
@@ -262,14 +255,10 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C3]](s32), [[C3]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LOAD]], 8
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 8
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND]](<2 x s32>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir
index 2c9b239f1d54c..759ffcd28ad8f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir
@@ -9,8 +9,7 @@ body: |
; CHECK-LABEL: name: test_sext_trunc_i64_i32_i64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; CHECK: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_TRUNC %0
@@ -27,8 +26,7 @@ body: |
; CHECK-LABEL: name: test_zext_trunc_i64_i32_i64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_TRUNC %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
index 81f6b8e71254c..8a957d1019125 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/dummy-target.ll
@@ -54,12 +54,10 @@ define i16 @halfinsts_add_i16(i16 %arg0) #1 {
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
- ; CHECK: S_SETPC_B64_return [[COPY4]], implicit $vgpr0
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
+ ; CHECK: $vgpr0 = COPY [[ADD]](s32)
+ ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
+ ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
%add = add i16 %arg0, %arg0
ret i16 %add
}
@@ -71,18 +69,12 @@ define <2 x i16> @halfinsts_add_v2i16(<2 x i16> %arg0) #1 {
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY3]], [[COPY4]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY5]], [[COPY6]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY7]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY8]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
- ; CHECK: S_SETPC_B64_return [[COPY9]], implicit $vgpr0, implicit $vgpr1
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY1]]
+ ; CHECK: $vgpr0 = COPY [[ADD]](s32)
+ ; CHECK: $vgpr1 = COPY [[ADD1]](s32)
+ ; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
+ ; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0, implicit $vgpr1
%add = add <2 x i16> %arg0, %arg0
ret <2 x i16> %add
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
index f25d1939bfa9a..d8abab5e208d6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
@@ -656,27 +656,27 @@ define i16 @v_fshl_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) {
; GFX6-LABEL: v_fshl_v2i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_and_b32_e32 v6, 0xff, v1
-; GFX6-NEXT: v_lshrrev_b32_e32 v4, 8, v2
; GFX6-NEXT: v_and_b32_e32 v5, 7, v2
-; GFX6-NEXT: v_xor_b32_e32 v2, -1, v2
-; GFX6-NEXT: v_and_b32_e32 v2, 7, v2
-; GFX6-NEXT: v_lshrrev_b32_e32 v6, 1, v6
+; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, 8, v2
+; GFX6-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v5, v0
-; GFX6-NEXT: v_lshrrev_b32_e32 v2, v2, v6
-; GFX6-NEXT: v_bfe_u32 v1, v1, 8, 8
+; GFX6-NEXT: v_and_b32_e32 v5, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v2, 7, v2
+; GFX6-NEXT: v_lshrrev_b32_e32 v5, 1, v5
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, v2, v5
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_and_b32_e32 v2, 7, v4
; GFX6-NEXT: v_xor_b32_e32 v4, -1, v4
+; GFX6-NEXT: v_bfe_u32 v1, v1, 8, 8
; GFX6-NEXT: v_and_b32_e32 v4, 7, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v2, v2, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v1, v4, v1
-; GFX6-NEXT: v_mov_b32_e32 v5, 0xff
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_and_b32_e32 v1, v1, v5
-; GFX6-NEXT: v_and_b32_e32 v0, v0, v5
+; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -710,22 +710,22 @@ define i16 @v_fshl_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) {
; GFX9-LABEL: v_fshl_v2i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v6, 7, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v2
+; GFX9-NEXT: v_and_b32_e32 v6, 7, v2
; GFX9-NEXT: v_xor_b32_e32 v2, -1, v2
-; GFX9-NEXT: v_lshlrev_b16_e32 v0, v6, v0
-; GFX9-NEXT: v_mov_b32_e32 v6, 1
+; GFX9-NEXT: s_mov_b32 s4, 1
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 8, v1
; GFX9-NEXT: v_and_b32_e32 v2, 7, v2
-; GFX9-NEXT: v_lshrrev_b16_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_lshrrev_b16_sdwa v1, s4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v0
; GFX9-NEXT: v_lshrrev_b16_e32 v1, v2, v1
+; GFX9-NEXT: v_lshlrev_b16_e32 v0, v6, v0
; GFX9-NEXT: v_xor_b32_e32 v2, -1, v5
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: v_and_b32_e32 v1, 7, v5
; GFX9-NEXT: v_lshlrev_b16_e32 v1, v1, v3
; GFX9-NEXT: v_and_b32_e32 v2, 7, v2
-; GFX9-NEXT: v_lshrrev_b16_sdwa v3, v6, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_lshrrev_b16_sdwa v3, s4, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_lshrrev_b16_e32 v2, v2, v3
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: v_and_b32_e32 v1, 0xff, v1
@@ -1071,12 +1071,13 @@ define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX8-NEXT: v_lshrrev_b16_e32 v6, 1, v6
; GFX8-NEXT: v_lshrrev_b16_e32 v5, v5, v6
; GFX8-NEXT: v_lshlrev_b16_sdwa v4, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_xor_b32_e32 v6, -1, v7
; GFX8-NEXT: v_or_b32_e32 v4, v4, v5
; GFX8-NEXT: v_and_b32_e32 v5, 7, v7
-; GFX8-NEXT: v_and_b32_e32 v6, 7, v6
-; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX8-NEXT: v_xor_b32_e32 v6, -1, v7
; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX8-NEXT: v_mov_b32_e32 v5, 1
+; GFX8-NEXT: v_and_b32_e32 v6, 7, v6
+; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
; GFX8-NEXT: v_lshrrev_b16_e32 v1, v6, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_mov_b32_e32 v1, 8
@@ -1095,22 +1096,22 @@ define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v8, 7, v2
-; GFX9-NEXT: v_mov_b32_e32 v10, 1
+; GFX9-NEXT: s_mov_b32 s5, 1
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v2
; GFX9-NEXT: v_xor_b32_e32 v2, -1, v2
; GFX9-NEXT: v_and_b32_e32 v2, 7, v2
-; GFX9-NEXT: v_lshrrev_b16_sdwa v11, v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_lshrrev_b16_sdwa v10, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_lshlrev_b16_e32 v8, v8, v0
-; GFX9-NEXT: v_lshrrev_b16_e32 v2, v2, v11
+; GFX9-NEXT: v_lshrrev_b16_e32 v2, v2, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 8, v1
; GFX9-NEXT: v_or_b32_e32 v2, v8, v2
; GFX9-NEXT: v_and_b32_e32 v8, 7, v5
; GFX9-NEXT: v_xor_b32_e32 v5, -1, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v0
; GFX9-NEXT: v_and_b32_e32 v5, 7, v5
-; GFX9-NEXT: v_lshrrev_b16_sdwa v4, v10, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NEXT: v_lshrrev_b16_sdwa v4, s5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_lshrrev_b16_e32 v4, v5, v4
; GFX9-NEXT: v_lshlrev_b16_e32 v3, v8, v3
; GFX9-NEXT: v_mov_b32_e32 v9, 0xff
@@ -1122,12 +1123,13 @@ define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX9-NEXT: v_lshrrev_b16_e32 v6, 1, v6
; GFX9-NEXT: v_lshrrev_b16_e32 v5, v5, v6
; GFX9-NEXT: v_lshlrev_b16_sdwa v4, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX9-NEXT: v_xor_b32_e32 v6, -1, v7
; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
; GFX9-NEXT: v_and_b32_e32 v5, 7, v7
-; GFX9-NEXT: v_and_b32_e32 v6, 7, v6
-; GFX9-NEXT: v_lshrrev_b16_sdwa v1, v10, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX9-NEXT: v_xor_b32_e32 v6, -1, v7
; GFX9-NEXT: v_lshlrev_b16_sdwa v0, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX9-NEXT: v_mov_b32_e32 v5, 1
+; GFX9-NEXT: v_and_b32_e32 v6, 7, v6
+; GFX9-NEXT: v_lshrrev_b16_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
; GFX9-NEXT: v_lshrrev_b16_e32 v1, v6, v1
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v1, 8
@@ -1465,31 +1467,33 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 inreg %amt.arg) {
; GFX6-LABEL: s_fshl_v2i24:
; GFX6: ; %bb.0:
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_movk_i32 s9, 0xff
; GFX6-NEXT: s_mov_b32 s11, 0x80008
; GFX6-NEXT: s_lshr_b32 s6, s0, 16
-; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX6-NEXT: s_lshr_b32 s7, s0, 24
; GFX6-NEXT: s_and_b32 s10, s0, s9
; GFX6-NEXT: s_bfe_u32 s0, s0, s11
; GFX6-NEXT: s_lshl_b32 s0, s0, 8
; GFX6-NEXT: s_and_b32 s6, s6, s9
-; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX6-NEXT: s_or_b32 s0, s10, s0
; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX6-NEXT: s_lshr_b32 s8, s1, 8
; GFX6-NEXT: s_and_b32 s1, s1, s9
; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_or_b32 s0, s0, s6
; GFX6-NEXT: s_and_b32 s6, s8, s9
; GFX6-NEXT: s_or_b32 s1, s7, s1
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
+; GFX6-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX6-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
-; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, v0
; GFX6-NEXT: s_or_b32 s1, s1, s6
; GFX6-NEXT: s_lshr_b32 s6, s2, 16
; GFX6-NEXT: s_lshr_b32 s7, s2, 24
@@ -1499,20 +1503,18 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_and_b32 s6, s6, s9
; GFX6-NEXT: s_or_b32 s2, s10, s2
; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
-; GFX6-NEXT: v_mov_b32_e32 v2, 0xffffffe8
-; GFX6-NEXT: v_mul_lo_u32 v3, v2, v1
; GFX6-NEXT: s_lshr_b32 s8, s3, 8
; GFX6-NEXT: s_and_b32 s3, s3, s9
; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
; GFX6-NEXT: s_lshl_b32 s3, s3, 8
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX6-NEXT: s_or_b32 s2, s2, s6
; GFX6-NEXT: s_and_b32 s6, s8, s9
; GFX6-NEXT: s_or_b32 s3, s7, s3
; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
; GFX6-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
-; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: s_or_b32 s3, s3, s6
; GFX6-NEXT: s_lshr_b32 s6, s4, 16
; GFX6-NEXT: s_lshr_b32 s7, s4, 24
@@ -1520,76 +1522,78 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_bfe_u32 s4, s4, s11
; GFX6-NEXT: s_lshl_b32 s4, s4, 8
; GFX6-NEXT: s_and_b32 s6, s6, s9
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, 24
; GFX6-NEXT: s_or_b32 s4, s10, s4
; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
; GFX6-NEXT: s_or_b32 s4, s4, s6
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT: v_mul_hi_u32 v1, s4, v1
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX6-NEXT: s_lshr_b32 s8, s5, 8
-; GFX6-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX6-NEXT: s_and_b32 s5, s5, s9
-; GFX6-NEXT: v_mul_lo_u32 v2, v2, v0
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, v2
; GFX6-NEXT: s_lshl_b32 s5, s5, 8
-; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s4, v1
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v1
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
+; GFX6-NEXT: v_mul_hi_u32 v1, v2, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-NEXT: s_and_b32 s6, s8, s9
; GFX6-NEXT: s_or_b32 s5, s7, s5
; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v1
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX6-NEXT: s_bfe_u32 s5, s5, 0x100000
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-NEXT: s_or_b32 s5, s5, s6
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v0, s5, v0
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; GFX6-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX6-NEXT: s_mov_b32 s6, 0xffffff
-; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v1
-; GFX6-NEXT: v_and_b32_e32 v1, s6, v1
-; GFX6-NEXT: v_mul_lo_u32 v0, v0, 24
-; GFX6-NEXT: v_lshl_b32_e32 v1, s0, v1
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v0
+; GFX6-NEXT: v_and_b32_e32 v0, s6, v0
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX6-NEXT: v_lshl_b32_e32 v0, s0, v0
; GFX6-NEXT: s_lshr_b32 s0, s2, 1
; GFX6-NEXT: v_and_b32_e32 v2, s6, v3
; GFX6-NEXT: v_lshr_b32_e32 v2, s0, v2
-; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
-; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: v_mov_b32_e32 v4, 0xffffff
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 23, v0
-; GFX6-NEXT: v_and_b32_e32 v0, v0, v4
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 23, v1
+; GFX6-NEXT: v_and_b32_e32 v1, v1, v4
; GFX6-NEXT: s_lshr_b32 s0, s3, 1
; GFX6-NEXT: v_and_b32_e32 v2, v2, v4
-; GFX6-NEXT: v_bfe_u32 v3, v1, 8, 8
-; GFX6-NEXT: v_lshl_b32_e32 v0, s1, v0
+; GFX6-NEXT: v_bfe_u32 v3, v0, 8, 8
+; GFX6-NEXT: v_lshl_b32_e32 v1, s1, v1
; GFX6-NEXT: v_lshr_b32_e32 v2, s0, v2
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT: v_and_b32_e32 v2, s9, v1
-; GFX6-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_and_b32_e32 v2, s9, v0
-; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX6-NEXT: v_bfe_u32 v2, v0, 8, 8
+; GFX6-NEXT: v_and_b32_e32 v2, s9, v0
; GFX6-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_readfirstlane_b32 s0, v1
-; GFX6-NEXT: v_readfirstlane_b32 s1, v0
+; GFX6-NEXT: v_and_b32_e32 v2, s9, v1
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX6-NEXT: v_bfe_u32 v2, v1, 8, 8
+; GFX6-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_fshl_v2i24:
@@ -1604,32 +1608,34 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_lshl_b32 s6, s6, s11
; GFX8-NEXT: s_or_b32 s0, s0, s6
; GFX8-NEXT: s_and_b32 s6, s7, s10
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_lshr_b32 s9, s1, 8
; GFX8-NEXT: s_and_b32 s1, s1, s10
; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
; GFX8-NEXT: s_lshl_b32 s1, s1, s11
-; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX8-NEXT: s_or_b32 s0, s0, s6
; GFX8-NEXT: s_and_b32 s6, s9, s10
; GFX8-NEXT: s_or_b32 s1, s8, s1
; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
; GFX8-NEXT: s_or_b32 s1, s1, s6
; GFX8-NEXT: s_lshr_b32 s6, s2, 8
+; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_and_b32 s6, s6, s10
-; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX8-NEXT: s_lshr_b32 s7, s2, 16
; GFX8-NEXT: s_lshr_b32 s8, s2, 24
; GFX8-NEXT: s_and_b32 s2, s2, s10
; GFX8-NEXT: s_lshl_b32 s6, s6, s11
; GFX8-NEXT: s_or_b32 s2, s2, s6
; GFX8-NEXT: s_and_b32 s6, s7, s10
-; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX8-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000
+; GFX8-NEXT: v_mul_lo_u32 v2, v1, v0
; GFX8-NEXT: s_lshr_b32 s9, s3, 8
; GFX8-NEXT: s_and_b32 s3, s3, s10
; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
@@ -1637,96 +1643,100 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_lshl_b32 s3, s3, s11
; GFX8-NEXT: s_or_b32 s2, s2, s6
; GFX8-NEXT: s_and_b32 s6, s9, s10
-; GFX8-NEXT: v_mov_b32_e32 v2, 0xffffffe8
; GFX8-NEXT: s_or_b32 s3, s8, s3
; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000
-; GFX8-NEXT: v_mul_lo_u32 v3, v2, v1
+; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
; GFX8-NEXT: s_or_b32 s3, s3, s6
; GFX8-NEXT: s_lshr_b32 s6, s4, 8
; GFX8-NEXT: s_and_b32 s6, s6, s10
-; GFX8-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX8-NEXT: s_lshr_b32 s7, s4, 16
; GFX8-NEXT: s_lshr_b32 s8, s4, 24
; GFX8-NEXT: s_and_b32 s4, s4, s10
; GFX8-NEXT: s_lshl_b32 s6, s6, s11
; GFX8-NEXT: s_or_b32 s4, s4, s6
; GFX8-NEXT: s_and_b32 s6, s7, s10
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v2, 24
; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
; GFX8-NEXT: s_or_b32 s4, s4, s6
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
-; GFX8-NEXT: v_mul_hi_u32 v1, s4, v1
-; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX8-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
+; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX8-NEXT: s_lshr_b32 s9, s5, 8
-; GFX8-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX8-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX8-NEXT: s_and_b32 s5, s5, s10
-; GFX8-NEXT: v_mul_lo_u32 v2, v2, v0
+; GFX8-NEXT: v_mul_lo_u32 v1, v1, v2
; GFX8-NEXT: s_lshl_b32 s5, s5, s11
-; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s4, v1
-; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v1
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0
+; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v0
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
+; GFX8-NEXT: v_mul_hi_u32 v1, v2, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: s_and_b32 s6, s9, s10
; GFX8-NEXT: s_or_b32 s5, s8, s5
; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000
-; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v1
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v0
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX8-NEXT: s_bfe_u32 s5, s5, 0x100000
; GFX8-NEXT: s_lshl_b32 s6, s6, 16
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: s_or_b32 s5, s5, s6
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
-; GFX8-NEXT: v_mul_hi_u32 v0, s5, v0
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, v2, v1
+; GFX8-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX8-NEXT: s_mov_b32 s6, 0xffffff
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v1
-; GFX8-NEXT: v_and_b32_e32 v1, s6, v1
-; GFX8-NEXT: v_mul_lo_u32 v0, v0, 24
-; GFX8-NEXT: v_lshlrev_b32_e64 v1, v1, s0
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v0
+; GFX8-NEXT: v_and_b32_e32 v0, s6, v0
+; GFX8-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX8-NEXT: v_lshlrev_b32_e64 v0, v0, s0
; GFX8-NEXT: s_lshr_b32 s0, s2, 1
; GFX8-NEXT: v_and_b32_e32 v2, s6, v3
; GFX8-NEXT: v_lshrrev_b32_e64 v2, v2, s0
-; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s5, v0
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v0
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v0
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s5, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX8-NEXT: v_mov_b32_e32 v4, 0xffffff
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 23, v0
-; GFX8-NEXT: v_and_b32_e32 v0, v0, v4
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 23, v1
+; GFX8-NEXT: v_and_b32_e32 v1, v1, v4
; GFX8-NEXT: v_and_b32_e32 v2, v2, v4
; GFX8-NEXT: s_lshr_b32 s0, s3, 1
-; GFX8-NEXT: v_lshlrev_b32_e64 v0, v0, s1
+; GFX8-NEXT: v_lshlrev_b32_e64 v1, v1, s1
; GFX8-NEXT: v_lshrrev_b32_e64 v2, v2, s0
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: v_mov_b32_e32 v2, 8
-; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX8-NEXT: v_mov_b32_e32 v4, 16
-; GFX8-NEXT: v_or_b32_sdwa v3, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-; GFX8-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX8-NEXT: v_and_b32_e32 v3, s10, v0
-; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX8-NEXT: v_or_b32_sdwa v3, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX8-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX8-NEXT: v_and_b32_e32 v3, s10, v1
+; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX8-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX8-NEXT: v_readfirstlane_b32 s0, v1
-; GFX8-NEXT: v_readfirstlane_b32 s1, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
+; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_fshl_v2i24:
; GFX9: ; %bb.0:
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_lshr_b32 s7, s0, 8
; GFX9-NEXT: s_movk_i32 s12, 0xff
; GFX9-NEXT: s_and_b32 s7, s7, s12
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX9-NEXT: s_bfe_u32 s13, 8, 0x100000
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_lshr_b32 s9, s0, 16
; GFX9-NEXT: s_lshr_b32 s10, s0, 24
; GFX9-NEXT: s_and_b32 s0, s0, s12
@@ -1734,31 +1744,33 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_or_b32 s0, s0, s7
; GFX9-NEXT: s_and_b32 s7, s9, s12
; GFX9-NEXT: s_bfe_u32 s7, s7, 0x100000
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xffffffe8
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v0
; GFX9-NEXT: s_lshr_b32 s11, s1, 8
; GFX9-NEXT: s_and_b32 s1, s1, s12
; GFX9-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX9-NEXT: s_lshl_b32 s7, s7, 16
; GFX9-NEXT: s_lshl_b32 s1, s1, s13
-; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
; GFX9-NEXT: s_or_b32 s0, s0, s7
; GFX9-NEXT: s_and_b32 s7, s11, s12
; GFX9-NEXT: s_or_b32 s1, s10, s1
; GFX9-NEXT: s_bfe_u32 s7, s7, 0x100000
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX9-NEXT: s_lshl_b32 s7, s7, 16
+; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: s_or_b32 s1, s1, s7
; GFX9-NEXT: s_lshr_b32 s7, s2, 8
; GFX9-NEXT: s_and_b32 s7, s7, s12
-; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX9-NEXT: s_lshr_b32 s9, s2, 16
; GFX9-NEXT: s_lshr_b32 s10, s2, 24
; GFX9-NEXT: s_and_b32 s2, s2, s12
; GFX9-NEXT: s_lshl_b32 s7, s7, s13
; GFX9-NEXT: s_or_b32 s2, s2, s7
; GFX9-NEXT: s_and_b32 s7, s9, s12
-; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX9-NEXT: s_bfe_u32 s7, s7, 0x100000
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v2, 24
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX9-NEXT: s_lshr_b32 s11, s3, 8
; GFX9-NEXT: s_and_b32 s3, s3, s12
; GFX9-NEXT: s_bfe_u32 s2, s2, 0x100000
@@ -1766,18 +1778,15 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_or_b32 s2, s2, s7
; GFX9-NEXT: s_and_b32 s7, s11, s12
; GFX9-NEXT: s_lshl_b32 s3, s3, s13
-; GFX9-NEXT: v_mov_b32_e32 v2, 0xffffffe8
; GFX9-NEXT: s_or_b32 s3, s10, s3
; GFX9-NEXT: s_bfe_u32 s7, s7, 0x100000
-; GFX9-NEXT: v_mul_lo_u32 v3, v2, v1
; GFX9-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX9-NEXT: s_lshl_b32 s7, s7, 16
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GFX9-NEXT: s_or_b32 s3, s3, s7
; GFX9-NEXT: s_lshr_b32 s7, s4, 8
; GFX9-NEXT: s_and_b32 s7, s7, s12
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX9-NEXT: s_lshr_b32 s9, s4, 16
; GFX9-NEXT: s_lshr_b32 s10, s4, 24
; GFX9-NEXT: s_and_b32 s4, s4, s12
@@ -1785,193 +1794,194 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_or_b32 s4, s4, s7
; GFX9-NEXT: s_and_b32 s7, s9, s12
; GFX9-NEXT: s_bfe_u32 s7, s7, 0x100000
-; GFX9-NEXT: v_mul_lo_u32 v2, v2, v0
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, v2
; GFX9-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX9-NEXT: s_lshl_b32 s7, s7, 16
; GFX9-NEXT: s_or_b32 s4, s4, s7
-; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT: v_mul_hi_u32 v1, s4, v1
+; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX9-NEXT: s_lshr_b32 s11, s5, 8
; GFX9-NEXT: s_and_b32 s5, s5, s12
-; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v1, v2, v1
; GFX9-NEXT: s_lshl_b32 s5, s5, s13
; GFX9-NEXT: s_and_b32 s7, s11, s12
; GFX9-NEXT: s_or_b32 s5, s10, s5
; GFX9-NEXT: s_bfe_u32 s7, s7, 0x100000
-; GFX9-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX9-NEXT: s_bfe_u32 s5, s5, 0x100000
; GFX9-NEXT: s_lshl_b32 s7, s7, 16
; GFX9-NEXT: s_or_b32 s5, s5, s7
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
-; GFX9-NEXT: v_mul_hi_u32 v0, s5, v0
-; GFX9-NEXT: v_sub_u32_e32 v1, s4, v1
-; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX9-NEXT: v_mul_lo_u32 v0, v0, 24
-; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX9-NEXT: s_mov_b32 s7, 0xffffff
-; GFX9-NEXT: v_sub_u32_e32 v3, 23, v1
-; GFX9-NEXT: s_lshr_b32 s2, s2, 1
-; GFX9-NEXT: v_and_b32_e32 v3, s7, v3
-; GFX9-NEXT: v_sub_u32_e32 v0, s5, v0
-; GFX9-NEXT: v_and_b32_e32 v1, s7, v1
-; GFX9-NEXT: v_lshrrev_b32_e64 v3, v3, s2
-; GFX9-NEXT: v_lshl_or_b32 v1, s0, v1, v3
+; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
+; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
+; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v0
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX9-NEXT: v_mov_b32_e32 v2, 0xffffff
+; GFX9-NEXT: s_mov_b32 s7, 0xffffff
; GFX9-NEXT: v_sub_u32_e32 v3, 23, v0
-; GFX9-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX9-NEXT: s_lshr_b32 s2, s2, 1
+; GFX9-NEXT: v_and_b32_e32 v3, s7, v3
+; GFX9-NEXT: v_sub_u32_e32 v1, s5, v1
+; GFX9-NEXT: v_and_b32_e32 v0, s7, v0
+; GFX9-NEXT: v_lshrrev_b32_e64 v3, v3, s2
+; GFX9-NEXT: v_lshl_or_b32 v0, s0, v0, v3
+; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_mov_b32_e32 v2, 0xffffff
+; GFX9-NEXT: v_sub_u32_e32 v3, 23, v1
+; GFX9-NEXT: v_and_b32_e32 v1, v1, v2
; GFX9-NEXT: s_lshr_b32 s0, s3, 1
; GFX9-NEXT: v_and_b32_e32 v2, v3, v2
; GFX9-NEXT: v_lshrrev_b32_e64 v2, v2, s0
-; GFX9-NEXT: v_lshl_or_b32 v0, s1, v0, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, s1, v1, v2
; GFX9-NEXT: s_mov_b32 s6, 8
-; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-; GFX9-NEXT: v_and_b32_e32 v3, s12, v0
+; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX9-NEXT: v_and_b32_e32 v3, s12, v1
; GFX9-NEXT: s_mov_b32 s8, 16
-; GFX9-NEXT: v_and_or_b32 v2, v1, s12, v2
-; GFX9-NEXT: v_lshlrev_b32_sdwa v1, s8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX9-NEXT: v_and_or_b32 v2, v0, s12, v2
+; GFX9-NEXT: v_lshlrev_b32_sdwa v0, s8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX9-NEXT: v_or3_b32 v1, v2, v1, v3
-; GFX9-NEXT: v_bfe_u32 v2, v0, 8, 8
-; GFX9-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, 8, v2
-; GFX9-NEXT: v_readfirstlane_b32 s0, v1
-; GFX9-NEXT: v_readfirstlane_b32 s1, v0
+; GFX9-NEXT: v_or3_b32 v0, v2, v0, v3
+; GFX9-NEXT: v_bfe_u32 v2, v1, 8, 8
+; GFX9-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 8, v2
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_fshl_v2i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, 24
; GFX10-NEXT: s_movk_i32 s9, 0xff
-; GFX10-NEXT: s_lshr_b32 s11, s1, 8
-; GFX10-NEXT: s_bfe_u32 s10, 8, 0x100000
-; GFX10-NEXT: s_and_b32 s1, s1, s9
+; GFX10-NEXT: s_lshr_b32 s10, s1, 8
+; GFX10-NEXT: s_bfe_u32 s11, 8, 0x100000
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX10-NEXT: s_and_b32 s1, s1, s9
; GFX10-NEXT: s_lshr_b32 s6, s0, 8
; GFX10-NEXT: s_lshr_b32 s8, s0, 24
-; GFX10-NEXT: s_lshl_b32 s1, s1, s10
+; GFX10-NEXT: s_lshl_b32 s1, s1, s11
; GFX10-NEXT: s_and_b32 s6, s6, s9
; GFX10-NEXT: s_or_b32 s1, s8, s1
; GFX10-NEXT: s_lshr_b32 s8, s4, 8
; GFX10-NEXT: s_lshr_b32 s7, s0, 16
+; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX10-NEXT: s_and_b32 s8, s8, s9
; GFX10-NEXT: s_and_b32 s0, s0, s9
-; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
-; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX10-NEXT: s_lshl_b32 s6, s6, s10
-; GFX10-NEXT: s_lshr_b32 s12, s4, 24
-; GFX10-NEXT: s_or_b32 s0, s0, s6
-; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX10-NEXT: s_lshl_b32 s6, s6, s11
; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX10-NEXT: s_or_b32 s0, s0, s6
; GFX10-NEXT: s_and_b32 s6, s7, s9
-; GFX10-NEXT: s_and_b32 s7, s11, s9
-; GFX10-NEXT: s_lshr_b32 s11, s4, 16
-; GFX10-NEXT: v_mul_lo_u32 v2, 0xffffffe8, v1
-; GFX10-NEXT: v_mul_lo_u32 v3, 0xffffffe8, v0
+; GFX10-NEXT: s_and_b32 s7, s10, s9
+; GFX10-NEXT: v_mul_lo_u32 v2, 0xffffffe8, v0
+; GFX10-NEXT: v_mul_lo_u32 v3, 0xffffffe8, v1
+; GFX10-NEXT: s_lshr_b32 s10, s4, 16
+; GFX10-NEXT: s_lshr_b32 s12, s4, 24
; GFX10-NEXT: s_and_b32 s4, s4, s9
-; GFX10-NEXT: s_lshl_b32 s8, s8, s10
+; GFX10-NEXT: s_lshl_b32 s8, s8, s11
; GFX10-NEXT: s_lshr_b32 s13, s5, 8
; GFX10-NEXT: s_or_b32 s4, s4, s8
-; GFX10-NEXT: s_and_b32 s8, s11, s9
-; GFX10-NEXT: s_and_b32 s5, s5, s9
-; GFX10-NEXT: v_mul_hi_u32 v2, v1, v2
-; GFX10-NEXT: v_mul_hi_u32 v3, v0, v3
+; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX10-NEXT: s_and_b32 s8, s10, s9
+; GFX10-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX10-NEXT: s_bfe_u32 s8, s8, 0x100000
+; GFX10-NEXT: s_and_b32 s5, s5, s9
; GFX10-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX10-NEXT: s_lshl_b32 s8, s8, 16
-; GFX10-NEXT: s_lshl_b32 s5, s5, s10
+; GFX10-NEXT: s_lshl_b32 s5, s5, s11
+; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
; GFX10-NEXT: s_or_b32 s4, s4, s8
; GFX10-NEXT: s_and_b32 s8, s13, s9
-; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX10-NEXT: s_or_b32 s5, s12, s5
; GFX10-NEXT: s_bfe_u32 s8, s8, 0x100000
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v3
+; GFX10-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3
; GFX10-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX10-NEXT: v_mul_hi_u32 v1, s4, v1
; GFX10-NEXT: s_lshl_b32 s8, s8, 16
-; GFX10-NEXT: s_lshr_b32 s11, s2, 16
+; GFX10-NEXT: s_lshr_b32 s10, s2, 16
; GFX10-NEXT: s_or_b32 s5, s5, s8
; GFX10-NEXT: s_lshr_b32 s8, s2, 8
-; GFX10-NEXT: v_mul_hi_u32 v0, s5, v0
+; GFX10-NEXT: v_mul_hi_u32 v1, s5, v1
+; GFX10-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX10-NEXT: s_and_b32 s8, s8, s9
; GFX10-NEXT: s_and_b32 s12, s2, s9
-; GFX10-NEXT: v_mul_lo_u32 v1, v1, 24
-; GFX10-NEXT: s_lshl_b32 s8, s8, s10
-; GFX10-NEXT: s_and_b32 s11, s11, s9
+; GFX10-NEXT: s_lshl_b32 s8, s8, s11
+; GFX10-NEXT: s_and_b32 s10, s10, s9
; GFX10-NEXT: s_or_b32 s8, s12, s8
; GFX10-NEXT: s_lshr_b32 s2, s2, 24
-; GFX10-NEXT: v_mul_lo_u32 v0, v0, 24
+; GFX10-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX10-NEXT: v_sub_nc_u32_e32 v0, s4, v0
+; GFX10-NEXT: s_bfe_u32 s4, s8, 0x100000
+; GFX10-NEXT: s_bfe_u32 s8, s10, 0x100000
; GFX10-NEXT: s_bfe_u32 s6, s6, 0x100000
; GFX10-NEXT: s_bfe_u32 s7, s7, 0x100000
-; GFX10-NEXT: v_sub_nc_u32_e32 v1, s4, v1
-; GFX10-NEXT: s_bfe_u32 s4, s8, 0x100000
-; GFX10-NEXT: s_bfe_u32 s8, s11, 0x100000
-; GFX10-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX10-NEXT: s_lshl_b32 s6, s6, 16
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, s5, v0
-; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
+; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
+; GFX10-NEXT: v_sub_nc_u32_e32 v1, s5, v1
; GFX10-NEXT: s_lshl_b32 s5, s8, 16
; GFX10-NEXT: s_lshr_b32 s8, s3, 8
-; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v0
; GFX10-NEXT: s_and_b32 s3, s3, s9
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
-; GFX10-NEXT: s_lshl_b32 s3, s3, s10
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v1
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
+; GFX10-NEXT: s_lshl_b32 s3, s3, s11
; GFX10-NEXT: s_or_b32 s4, s4, s5
+; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
; GFX10-NEXT: s_or_b32 s2, s2, s3
-; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
; GFX10-NEXT: s_and_b32 s3, s8, s9
; GFX10-NEXT: s_mov_b32 s5, 0xffffff
; GFX10-NEXT: s_bfe_u32 s3, s3, 0x100000
-; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
+; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
; GFX10-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX10-NEXT: s_lshl_b32 s3, s3, 16
-; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX10-NEXT: v_sub_nc_u32_e32 v2, 23, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
+; GFX10-NEXT: s_bfe_u32 s0, s0, 0x100000
+; GFX10-NEXT: v_sub_nc_u32_e32 v2, 23, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v3, 0xffffff
; GFX10-NEXT: s_or_b32 s2, s2, s3
; GFX10-NEXT: s_lshr_b32 s3, s4, 1
; GFX10-NEXT: v_and_b32_e32 v2, s5, v2
-; GFX10-NEXT: v_sub_nc_u32_e32 v4, 23, v0
+; GFX10-NEXT: v_sub_nc_u32_e32 v4, 23, v1
; GFX10-NEXT: s_lshr_b32 s2, s2, 1
-; GFX10-NEXT: v_and_b32_e32 v1, s5, v1
-; GFX10-NEXT: v_and_b32_e32 v0, v0, v3
+; GFX10-NEXT: v_and_b32_e32 v0, s5, v0
+; GFX10-NEXT: v_and_b32_e32 v1, v1, v3
; GFX10-NEXT: v_lshrrev_b32_e64 v2, v2, s3
; GFX10-NEXT: v_and_b32_e32 v4, v4, v3
+; GFX10-NEXT: s_lshl_b32 s6, s6, 16
+; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX10-NEXT: s_lshl_b32 s7, s7, 16
; GFX10-NEXT: s_or_b32 s0, s0, s6
-; GFX10-NEXT: s_or_b32 s1, s1, s7
-; GFX10-NEXT: v_lshl_or_b32 v1, s0, v1, v2
; GFX10-NEXT: v_lshrrev_b32_e64 v3, v4, s2
+; GFX10-NEXT: s_or_b32 s1, s1, s7
+; GFX10-NEXT: v_lshl_or_b32 v0, s0, v0, v2
; GFX10-NEXT: s_mov_b32 s0, 8
-; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-; GFX10-NEXT: v_lshl_or_b32 v0, s1, v0, v3
+; GFX10-NEXT: v_lshl_or_b32 v1, s1, v1, v3
+; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX10-NEXT: s_mov_b32 s0, 16
-; GFX10-NEXT: v_and_or_b32 v2, v1, s9, v2
-; GFX10-NEXT: v_and_b32_e32 v3, s9, v0
-; GFX10-NEXT: v_bfe_u32 v4, v0, 8, 8
-; GFX10-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX10-NEXT: v_and_b32_e32 v3, s9, v1
+; GFX10-NEXT: v_bfe_u32 v4, v1, 8, 8
+; GFX10-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX10-NEXT: v_and_or_b32 v2, v0, s9, v2
+; GFX10-NEXT: v_lshlrev_b32_sdwa v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX10-NEXT: v_lshl_or_b32 v0, v0, 8, v4
-; GFX10-NEXT: v_or3_b32 v1, v2, v1, v3
-; GFX10-NEXT: v_readfirstlane_b32 s1, v0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v1
+; GFX10-NEXT: v_lshl_or_b32 v1, v1, 8, v4
+; GFX10-NEXT: v_or3_b32 v0, v2, v0, v3
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i48 %lhs.arg to <2 x i24>
%rhs = bitcast i48 %rhs.arg to <2 x i24>
@@ -1987,36 +1997,38 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX6-NEXT: v_mov_b32_e32 v8, 0xffffffe8
+; GFX6-NEXT: v_mov_b32_e32 v7, 0xffffffe8
; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX6-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
-; GFX6-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
; GFX6-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GFX6-NEXT: v_mul_lo_u32 v9, v8, v7
-; GFX6-NEXT: v_mul_hi_u32 v9, v7, v9
-; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v9
-; GFX6-NEXT: v_mul_hi_u32 v7, v4, v7
+; GFX6-NEXT: v_mul_lo_u32 v8, v7, v6
+; GFX6-NEXT: v_mul_hi_u32 v8, v6, v8
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v8
+; GFX6-NEXT: v_mul_hi_u32 v6, v4, v6
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v8, v9
; GFX6-NEXT: v_mov_b32_e32 v9, 0xffffff
; GFX6-NEXT: v_and_b32_e32 v2, v2, v9
+; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX6-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; GFX6-NEXT: v_cvt_u32_f32_e32 v8, v8
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX6-NEXT: v_mul_lo_u32 v7, v7, 24
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v7
-; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, 24, v4
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v6
+; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 24, v4
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, 24, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 24, v4
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX6-NEXT: v_mul_lo_u32 v7, v8, v6
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 23, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX6-NEXT: v_mul_lo_u32 v6, v7, v8
+; GFX6-NEXT: v_sub_i32_e32 v7, vcc, 23, v4
; GFX6-NEXT: v_and_b32_e32 v4, v4, v9
; GFX6-NEXT: v_lshlrev_b32_e32 v0, v4, v0
-; GFX6-NEXT: v_mul_hi_u32 v7, v6, v7
+; GFX6-NEXT: v_mul_hi_u32 v6, v8, v6
; GFX6-NEXT: v_and_b32_e32 v4, v5, v9
-; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v7
+; GFX6-NEXT: v_add_i32_e32 v5, vcc, v8, v6
; GFX6-NEXT: v_mul_hi_u32 v5, v4, v5
-; GFX6-NEXT: v_and_b32_e32 v6, v8, v9
+; GFX6-NEXT: v_and_b32_e32 v6, v7, v9
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v6, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_mul_lo_u32 v5, v5, 24
@@ -2042,36 +2054,38 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX8-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX8-NEXT: v_mov_b32_e32 v8, 0xffffffe8
+; GFX8-NEXT: v_mov_b32_e32 v7, 0xffffffe8
; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX8-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
-; GFX8-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
; GFX8-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GFX8-NEXT: v_mul_lo_u32 v9, v8, v7
-; GFX8-NEXT: v_mul_hi_u32 v9, v7, v9
-; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v9
-; GFX8-NEXT: v_mul_hi_u32 v7, v4, v7
+; GFX8-NEXT: v_mul_lo_u32 v8, v7, v6
+; GFX8-NEXT: v_mul_hi_u32 v8, v6, v8
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v8
+; GFX8-NEXT: v_mul_hi_u32 v6, v4, v6
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v8, v9
; GFX8-NEXT: v_mov_b32_e32 v9, 0xffffff
; GFX8-NEXT: v_and_b32_e32 v2, v2, v9
+; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX8-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; GFX8-NEXT: v_cvt_u32_f32_e32 v8, v8
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX8-NEXT: v_mul_lo_u32 v7, v7, 24
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v7
-; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, 24, v4
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v6
+; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 24, v4
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, 24, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 24, v4
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX8-NEXT: v_mul_lo_u32 v7, v8, v6
-; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 23, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX8-NEXT: v_mul_lo_u32 v6, v7, v8
+; GFX8-NEXT: v_sub_u32_e32 v7, vcc, 23, v4
; GFX8-NEXT: v_and_b32_e32 v4, v4, v9
; GFX8-NEXT: v_lshlrev_b32_e32 v0, v4, v0
-; GFX8-NEXT: v_mul_hi_u32 v7, v6, v7
+; GFX8-NEXT: v_mul_hi_u32 v6, v8, v6
; GFX8-NEXT: v_and_b32_e32 v4, v5, v9
-; GFX8-NEXT: v_add_u32_e32 v5, vcc, v6, v7
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, v8, v6
; GFX8-NEXT: v_mul_hi_u32 v5, v4, v5
-; GFX8-NEXT: v_and_b32_e32 v6, v8, v9
+; GFX8-NEXT: v_and_b32_e32 v6, v7, v9
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v6, v2
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: v_mul_lo_u32 v5, v5, 24
@@ -2097,39 +2111,41 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX9-NEXT: v_mov_b32_e32 v8, 0xffffffe8
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX9-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
-; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX9-NEXT: v_mov_b32_e32 v7, 0xffffffe8
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v9, v9
; GFX9-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GFX9-NEXT: v_mul_lo_u32 v9, v8, v7
-; GFX9-NEXT: v_mul_lo_u32 v8, v8, v6
-; GFX9-NEXT: v_mul_hi_u32 v9, v7, v9
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX9-NEXT: v_mul_f32_e32 v9, 0x4f7ffffe, v9
+; GFX9-NEXT: v_mul_lo_u32 v8, v7, v6
; GFX9-NEXT: v_mul_hi_u32 v8, v6, v8
-; GFX9-NEXT: v_add_u32_e32 v7, v7, v9
-; GFX9-NEXT: v_mul_hi_u32 v7, v4, v7
+; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
+; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v9
+; GFX9-NEXT: v_mul_hi_u32 v6, v4, v6
; GFX9-NEXT: v_mov_b32_e32 v9, 0xffffff
; GFX9-NEXT: v_and_b32_e32 v5, v5, v9
-; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
-; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24
-; GFX9-NEXT: v_mul_hi_u32 v6, v5, v6
+; GFX9-NEXT: v_mul_lo_u32 v7, v7, v8
+; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX9-NEXT: v_and_b32_e32 v2, v2, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 1, v2
-; GFX9-NEXT: v_sub_u32_e32 v4, v4, v7
-; GFX9-NEXT: v_subrev_u32_e32 v7, 24, v4
+; GFX9-NEXT: v_mul_hi_u32 v7, v8, v7
+; GFX9-NEXT: v_sub_u32_e32 v4, v4, v6
+; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v7, 24, v4
+; GFX9-NEXT: v_add_u32_e32 v7, v8, v7
+; GFX9-NEXT: v_mul_hi_u32 v7, v5, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
-; GFX9-NEXT: v_sub_u32_e32 v7, 23, v4
-; GFX9-NEXT: v_and_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24
+; GFX9-NEXT: v_sub_u32_e32 v6, 23, v4
+; GFX9-NEXT: v_and_b32_e32 v6, v6, v9
; GFX9-NEXT: v_and_b32_e32 v4, v4, v9
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, v7, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, v6, v2
; GFX9-NEXT: v_lshl_or_b32 v0, v0, v4, v2
-; GFX9-NEXT: v_sub_u32_e32 v2, v5, v6
+; GFX9-NEXT: v_sub_u32_e32 v2, v5, v7
; GFX9-NEXT: v_subrev_u32_e32 v4, 24, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
@@ -2150,30 +2166,32 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v7, 24
; GFX10-NEXT: v_mov_b32_e32 v10, 0xffffff
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX10-NEXT: v_rcp_iflag_f32_e32 v6, v6
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v7, v7
; GFX10-NEXT: v_and_b32_e32 v5, v5, v10
; GFX10-NEXT: v_and_b32_e32 v2, v2, v10
; GFX10-NEXT: v_and_b32_e32 v3, v3, v10
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 1, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 1, v3
-; GFX10-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
; GFX10-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
-; GFX10-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX10-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GFX10-NEXT: v_mul_lo_u32 v8, 0xffffffe8, v7
-; GFX10-NEXT: v_mul_lo_u32 v9, 0xffffffe8, v6
-; GFX10-NEXT: v_mul_hi_u32 v8, v7, v8
-; GFX10-NEXT: v_mul_hi_u32 v9, v6, v9
-; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v8
-; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v9
-; GFX10-NEXT: v_mul_hi_u32 v7, v4, v7
-; GFX10-NEXT: v_mul_hi_u32 v6, v5, v6
-; GFX10-NEXT: v_mul_lo_u32 v7, v7, 24
+; GFX10-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX10-NEXT: v_mul_lo_u32 v8, 0xffffffe8, v6
+; GFX10-NEXT: v_mul_lo_u32 v9, 0xffffffe8, v7
+; GFX10-NEXT: v_mul_hi_u32 v8, v6, v8
+; GFX10-NEXT: v_mul_hi_u32 v9, v7, v9
+; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v8
+; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v9
+; GFX10-NEXT: v_mul_hi_u32 v6, v4, v6
+; GFX10-NEXT: v_mul_hi_u32 v7, v5, v7
; GFX10-NEXT: v_mul_lo_u32 v6, v6, 24
-; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v7
-; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v6
+; GFX10-NEXT: v_mul_lo_u32 v7, v7, 24
+; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v6
+; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v7
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 24, v4
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, 24, v5
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
index 5a378873ba8dd..8ba814a5df078 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
@@ -1465,7 +1465,8 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_movk_i32 s9, 0xff
; GFX6-NEXT: s_mov_b32 s11, 0x80008
; GFX6-NEXT: s_lshr_b32 s6, s0, 16
-; GFX6-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
+; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX6-NEXT: s_lshr_b32 s8, s1, 8
; GFX6-NEXT: s_and_b32 s1, s1, s9
; GFX6-NEXT: s_lshr_b32 s7, s0, 24
@@ -1473,11 +1474,12 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_bfe_u32 s0, s0, s11
; GFX6-NEXT: s_lshl_b32 s0, s0, 8
; GFX6-NEXT: s_lshl_b32 s1, s1, 8
-; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX6-NEXT: s_or_b32 s0, s10, s0
; GFX6-NEXT: s_or_b32 s1, s7, s1
; GFX6-NEXT: s_and_b32 s7, s8, s9
; GFX6-NEXT: s_lshr_b32 s8, s2, 16
+; GFX6-NEXT: v_mul_lo_u32 v2, v1, v0
; GFX6-NEXT: s_lshr_b32 s10, s2, 24
; GFX6-NEXT: s_and_b32 s13, s2, s9
; GFX6-NEXT: s_bfe_u32 s2, s2, s11
@@ -1485,20 +1487,18 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_and_b32 s8, s8, s9
; GFX6-NEXT: s_or_b32 s2, s13, s2
; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000
-; GFX6-NEXT: v_mov_b32_e32 v2, 0xffffffe8
-; GFX6-NEXT: v_mul_lo_u32 v3, v2, v1
; GFX6-NEXT: s_lshr_b32 s12, s3, 8
; GFX6-NEXT: s_and_b32 s3, s3, s9
; GFX6-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX6-NEXT: s_lshl_b32 s8, s8, 16
; GFX6-NEXT: s_lshl_b32 s3, s3, 8
+; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX6-NEXT: s_or_b32 s2, s2, s8
; GFX6-NEXT: s_and_b32 s8, s12, s9
; GFX6-NEXT: s_or_b32 s3, s10, s3
; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000
; GFX6-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX6-NEXT: s_lshl_b32 s8, s8, 16
-; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX6-NEXT: s_or_b32 s3, s3, s8
; GFX6-NEXT: s_lshr_b32 s8, s4, 16
; GFX6-NEXT: s_lshr_b32 s10, s4, 24
@@ -1506,101 +1506,105 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX6-NEXT: s_bfe_u32 s4, s4, s11
; GFX6-NEXT: s_lshl_b32 s4, s4, 8
; GFX6-NEXT: s_and_b32 s8, s8, s9
+; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, 24
; GFX6-NEXT: s_or_b32 s4, s13, s4
; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX6-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX6-NEXT: s_lshl_b32 s8, s8, 16
; GFX6-NEXT: s_or_b32 s4, s4, s8
-; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT: v_mul_hi_u32 v1, s4, v1
-; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
+; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX6-NEXT: s_lshr_b32 s12, s5, 8
-; GFX6-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX6-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX6-NEXT: s_and_b32 s5, s5, s9
-; GFX6-NEXT: v_mul_lo_u32 v2, v2, v0
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, v2
; GFX6-NEXT: s_lshl_b32 s5, s5, 8
-; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s4, v1
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v1
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
+; GFX6-NEXT: v_mul_hi_u32 v1, v2, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-NEXT: s_and_b32 s8, s12, s9
; GFX6-NEXT: s_or_b32 s5, s10, s5
; GFX6-NEXT: s_bfe_u32 s8, s8, 0x100000
-; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v1
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 24, v0
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX6-NEXT: s_bfe_u32 s5, s5, 0x100000
; GFX6-NEXT: s_lshl_b32 s8, s8, 16
-; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX6-NEXT: s_or_b32 s5, s5, s8
-; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT: v_mul_hi_u32 v0, s5, v0
+; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1
+; GFX6-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX6-NEXT: s_and_b32 s6, s6, s9
; GFX6-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX6-NEXT: s_bfe_u32 s6, s6, 0x100000
-; GFX6-NEXT: v_mul_lo_u32 v0, v0, 24
+; GFX6-NEXT: v_mul_lo_u32 v1, v1, 24
; GFX6-NEXT: s_mov_b32 s8, 0xffffff
-; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v1
+; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 23, v0
; GFX6-NEXT: s_lshl_b32 s4, s6, 17
; GFX6-NEXT: s_lshl_b32 s0, s0, 1
-; GFX6-NEXT: v_and_b32_e32 v1, s8, v1
+; GFX6-NEXT: v_and_b32_e32 v0, s8, v0
; GFX6-NEXT: s_or_b32 s0, s4, s0
; GFX6-NEXT: v_and_b32_e32 v2, s8, v3
; GFX6-NEXT: v_lshl_b32_e32 v2, s0, v2
-; GFX6-NEXT: v_lshr_b32_e32 v1, s2, v1
-; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
-; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0
-; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT: v_lshr_b32_e32 v0, s2, v0
+; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1
+; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 24, v1
+; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX6-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX6-NEXT: s_bfe_u32 s7, s7, 0x100000
; GFX6-NEXT: v_mov_b32_e32 v4, 0xffffff
-; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 23, v0
+; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 23, v1
; GFX6-NEXT: s_lshl_b32 s0, s7, 17
; GFX6-NEXT: s_lshl_b32 s1, s1, 1
-; GFX6-NEXT: v_and_b32_e32 v0, v0, v4
+; GFX6-NEXT: v_and_b32_e32 v1, v1, v4
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: v_and_b32_e32 v2, v2, v4
-; GFX6-NEXT: v_bfe_u32 v3, v1, 8, 8
+; GFX6-NEXT: v_bfe_u32 v3, v0, 8, 8
; GFX6-NEXT: v_lshl_b32_e32 v2, s0, v2
-; GFX6-NEXT: v_lshr_b32_e32 v0, s3, v0
-; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_and_b32_e32 v2, s9, v1
-; GFX6-NEXT: v_bfe_u32 v1, v1, 16, 8
-; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT: v_lshr_b32_e32 v1, s3, v1
; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
; GFX6-NEXT: v_and_b32_e32 v2, s9, v0
-; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v2
-; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX6-NEXT: v_bfe_u32 v2, v0, 8, 8
; GFX6-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX6-NEXT: v_readfirstlane_b32 s0, v1
-; GFX6-NEXT: v_readfirstlane_b32 s1, v0
+; GFX6-NEXT: v_and_b32_e32 v2, s9, v1
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX6-NEXT: v_bfe_u32 v2, v1, 8, 8
+; GFX6-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX6-NEXT: v_readfirstlane_b32 s0, v0
+; GFX6-NEXT: v_readfirstlane_b32 s1, v1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_fshr_v2i24:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_movk_i32 s10, 0xff
; GFX8-NEXT: s_lshr_b32 s9, s1, 8
-; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
; GFX8-NEXT: s_bfe_u32 s11, 8, 0x100000
; GFX8-NEXT: s_and_b32 s1, s1, s10
; GFX8-NEXT: s_lshr_b32 s6, s0, 8
+; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
; GFX8-NEXT: s_lshr_b32 s8, s0, 24
; GFX8-NEXT: s_lshl_b32 s1, s1, s11
; GFX8-NEXT: s_or_b32 s1, s8, s1
; GFX8-NEXT: s_and_b32 s6, s6, s10
; GFX8-NEXT: s_lshr_b32 s8, s2, 8
+; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX8-NEXT: s_and_b32 s8, s8, s10
; GFX8-NEXT: s_lshr_b32 s7, s0, 16
; GFX8-NEXT: s_and_b32 s0, s0, s10
@@ -1608,15 +1612,15 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_or_b32 s0, s0, s6
; GFX8-NEXT: s_and_b32 s6, s7, s10
; GFX8-NEXT: s_and_b32 s7, s9, s10
-; GFX8-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX8-NEXT: s_lshr_b32 s9, s2, 16
; GFX8-NEXT: s_lshr_b32 s12, s2, 24
; GFX8-NEXT: s_and_b32 s2, s2, s10
; GFX8-NEXT: s_lshl_b32 s8, s8, s11
; GFX8-NEXT: s_or_b32 s2, s2, s8
; GFX8-NEXT: s_and_b32 s8, s9, s10
-; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX8-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX8-NEXT: s_bfe_u32 s8, s8, 0x100000
+; GFX8-NEXT: v_mul_lo_u32 v2, v1, v0
; GFX8-NEXT: s_lshr_b32 s13, s3, 8
; GFX8-NEXT: s_and_b32 s3, s3, s10
; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
@@ -1624,110 +1628,115 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX8-NEXT: s_lshl_b32 s3, s3, s11
; GFX8-NEXT: s_or_b32 s2, s2, s8
; GFX8-NEXT: s_and_b32 s8, s13, s10
-; GFX8-NEXT: v_mov_b32_e32 v2, 0xffffffe8
; GFX8-NEXT: s_or_b32 s3, s12, s3
; GFX8-NEXT: s_bfe_u32 s8, s8, 0x100000
-; GFX8-NEXT: v_mul_lo_u32 v3, v2, v1
+; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX8-NEXT: s_lshl_b32 s8, s8, 16
; GFX8-NEXT: s_or_b32 s3, s3, s8
; GFX8-NEXT: s_lshr_b32 s8, s4, 8
; GFX8-NEXT: s_and_b32 s8, s8, s10
-; GFX8-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX8-NEXT: s_lshr_b32 s9, s4, 16
; GFX8-NEXT: s_lshr_b32 s12, s4, 24
; GFX8-NEXT: s_and_b32 s4, s4, s10
; GFX8-NEXT: s_lshl_b32 s8, s8, s11
; GFX8-NEXT: s_or_b32 s4, s4, s8
; GFX8-NEXT: s_and_b32 s8, s9, s10
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v2, 24
; GFX8-NEXT: s_bfe_u32 s8, s8, 0x100000
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX8-NEXT: s_lshl_b32 s8, s8, 16
; GFX8-NEXT: s_or_b32 s4, s4, s8
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
-; GFX8-NEXT: v_mul_hi_u32 v1, s4, v1
-; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
-; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX8-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
+; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX8-NEXT: s_lshr_b32 s13, s5, 8
-; GFX8-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX8-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX8-NEXT: s_and_b32 s5, s5, s10
-; GFX8-NEXT: v_mul_lo_u32 v2, v2, v0
+; GFX8-NEXT: v_mul_lo_u32 v1, v1, v2
; GFX8-NEXT: s_lshl_b32 s5, s5, s11
-; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s4, v1
-; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v1
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0
+; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v0
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
+; GFX8-NEXT: v_mul_hi_u32 v1, v2, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: s_and_b32 s8, s13, s10
; GFX8-NEXT: s_or_b32 s5, s12, s5
; GFX8-NEXT: s_bfe_u32 s8, s8, 0x100000
-; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v1
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 24, v0
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX8-NEXT: s_bfe_u32 s5, s5, 0x100000
; GFX8-NEXT: s_lshl_b32 s8, s8, 16
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT: s_or_b32 s5, s5, s8
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
-; GFX8-NEXT: v_mul_hi_u32 v0, s5, v0
+; GFX8-NEXT: v_add_u32_e32 v1, vcc, v2, v1
+; GFX8-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX8-NEXT: s_bfe_u32 s6, s6, 0x100000
; GFX8-NEXT: s_mov_b32 s8, 0xffffff
-; GFX8-NEXT: v_mul_lo_u32 v0, v0, 24
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v1
+; GFX8-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v0
; GFX8-NEXT: s_lshl_b32 s4, s6, 17
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
-; GFX8-NEXT: v_and_b32_e32 v1, s8, v1
+; GFX8-NEXT: v_and_b32_e32 v0, s8, v0
; GFX8-NEXT: s_or_b32 s0, s4, s0
; GFX8-NEXT: v_and_b32_e32 v2, s8, v3
; GFX8-NEXT: v_lshlrev_b32_e64 v2, v2, s0
-; GFX8-NEXT: v_lshrrev_b32_e64 v1, v1, s2
-; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s5, v0
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v0
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v0
-; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s2
+; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s5, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 24, v1
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_bfe_u32 s7, s7, 0x100000
; GFX8-NEXT: v_mov_b32_e32 v4, 0xffffff
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 23, v0
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 23, v1
; GFX8-NEXT: s_lshl_b32 s0, s7, 17
; GFX8-NEXT: s_lshl_b32 s1, s1, 1
-; GFX8-NEXT: v_and_b32_e32 v0, v0, v4
+; GFX8-NEXT: v_and_b32_e32 v1, v1, v4
; GFX8-NEXT: v_and_b32_e32 v2, v2, v4
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: v_lshlrev_b32_e64 v2, v2, s0
-; GFX8-NEXT: v_lshrrev_b32_e64 v0, v0, s3
-; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-NEXT: v_lshrrev_b32_e64 v1, v1, s3
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: v_mov_b32_e32 v2, 8
-; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX8-NEXT: v_lshlrev_b32_sdwa v3, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX8-NEXT: v_mov_b32_e32 v4, 16
-; GFX8-NEXT: v_or_b32_sdwa v3, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-; GFX8-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX8-NEXT: v_and_b32_e32 v3, s10, v0
-; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX8-NEXT: v_or_b32_sdwa v3, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX8-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX8-NEXT: v_and_b32_e32 v3, s10, v1
+; GFX8-NEXT: v_lshlrev_b32_sdwa v2, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX8-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX8-NEXT: v_readfirstlane_b32 s0, v1
-; GFX8-NEXT: v_readfirstlane_b32 s1, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
+; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_readfirstlane_b32 s0, v0
+; GFX8-NEXT: v_readfirstlane_b32 s1, v1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_fshr_v2i24:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xffffffe8
; GFX9-NEXT: s_movk_i32 s12, 0xff
; GFX9-NEXT: s_lshr_b32 s11, s1, 8
-; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
+; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX9-NEXT: s_bfe_u32 s13, 8, 0x100000
; GFX9-NEXT: s_and_b32 s1, s1, s12
; GFX9-NEXT: s_lshr_b32 s7, s0, 8
+; GFX9-NEXT: v_mul_lo_u32 v2, v1, v0
; GFX9-NEXT: s_lshr_b32 s10, s0, 24
; GFX9-NEXT: s_lshl_b32 s1, s1, s13
; GFX9-NEXT: s_or_b32 s1, s10, s1
+; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX9-NEXT: s_and_b32 s7, s7, s12
; GFX9-NEXT: s_lshr_b32 s10, s2, 8
; GFX9-NEXT: s_and_b32 s10, s10, s12
@@ -1737,15 +1746,16 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_or_b32 s0, s0, s7
; GFX9-NEXT: s_and_b32 s7, s9, s12
; GFX9-NEXT: s_and_b32 s9, s11, s12
-; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX9-NEXT: s_lshr_b32 s11, s2, 16
; GFX9-NEXT: s_lshr_b32 s14, s2, 24
; GFX9-NEXT: s_and_b32 s2, s2, s12
; GFX9-NEXT: s_lshl_b32 s10, s10, s13
; GFX9-NEXT: s_or_b32 s2, s2, s10
; GFX9-NEXT: s_and_b32 s10, s11, s12
-; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v2, 24
; GFX9-NEXT: s_bfe_u32 s10, s10, 0x100000
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v2
; GFX9-NEXT: s_lshr_b32 s15, s3, 8
; GFX9-NEXT: s_and_b32 s3, s3, s12
; GFX9-NEXT: s_bfe_u32 s2, s2, 0x100000
@@ -1753,18 +1763,15 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_lshl_b32 s3, s3, s13
; GFX9-NEXT: s_or_b32 s2, s2, s10
; GFX9-NEXT: s_and_b32 s10, s15, s12
-; GFX9-NEXT: v_mov_b32_e32 v2, 0xffffffe8
; GFX9-NEXT: s_or_b32 s3, s14, s3
; GFX9-NEXT: s_bfe_u32 s10, s10, 0x100000
-; GFX9-NEXT: v_mul_lo_u32 v3, v2, v1
-; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX9-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
; GFX9-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX9-NEXT: s_lshl_b32 s10, s10, 16
; GFX9-NEXT: s_or_b32 s3, s3, s10
; GFX9-NEXT: s_lshr_b32 s10, s4, 8
-; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2
; GFX9-NEXT: s_and_b32 s10, s10, s12
-; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3
; GFX9-NEXT: s_lshr_b32 s11, s4, 16
; GFX9-NEXT: s_lshr_b32 s14, s4, 24
; GFX9-NEXT: s_and_b32 s4, s4, s12
@@ -1772,201 +1779,202 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
; GFX9-NEXT: s_or_b32 s4, s4, s10
; GFX9-NEXT: s_and_b32 s10, s11, s12
; GFX9-NEXT: s_bfe_u32 s10, s10, 0x100000
-; GFX9-NEXT: v_mul_lo_u32 v2, v2, v0
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, v2
; GFX9-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX9-NEXT: s_lshl_b32 s10, s10, 16
; GFX9-NEXT: s_or_b32 s4, s4, s10
-; GFX9-NEXT: v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT: v_mul_hi_u32 v1, s4, v1
+; GFX9-NEXT: v_mul_hi_u32 v0, s4, v0
; GFX9-NEXT: s_lshr_b32 s15, s5, 8
; GFX9-NEXT: s_and_b32 s5, s5, s12
-; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2
+; GFX9-NEXT: v_mul_hi_u32 v1, v2, v1
; GFX9-NEXT: s_lshl_b32 s5, s5, s13
; GFX9-NEXT: s_and_b32 s10, s15, s12
; GFX9-NEXT: s_or_b32 s5, s14, s5
; GFX9-NEXT: s_bfe_u32 s10, s10, 0x100000
-; GFX9-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX9-NEXT: v_mul_lo_u32 v0, v0, 24
; GFX9-NEXT: s_bfe_u32 s5, s5, 0x100000
; GFX9-NEXT: s_lshl_b32 s10, s10, 16
; GFX9-NEXT: s_or_b32 s5, s5, s10
-; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
-; GFX9-NEXT: v_mul_hi_u32 v0, s5, v0
-; GFX9-NEXT: v_sub_u32_e32 v1, s4, v1
-; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX9-NEXT: v_mul_lo_u32 v0, v0, 24
-; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
+; GFX9-NEXT: v_mul_hi_u32 v1, s5, v1
+; GFX9-NEXT: v_sub_u32_e32 v0, s4, v0
+; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v0
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
; GFX9-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT: s_bfe_u32 s7, s7, 0x100000
; GFX9-NEXT: s_mov_b32 s10, 0xffffff
-; GFX9-NEXT: v_sub_u32_e32 v3, 23, v1
-; GFX9-NEXT: v_and_b32_e32 v1, s10, v1
+; GFX9-NEXT: v_sub_u32_e32 v3, 23, v0
+; GFX9-NEXT: v_and_b32_e32 v0, s10, v0
; GFX9-NEXT: s_lshl_b32 s4, s7, 17
; GFX9-NEXT: s_lshl_b32 s0, s0, 1
-; GFX9-NEXT: v_sub_u32_e32 v0, s5, v0
+; GFX9-NEXT: v_sub_u32_e32 v1, s5, v1
; GFX9-NEXT: s_or_b32 s0, s4, s0
; GFX9-NEXT: v_and_b32_e32 v3, s10, v3
-; GFX9-NEXT: v_lshrrev_b32_e64 v1, v1, s2
-; GFX9-NEXT: v_lshl_or_b32 v1, s0, v3, v1
-; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v0
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v0
-; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v0
+; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s2
+; GFX9-NEXT: v_lshl_or_b32 v0, s0, v3, v0
+; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v3, 24, v1
+; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v1
; GFX9-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: s_bfe_u32 s9, s9, 0x100000
; GFX9-NEXT: v_mov_b32_e32 v2, 0xffffff
-; GFX9-NEXT: v_sub_u32_e32 v3, 23, v0
-; GFX9-NEXT: v_and_b32_e32 v0, v0, v2
+; GFX9-NEXT: v_sub_u32_e32 v3, 23, v1
+; GFX9-NEXT: v_and_b32_e32 v1, v1, v2
; GFX9-NEXT: s_lshl_b32 s0, s9, 17
; GFX9-NEXT: s_lshl_b32 s1, s1, 1
; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: v_and_b32_e32 v3, v3, v2
-; GFX9-NEXT: v_lshrrev_b32_e64 v0, v0, s3
-; GFX9-NEXT: v_lshl_or_b32 v0, s0, v3, v0
+; GFX9-NEXT: v_lshrrev_b32_e64 v1, v1, s3
+; GFX9-NEXT: v_lshl_or_b32 v1, s0, v3, v1
; GFX9-NEXT: s_mov_b32 s6, 8
-; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-; GFX9-NEXT: v_and_b32_e32 v3, s12, v0
+; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX9-NEXT: v_and_b32_e32 v3, s12, v1
; GFX9-NEXT: s_mov_b32 s8, 16
-; GFX9-NEXT: v_and_or_b32 v2, v1, s12, v2
-; GFX9-NEXT: v_lshlrev_b32_sdwa v1, s8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX9-NEXT: v_and_or_b32 v2, v0, s12, v2
+; GFX9-NEXT: v_lshlrev_b32_sdwa v0, s8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX9-NEXT: v_or3_b32 v1, v2, v1, v3
-; GFX9-NEXT: v_bfe_u32 v2, v0, 8, 8
-; GFX9-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, 8, v2
-; GFX9-NEXT: v_readfirstlane_b32 s0, v1
-; GFX9-NEXT: v_readfirstlane_b32 s1, v0
+; GFX9-NEXT: v_or3_b32 v0, v2, v0, v3
+; GFX9-NEXT: v_bfe_u32 v2, v1, 8, 8
+; GFX9-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 8, v2
+; GFX9-NEXT: v_readfirstlane_b32 s0, v0
+; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_fshr_v2i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
-; GFX10-NEXT: s_movk_i32 s8, 0xff
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, 24
+; GFX10-NEXT: s_movk_i32 s9, 0xff
; GFX10-NEXT: s_lshr_b32 s12, s4, 8
; GFX10-NEXT: s_lshr_b32 s13, s4, 16
-; GFX10-NEXT: s_bfe_u32 s10, 8, 0x100000
; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0
-; GFX10-NEXT: s_and_b32 s12, s12, s8
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1
+; GFX10-NEXT: s_bfe_u32 s10, 8, 0x100000
+; GFX10-NEXT: s_and_b32 s12, s12, s9
; GFX10-NEXT: s_lshr_b32 s14, s4, 24
-; GFX10-NEXT: s_and_b32 s4, s4, s8
+; GFX10-NEXT: s_and_b32 s4, s4, s9
; GFX10-NEXT: s_lshl_b32 s12, s12, s10
-; GFX10-NEXT: s_and_b32 s13, s13, s8
+; GFX10-NEXT: s_and_b32 s13, s13, s9
; GFX10-NEXT: s_or_b32 s4, s4, s12
; GFX10-NEXT: s_bfe_u32 s12, s13, 0x100000
-; GFX10-NEXT: s_lshr_b32 s15, s5, 8
-; GFX10-NEXT: s_and_b32 s5, s5, s8
-; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v0
; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
+; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
+; GFX10-NEXT: s_lshr_b32 s15, s5, 8
+; GFX10-NEXT: s_and_b32 s5, s5, s9
; GFX10-NEXT: s_bfe_u32 s4, s4, 0x100000
+; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
+; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX10-NEXT: s_lshl_b32 s12, s12, 16
; GFX10-NEXT: s_lshl_b32 s5, s5, s10
-; GFX10-NEXT: v_cvt_u32_f32_e32 v1, v1
-; GFX10-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX10-NEXT: s_or_b32 s4, s4, s12
-; GFX10-NEXT: s_and_b32 s12, s15, s8
+; GFX10-NEXT: v_mul_lo_u32 v2, 0xffffffe8, v0
+; GFX10-NEXT: v_mul_lo_u32 v3, 0xffffffe8, v1
+; GFX10-NEXT: s_and_b32 s12, s15, s9
; GFX10-NEXT: s_or_b32 s5, s14, s5
-; GFX10-NEXT: v_mul_lo_u32 v2, 0xffffffe8, v1
-; GFX10-NEXT: v_mul_lo_u32 v3, 0xffffffe8, v0
; GFX10-NEXT: s_bfe_u32 s12, s12, 0x100000
; GFX10-NEXT: s_bfe_u32 s5, s5, 0x100000
; GFX10-NEXT: s_lshl_b32 s12, s12, 16
; GFX10-NEXT: s_lshr_b32 s11, s1, 8
+; GFX10-NEXT: v_mul_hi_u32 v2, v0, v2
; GFX10-NEXT: s_or_b32 s5, s5, s12
-; GFX10-NEXT: s_and_b32 s1, s1, s8
-; GFX10-NEXT: v_mul_hi_u32 v2, v1, v2
+; GFX10-NEXT: s_and_b32 s1, s1, s9
; GFX10-NEXT: s_lshr_b32 s6, s0, 8
-; GFX10-NEXT: s_lshr_b32 s9, s0, 24
+; GFX10-NEXT: s_lshr_b32 s8, s0, 24
; GFX10-NEXT: s_lshl_b32 s1, s1, s10
-; GFX10-NEXT: s_and_b32 s6, s6, s8
-; GFX10-NEXT: s_or_b32 s1, s9, s1
-; GFX10-NEXT: s_lshr_b32 s9, s2, 8
+; GFX10-NEXT: s_and_b32 s6, s6, s9
+; GFX10-NEXT: s_or_b32 s1, s8, s1
+; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
+; GFX10-NEXT: v_mul_hi_u32 v2, v1, v3
+; GFX10-NEXT: s_lshr_b32 s8, s2, 8
; GFX10-NEXT: s_lshr_b32 s7, s0, 16
-; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
-; GFX10-NEXT: v_mul_hi_u32 v2, v0, v3
-; GFX10-NEXT: s_and_b32 s9, s9, s8
-; GFX10-NEXT: s_and_b32 s0, s0, s8
+; GFX10-NEXT: s_and_b32 s8, s8, s9
+; GFX10-NEXT: v_mul_hi_u32 v0, s4, v0
+; GFX10-NEXT: s_and_b32 s0, s0, s9
; GFX10-NEXT: s_lshl_b32 s6, s6, s10
-; GFX10-NEXT: v_mul_hi_u32 v1, s4, v1
+; GFX10-NEXT: s_lshr_b32 s13, s2, 24
+; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v2
; GFX10-NEXT: s_or_b32 s0, s0, s6
-; GFX10-NEXT: s_and_b32 s6, s7, s8
-; GFX10-NEXT: s_and_b32 s7, s11, s8
-; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2
+; GFX10-NEXT: s_and_b32 s6, s7, s9
+; GFX10-NEXT: s_and_b32 s7, s11, s9
+; GFX10-NEXT: v_mul_lo_u32 v0, v0, 24
+; GFX10-NEXT: v_mul_hi_u32 v1, s5, v1
; GFX10-NEXT: s_lshr_b32 s11, s2, 16
-; GFX10-NEXT: s_lshr_b32 s13, s2, 24
-; GFX10-NEXT: s_and_b32 s2, s2, s8
-; GFX10-NEXT: v_mul_lo_u32 v1, v1, 24
-; GFX10-NEXT: v_mul_hi_u32 v0, s5, v0
-; GFX10-NEXT: s_lshl_b32 s9, s9, s10
+; GFX10-NEXT: s_and_b32 s2, s2, s9
+; GFX10-NEXT: s_lshl_b32 s8, s8, s10
; GFX10-NEXT: s_lshr_b32 s12, s3, 8
-; GFX10-NEXT: s_or_b32 s2, s2, s9
-; GFX10-NEXT: s_and_b32 s9, s11, s8
+; GFX10-NEXT: s_or_b32 s2, s2, s8
+; GFX10-NEXT: s_and_b32 s8, s11, s9
+; GFX10-NEXT: v_sub_nc_u32_e32 v0, s4, v0
+; GFX10-NEXT: v_mul_lo_u32 v1, v1, 24
+; GFX10-NEXT: s_bfe_u32 s4, s8, 0x100000
; GFX10-NEXT: s_bfe_u32 s2, s2, 0x100000
-; GFX10-NEXT: s_and_b32 s3, s3, s8
-; GFX10-NEXT: v_sub_nc_u32_e32 v1, s4, v1
-; GFX10-NEXT: v_mul_lo_u32 v0, v0, 24
-; GFX10-NEXT: s_bfe_u32 s4, s9, 0x100000
-; GFX10-NEXT: s_lshl_b32 s3, s3, s10
; GFX10-NEXT: s_lshl_b32 s4, s4, 16
-; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
+; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
+; GFX10-NEXT: s_and_b32 s3, s3, s9
; GFX10-NEXT: s_or_b32 s2, s2, s4
+; GFX10-NEXT: v_sub_nc_u32_e32 v1, s5, v1
; GFX10-NEXT: s_mov_b32 s4, 0xffffff
-; GFX10-NEXT: v_sub_nc_u32_e32 v0, s5, v0
-; GFX10-NEXT: s_and_b32 s5, s12, s8
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX10-NEXT: s_lshl_b32 s3, s3, s10
+; GFX10-NEXT: s_and_b32 s5, s12, s9
+; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
+; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v0
; GFX10-NEXT: s_or_b32 s3, s13, s3
; GFX10-NEXT: s_bfe_u32 s5, s5, 0x100000
-; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
-; GFX10-NEXT: v_subrev_nc_u32_e32 v3, 24, v1
; GFX10-NEXT: s_bfe_u32 s3, s3, 0x100000
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
; GFX10-NEXT: s_lshl_b32 s5, s5, 16
; GFX10-NEXT: s_bfe_u32 s0, s0, 0x100000
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
; GFX10-NEXT: s_bfe_u32 s6, s6, 0x100000
+; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
+; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v1
; GFX10-NEXT: s_or_b32 s3, s3, s5
; GFX10-NEXT: s_bfe_u32 s1, s1, 0x100000
-; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 24, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
-; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v0
; GFX10-NEXT: s_bfe_u32 s7, s7, 0x100000
-; GFX10-NEXT: s_lshl_b32 s5, s6, 17
-; GFX10-NEXT: s_lshl_b32 s0, s0, 1
-; GFX10-NEXT: v_sub_nc_u32_e32 v3, 23, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
+; GFX10-NEXT: v_sub_nc_u32_e32 v3, 23, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v2, 0xffffff
-; GFX10-NEXT: v_and_b32_e32 v1, s4, v1
-; GFX10-NEXT: s_or_b32 s0, s5, s0
+; GFX10-NEXT: v_and_b32_e32 v0, s4, v0
+; GFX10-NEXT: s_lshl_b32 s5, s6, 17
; GFX10-NEXT: v_and_b32_e32 v3, s4, v3
-; GFX10-NEXT: v_sub_nc_u32_e32 v4, 23, v0
-; GFX10-NEXT: v_and_b32_e32 v0, v0, v2
-; GFX10-NEXT: v_lshrrev_b32_e64 v1, v1, s2
+; GFX10-NEXT: v_sub_nc_u32_e32 v4, 23, v1
+; GFX10-NEXT: v_and_b32_e32 v1, v1, v2
+; GFX10-NEXT: v_lshrrev_b32_e64 v0, v0, s2
+; GFX10-NEXT: s_lshl_b32 s0, s0, 1
; GFX10-NEXT: s_lshl_b32 s2, s7, 17
-; GFX10-NEXT: s_lshl_b32 s1, s1, 1
; GFX10-NEXT: v_and_b32_e32 v2, v4, v2
-; GFX10-NEXT: v_lshrrev_b32_e64 v0, v0, s3
-; GFX10-NEXT: v_lshl_or_b32 v1, s0, v3, v1
+; GFX10-NEXT: v_lshrrev_b32_e64 v1, v1, s3
+; GFX10-NEXT: s_or_b32 s0, s5, s0
+; GFX10-NEXT: s_lshl_b32 s1, s1, 1
+; GFX10-NEXT: v_lshl_or_b32 v0, s0, v3, v0
; GFX10-NEXT: s_or_b32 s0, s2, s1
-; GFX10-NEXT: v_lshl_or_b32 v0, s0, v2, v0
+; GFX10-NEXT: v_lshl_or_b32 v1, s0, v2, v1
; GFX10-NEXT: s_mov_b32 s0, 8
-; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX10-NEXT: s_mov_b32 s0, 16
-; GFX10-NEXT: v_and_b32_e32 v3, s8, v0
-; GFX10-NEXT: v_bfe_u32 v4, v0, 8, 8
-; GFX10-NEXT: v_bfe_u32 v0, v0, 16, 8
-; GFX10-NEXT: v_and_or_b32 v2, v1, s8, v2
-; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+; GFX10-NEXT: v_and_b32_e32 v3, s9, v1
+; GFX10-NEXT: v_bfe_u32 v4, v1, 8, 8
+; GFX10-NEXT: v_bfe_u32 v1, v1, 16, 8
+; GFX10-NEXT: v_and_or_b32 v2, v0, s9, v2
+; GFX10-NEXT: v_lshlrev_b32_sdwa v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 24, v3
-; GFX10-NEXT: v_lshl_or_b32 v0, v0, 8, v4
-; GFX10-NEXT: v_or3_b32 v1, v2, v1, v3
-; GFX10-NEXT: v_readfirstlane_b32 s1, v0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v1
+; GFX10-NEXT: v_lshl_or_b32 v1, v1, 8, v4
+; GFX10-NEXT: v_or3_b32 v0, v2, v0, v3
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i48 %lhs.arg to <2 x i24>
%rhs = bitcast i48 %rhs.arg to <2 x i24>
@@ -1982,40 +1990,42 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX6-NEXT: v_mov_b32_e32 v8, 0xffffffe8
+; GFX6-NEXT: v_mov_b32_e32 v7, 0xffffffe8
; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
-; GFX6-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
-; GFX6-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
; GFX6-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 1, v1
-; GFX6-NEXT: v_mul_lo_u32 v9, v8, v7
-; GFX6-NEXT: v_mul_hi_u32 v9, v7, v9
-; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v9
-; GFX6-NEXT: v_mul_hi_u32 v7, v4, v7
+; GFX6-NEXT: v_mul_lo_u32 v8, v7, v6
+; GFX6-NEXT: v_mul_hi_u32 v8, v6, v8
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v8
+; GFX6-NEXT: v_mul_hi_u32 v6, v4, v6
+; GFX6-NEXT: v_rcp_iflag_f32_e32 v8, v9
; GFX6-NEXT: v_mov_b32_e32 v9, 0xffffff
; GFX6-NEXT: v_and_b32_e32 v5, v5, v9
+; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX6-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; GFX6-NEXT: v_cvt_u32_f32_e32 v8, v8
; GFX6-NEXT: v_and_b32_e32 v2, v2, v9
-; GFX6-NEXT: v_mul_lo_u32 v7, v7, 24
-; GFX6-NEXT: v_and_b32_e32 v3, v3, v9
-; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v7
-; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, 24, v4
+; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v6
+; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 24, v4
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, 24, v4
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, 24, v4
; GFX6-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX6-NEXT: v_mul_lo_u32 v7, v8, v6
-; GFX6-NEXT: v_sub_i32_e32 v8, vcc, 23, v4
-; GFX6-NEXT: v_and_b32_e32 v8, v8, v9
+; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX6-NEXT: v_mul_lo_u32 v6, v7, v8
+; GFX6-NEXT: v_sub_i32_e32 v7, vcc, 23, v4
+; GFX6-NEXT: v_and_b32_e32 v7, v7, v9
; GFX6-NEXT: v_and_b32_e32 v4, v4, v9
-; GFX6-NEXT: v_mul_hi_u32 v7, v6, v7
-; GFX6-NEXT: v_lshlrev_b32_e32 v0, v8, v0
+; GFX6-NEXT: v_mul_hi_u32 v6, v8, v6
+; GFX6-NEXT: v_lshlrev_b32_e32 v0, v7, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v7
+; GFX6-NEXT: v_add_i32_e32 v6, vcc, v8, v6
; GFX6-NEXT: v_mul_hi_u32 v6, v5, v6
+; GFX6-NEXT: v_and_b32_e32 v3, v3, v9
; GFX6-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v5, v6
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 24, v2
@@ -2037,40 +2047,42 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX8-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX8-NEXT: v_mov_b32_e32 v8, 0xffffffe8
+; GFX8-NEXT: v_mov_b32_e32 v7, 0xffffffe8
; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
-; GFX8-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
-; GFX8-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
; GFX8-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 1, v1
-; GFX8-NEXT: v_mul_lo_u32 v9, v8, v7
-; GFX8-NEXT: v_mul_hi_u32 v9, v7, v9
-; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v9
-; GFX8-NEXT: v_mul_hi_u32 v7, v4, v7
+; GFX8-NEXT: v_mul_lo_u32 v8, v7, v6
+; GFX8-NEXT: v_mul_hi_u32 v8, v6, v8
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v8
+; GFX8-NEXT: v_mul_hi_u32 v6, v4, v6
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v8, v9
; GFX8-NEXT: v_mov_b32_e32 v9, 0xffffff
; GFX8-NEXT: v_and_b32_e32 v5, v5, v9
+; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX8-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; GFX8-NEXT: v_cvt_u32_f32_e32 v8, v8
; GFX8-NEXT: v_and_b32_e32 v2, v2, v9
-; GFX8-NEXT: v_mul_lo_u32 v7, v7, 24
-; GFX8-NEXT: v_and_b32_e32 v3, v3, v9
-; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v7
-; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, 24, v4
+; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v6
+; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 24, v4
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, 24, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, 24, v4
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX8-NEXT: v_mul_lo_u32 v7, v8, v6
-; GFX8-NEXT: v_sub_u32_e32 v8, vcc, 23, v4
-; GFX8-NEXT: v_and_b32_e32 v8, v8, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX8-NEXT: v_mul_lo_u32 v6, v7, v8
+; GFX8-NEXT: v_sub_u32_e32 v7, vcc, 23, v4
+; GFX8-NEXT: v_and_b32_e32 v7, v7, v9
; GFX8-NEXT: v_and_b32_e32 v4, v4, v9
-; GFX8-NEXT: v_mul_hi_u32 v7, v6, v7
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, v8, v0
+; GFX8-NEXT: v_mul_hi_u32 v6, v8, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, v7, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v2
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v7
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, v8, v6
; GFX8-NEXT: v_mul_hi_u32 v6, v5, v6
+; GFX8-NEXT: v_and_b32_e32 v3, v3, v9
; GFX8-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v5, v6
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, 24, v2
@@ -2092,41 +2104,43 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v6
-; GFX9-NEXT: v_mov_b32_e32 v8, 0xffffffe8
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
-; GFX9-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
-; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX9-NEXT: v_mov_b32_e32 v7, 0xffffffe8
+; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v9, 24
+; GFX9-NEXT: v_rcp_iflag_f32_e32 v9, v9
; GFX9-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX9-NEXT: v_mul_f32_e32 v9, 0x4f7ffffe, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_mul_lo_u32 v8, v7, v6
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 1, v1
-; GFX9-NEXT: v_mul_lo_u32 v9, v8, v7
-; GFX9-NEXT: v_mul_lo_u32 v8, v8, v6
-; GFX9-NEXT: v_mul_hi_u32 v9, v7, v9
; GFX9-NEXT: v_mul_hi_u32 v8, v6, v8
-; GFX9-NEXT: v_add_u32_e32 v7, v7, v9
-; GFX9-NEXT: v_mul_hi_u32 v7, v4, v7
+; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
+; GFX9-NEXT: v_cvt_u32_f32_e32 v8, v9
+; GFX9-NEXT: v_mul_hi_u32 v6, v4, v6
; GFX9-NEXT: v_mov_b32_e32 v9, 0xffffff
; GFX9-NEXT: v_and_b32_e32 v5, v5, v9
-; GFX9-NEXT: v_add_u32_e32 v6, v6, v8
-; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24
-; GFX9-NEXT: v_mul_hi_u32 v6, v5, v6
+; GFX9-NEXT: v_mul_lo_u32 v7, v7, v8
+; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
; GFX9-NEXT: v_and_b32_e32 v2, v2, v9
; GFX9-NEXT: v_and_b32_e32 v3, v3, v9
-; GFX9-NEXT: v_sub_u32_e32 v4, v4, v7
-; GFX9-NEXT: v_subrev_u32_e32 v7, 24, v4
+; GFX9-NEXT: v_mul_hi_u32 v7, v8, v7
+; GFX9-NEXT: v_sub_u32_e32 v4, v4, v6
+; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX9-NEXT: v_subrev_u32_e32 v7, 24, v4
+; GFX9-NEXT: v_add_u32_e32 v7, v8, v7
+; GFX9-NEXT: v_mul_hi_u32 v7, v5, v7
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX9-NEXT: v_subrev_u32_e32 v6, 24, v4
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v4
-; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
-; GFX9-NEXT: v_sub_u32_e32 v7, 23, v4
+; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
+; GFX9-NEXT: v_sub_u32_e32 v6, 23, v4
; GFX9-NEXT: v_and_b32_e32 v4, v4, v9
-; GFX9-NEXT: v_and_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_and_b32_e32 v6, v6, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v2, v4, v2
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, v7, v2
-; GFX9-NEXT: v_sub_u32_e32 v2, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, v6, v2
+; GFX9-NEXT: v_sub_u32_e32 v2, v5, v7
; GFX9-NEXT: v_subrev_u32_e32 v4, 24, v2
; GFX9-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
@@ -2145,30 +2159,32 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v7, 24
; GFX10-NEXT: v_mov_b32_e32 v10, 0xffffff
; GFX10-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v1, 1, v1
; GFX10-NEXT: v_rcp_iflag_f32_e32 v6, v6
+; GFX10-NEXT: v_rcp_iflag_f32_e32 v7, v7
; GFX10-NEXT: v_and_b32_e32 v5, v5, v10
; GFX10-NEXT: v_and_b32_e32 v2, v2, v10
; GFX10-NEXT: v_and_b32_e32 v3, v3, v10
-; GFX10-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 1, v1
; GFX10-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
-; GFX10-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX10-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7
; GFX10-NEXT: v_cvt_u32_f32_e32 v6, v6
-; GFX10-NEXT: v_mul_lo_u32 v8, 0xffffffe8, v7
-; GFX10-NEXT: v_mul_lo_u32 v9, 0xffffffe8, v6
-; GFX10-NEXT: v_mul_hi_u32 v8, v7, v8
-; GFX10-NEXT: v_mul_hi_u32 v9, v6, v9
-; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v8
-; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v9
-; GFX10-NEXT: v_mul_hi_u32 v7, v4, v7
-; GFX10-NEXT: v_mul_hi_u32 v6, v5, v6
-; GFX10-NEXT: v_mul_lo_u32 v7, v7, 24
+; GFX10-NEXT: v_cvt_u32_f32_e32 v7, v7
+; GFX10-NEXT: v_mul_lo_u32 v8, 0xffffffe8, v6
+; GFX10-NEXT: v_mul_lo_u32 v9, 0xffffffe8, v7
+; GFX10-NEXT: v_mul_hi_u32 v8, v6, v8
+; GFX10-NEXT: v_mul_hi_u32 v9, v7, v9
+; GFX10-NEXT: v_add_nc_u32_e32 v6, v6, v8
+; GFX10-NEXT: v_add_nc_u32_e32 v7, v7, v9
+; GFX10-NEXT: v_mul_hi_u32 v6, v4, v6
+; GFX10-NEXT: v_mul_hi_u32 v7, v5, v7
; GFX10-NEXT: v_mul_lo_u32 v6, v6, 24
-; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v7
-; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v6
+; GFX10-NEXT: v_mul_lo_u32 v7, v7, 24
+; GFX10-NEXT: v_sub_nc_u32_e32 v4, v4, v6
+; GFX10-NEXT: v_sub_nc_u32_e32 v5, v5, v7
; GFX10-NEXT: v_subrev_nc_u32_e32 v6, 24, v4
; GFX10-NEXT: v_cmp_le_u32_e32 vcc_lo, 24, v4
; GFX10-NEXT: v_subrev_nc_u32_e32 v7, 24, v5
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/image_ls_mipmap_zero.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/image_ls_mipmap_zero.a16.ll
index 8d1967fe78e9c..af7509fd0897d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/image_ls_mipmap_zero.a16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/image_ls_mipmap_zero.a16.ll
@@ -16,9 +16,8 @@ define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, i16 %s) {
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[DEF]](s32)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX9: $vgpr0 = COPY [[UV]](s32)
@@ -39,9 +38,8 @@ define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, i16 %s) {
; GFX10: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[DEF]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -69,9 +67,7 @@ define amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, i16 %s, i16 %t)
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX9: $vgpr0 = COPY [[UV]](s32)
@@ -93,9 +89,7 @@ define amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, i16 %s, i16 %t)
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
- ; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -124,12 +118,9 @@ define amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, i16 %s, i16 %t,
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -153,12 +144,9 @@ define amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, i16 %s, i16 %t,
; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
- ; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
- ; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -187,9 +175,7 @@ define amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, i16 %s, i1
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX9: $vgpr0 = COPY [[UV]](s32)
@@ -211,9 +197,7 @@ define amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, i16 %s, i1
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
- ; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -242,12 +226,9 @@ define amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, i16 %s, i1
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -271,12 +252,9 @@ define amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, i16 %s, i1
; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
- ; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
- ; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -306,12 +284,9 @@ define amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, i16 %s, i16 %
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -335,12 +310,9 @@ define amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, i16 %s, i16 %
; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
- ; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
- ; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -373,9 +345,8 @@ define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
; GFX10-LABEL: name: store_mip_1d
@@ -396,9 +367,8 @@ define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i
; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
; GFX10: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10: S_ENDPGM 0
main_body:
@@ -426,9 +396,7 @@ define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
; GFX10-LABEL: name: store_mip_2d
@@ -450,9 +418,7 @@ define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i
; GFX10: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10: S_ENDPGM 0
main_body:
@@ -481,12 +447,9 @@ define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.3d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
@@ -510,12 +473,9 @@ define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.3d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10: S_ENDPGM 0
@@ -544,9 +504,7 @@ define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
; GFX10-LABEL: name: store_mip_1darray
@@ -568,9 +526,7 @@ define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX10: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10: S_ENDPGM 0
main_body:
@@ -599,12 +555,9 @@ define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
@@ -628,12 +581,9 @@ define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10: S_ENDPGM 0
@@ -663,12 +613,9 @@ define amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata,
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.cube), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
@@ -692,12 +639,9 @@ define amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata,
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.cube), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, 0, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10: S_ENDPGM 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
index d412b9c3b789f..44067b31ffcca 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
@@ -79,12 +79,9 @@ body: |
; GFX6-LABEL: name: test_add_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
+ ; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; GFX6: $vgpr0 = COPY [[AND]](s32)
; GFX8-LABEL: name: test_add_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
@@ -125,17 +122,11 @@ body: |
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY5]]
+ ; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[BITCAST]], [[BITCAST1]]
+ ; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[LSHR1]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C1]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C1]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -183,17 +174,11 @@ body: |
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY6]], [[COPY7]]
+ ; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY3]]
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY8]], [[COPY9]]
+ ; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY4]]
; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
- ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY10]], [[COPY11]]
+ ; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY5]]
; GFX6: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD2]](s32)
; GFX6: S_ENDPGM 0, implicit [[TRUNC]](s16), implicit [[TRUNC1]](s16), implicit [[TRUNC2]](s16)
; GFX8-LABEL: name: test_add_v3s16
@@ -220,19 +205,13 @@ body: |
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
+ ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY6]](s32)
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[DEF]](s32)
; GFX9: [[ADD:%[0-9]+]]:_(<2 x s16>) = G_ADD [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]]
; GFX9: [[ADD1:%[0-9]+]]:_(<2 x s16>) = G_ADD [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]]
; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[ADD]](<2 x s16>)
@@ -283,30 +262,18 @@ body: |
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY5]]
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY6]], [[COPY7]]
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[COPY8]], [[COPY9]]
+ ; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[BITCAST]], [[BITCAST2]]
+ ; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[LSHR2]]
+ ; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[BITCAST1]], [[BITCAST3]]
+ ; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR1]], [[LSHR3]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C1]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C1]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[ADD3]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C1]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD3]], [[C1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -413,12 +380,9 @@ body: |
; GFX6-LABEL: name: test_add_s7
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
+ ; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; GFX6: $vgpr0 = COPY [[AND]](s32)
; GFX8-LABEL: name: test_add_s7
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
@@ -458,27 +422,18 @@ body: |
; GFX6-LABEL: name: test_add_s24
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
+ ; GFX6: $vgpr0 = COPY [[ADD]](s32)
; GFX8-LABEL: name: test_add_s24
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; GFX8: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX8: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
+ ; GFX8: $vgpr0 = COPY [[ADD]](s32)
; GFX9-LABEL: name: test_add_s24
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX9: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
+ ; GFX9: $vgpr0 = COPY [[ADD]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s24) = G_TRUNC %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
index 59cc9777704f6..16fa0c808fddf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
@@ -60,9 +60,7 @@ body: |
; CHECK: [[AND1:%[0-9]+]]:_(s1) = G_AND [[ICMP1]], [[ICMP3]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[AND1]](s1)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
@@ -100,10 +98,7 @@ body: |
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[AND1]](s1)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[AND2]](s1)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
@@ -186,11 +181,8 @@ body: |
; CHECK-LABEL: name: test_and_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
+ ; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s7) = G_TRUNC %0
@@ -209,11 +201,8 @@ body: |
; CHECK-LABEL: name: test_and_s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
+ ; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s8) = G_TRUNC %0
@@ -255,11 +244,8 @@ body: |
; CHECK-LABEL: name: test_and_s24
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
+ ; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s24) = G_TRUNC %0
@@ -278,11 +264,8 @@ body: |
; CHECK-LABEL: name: test_and_s48
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
- ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[COPY1]]
+ ; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s48) = G_TRUNC %0
@@ -457,24 +440,18 @@ body: |
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL1]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL2]]
; CHECK: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -544,24 +521,18 @@ body: |
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV19]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL1]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL2]]
; CHECK: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -630,27 +601,11 @@ body: |
; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<4 x s32>)
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[COPY7]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[AND2]](s32)
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[AND3]](s32)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[UV4]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[UV5]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[UV6]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[UV7]]
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
%0:_(<4 x s8>) = G_IMPLICIT_DEF
%1:_(<4 x s8>) = G_IMPLICIT_DEF
@@ -669,47 +624,15 @@ body: |
; CHECK: [[DEF1:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<8 x s32>)
; CHECK: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<8 x s32>)
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV8]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV9]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV10]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV11]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[COPY7]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV12]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[COPY9]]
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV13]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[COPY11]]
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV14]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[COPY13]]
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[UV15]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[COPY15]]
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[AND2]](s32)
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[AND3]](s32)
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[AND4]](s32)
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[AND5]](s32)
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[AND6]](s32)
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[AND7]](s32)
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
- ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[COPY19]](s32)
- ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[COPY20]](s32)
- ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[COPY21]](s32)
- ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[COPY22]](s32)
- ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[COPY23]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[UV8]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[UV9]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[UV10]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[UV11]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[UV12]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[UV13]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[UV6]], [[UV14]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[UV7]], [[UV15]]
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32), [[AND4]](s32), [[AND5]](s32), [[AND6]](s32), [[AND7]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<8 x s32>)
%0:_(<8 x s8>) = G_IMPLICIT_DEF
%1:_(<8 x s8>) = G_IMPLICIT_DEF
@@ -728,89 +651,25 @@ body: |
; CHECK: [[DEF1:%[0-9]+]]:_(<16 x s32>) = G_IMPLICIT_DEF
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<16 x s32>)
; CHECK: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<16 x s32>)
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV16]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV17]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV18]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV19]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[COPY7]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV20]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[COPY9]]
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV21]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[COPY11]]
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV22]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[COPY13]]
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[UV23]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[COPY15]]
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[AND2]](s32)
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[AND3]](s32)
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[AND4]](s32)
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[AND5]](s32)
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[AND6]](s32)
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[AND7]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[UV16]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[UV17]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[UV18]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[UV19]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[UV20]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[UV21]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[UV6]], [[UV22]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[UV7]], [[UV23]]
; CHECK: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32), [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32), [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32), [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32), [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32), [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32), [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<16 x s32>)
; CHECK: [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32), [[UV50:%[0-9]+]]:_(s32), [[UV51:%[0-9]+]]:_(s32), [[UV52:%[0-9]+]]:_(s32), [[UV53:%[0-9]+]]:_(s32), [[UV54:%[0-9]+]]:_(s32), [[UV55:%[0-9]+]]:_(s32), [[UV56:%[0-9]+]]:_(s32), [[UV57:%[0-9]+]]:_(s32), [[UV58:%[0-9]+]]:_(s32), [[UV59:%[0-9]+]]:_(s32), [[UV60:%[0-9]+]]:_(s32), [[UV61:%[0-9]+]]:_(s32), [[UV62:%[0-9]+]]:_(s32), [[UV63:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<16 x s32>)
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[UV40]](s32)
- ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV56]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[COPY25]]
- ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[UV41]](s32)
- ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[UV57]](s32)
- ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[COPY27]]
- ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[UV42]](s32)
- ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV58]](s32)
- ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[COPY29]]
- ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[UV43]](s32)
- ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[UV59]](s32)
- ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[COPY31]]
- ; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[UV44]](s32)
- ; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[UV60]](s32)
- ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[COPY33]]
- ; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[UV45]](s32)
- ; CHECK: [[COPY35:%[0-9]+]]:_(s32) = COPY [[UV61]](s32)
- ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY34]], [[COPY35]]
- ; CHECK: [[COPY36:%[0-9]+]]:_(s32) = COPY [[UV46]](s32)
- ; CHECK: [[COPY37:%[0-9]+]]:_(s32) = COPY [[UV62]](s32)
- ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY36]], [[COPY37]]
- ; CHECK: [[COPY38:%[0-9]+]]:_(s32) = COPY [[UV47]](s32)
- ; CHECK: [[COPY39:%[0-9]+]]:_(s32) = COPY [[UV63]](s32)
- ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY38]], [[COPY39]]
- ; CHECK: [[COPY40:%[0-9]+]]:_(s32) = COPY [[AND8]](s32)
- ; CHECK: [[COPY41:%[0-9]+]]:_(s32) = COPY [[AND9]](s32)
- ; CHECK: [[COPY42:%[0-9]+]]:_(s32) = COPY [[AND10]](s32)
- ; CHECK: [[COPY43:%[0-9]+]]:_(s32) = COPY [[AND11]](s32)
- ; CHECK: [[COPY44:%[0-9]+]]:_(s32) = COPY [[AND12]](s32)
- ; CHECK: [[COPY45:%[0-9]+]]:_(s32) = COPY [[AND13]](s32)
- ; CHECK: [[COPY46:%[0-9]+]]:_(s32) = COPY [[AND14]](s32)
- ; CHECK: [[COPY47:%[0-9]+]]:_(s32) = COPY [[AND15]](s32)
- ; CHECK: [[COPY48:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; CHECK: [[COPY49:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; CHECK: [[COPY50:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
- ; CHECK: [[COPY51:%[0-9]+]]:_(s32) = COPY [[COPY19]](s32)
- ; CHECK: [[COPY52:%[0-9]+]]:_(s32) = COPY [[COPY20]](s32)
- ; CHECK: [[COPY53:%[0-9]+]]:_(s32) = COPY [[COPY21]](s32)
- ; CHECK: [[COPY54:%[0-9]+]]:_(s32) = COPY [[COPY22]](s32)
- ; CHECK: [[COPY55:%[0-9]+]]:_(s32) = COPY [[COPY23]](s32)
- ; CHECK: [[COPY56:%[0-9]+]]:_(s32) = COPY [[COPY40]](s32)
- ; CHECK: [[COPY57:%[0-9]+]]:_(s32) = COPY [[COPY41]](s32)
- ; CHECK: [[COPY58:%[0-9]+]]:_(s32) = COPY [[COPY42]](s32)
- ; CHECK: [[COPY59:%[0-9]+]]:_(s32) = COPY [[COPY43]](s32)
- ; CHECK: [[COPY60:%[0-9]+]]:_(s32) = COPY [[COPY44]](s32)
- ; CHECK: [[COPY61:%[0-9]+]]:_(s32) = COPY [[COPY45]](s32)
- ; CHECK: [[COPY62:%[0-9]+]]:_(s32) = COPY [[COPY46]](s32)
- ; CHECK: [[COPY63:%[0-9]+]]:_(s32) = COPY [[COPY47]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[COPY48]](s32), [[COPY49]](s32), [[COPY50]](s32), [[COPY51]](s32), [[COPY52]](s32), [[COPY53]](s32), [[COPY54]](s32), [[COPY55]](s32), [[COPY56]](s32), [[COPY57]](s32), [[COPY58]](s32), [[COPY59]](s32), [[COPY60]](s32), [[COPY61]](s32), [[COPY62]](s32), [[COPY63]](s32)
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV40]], [[UV56]]
+ ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[UV41]], [[UV57]]
+ ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[UV42]], [[UV58]]
+ ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[UV43]], [[UV59]]
+ ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV44]], [[UV60]]
+ ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[UV45]], [[UV61]]
+ ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[UV46]], [[UV62]]
+ ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[UV47]], [[UV63]]
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32), [[AND4]](s32), [[AND5]](s32), [[AND6]](s32), [[AND7]](s32), [[AND8]](s32), [[AND9]](s32), [[AND10]](s32), [[AND11]](s32), [[AND12]](s32), [[AND13]](s32), [[AND14]](s32), [[AND15]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[BUILD_VECTOR]](<16 x s32>)
%0:_(<16 x s8>) = G_IMPLICIT_DEF
%1:_(<16 x s8>) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
index 2823f07fec0e5..61b0ba7e8efec 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
@@ -40,8 +40,7 @@ body: |
; CHECK-LABEL: name: test_anyext_s16_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s32) = G_ANYEXT %1
@@ -56,8 +55,7 @@ body: |
; CHECK-LABEL: name: test_anyext_s24_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s24) = G_TRUNC %0
%2:_(s32) = G_ANYEXT %1
@@ -101,9 +99,7 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[LSHR]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s32>) = G_ANYEXT %0
@@ -127,10 +123,7 @@ body: |
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[LSHR]](s32), [[BITCAST1]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<3 x s16>) = G_EXTRACT %0, 0
@@ -250,8 +243,7 @@ body: |
; CHECK-LABEL: name: test_anyext_s7_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: S_ENDPGM 0, implicit [[COPY1]](s32)
+ ; CHECK: S_ENDPGM 0, implicit [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
%2:_(s32) = G_ANYEXT %1
@@ -266,8 +258,7 @@ body: |
; CHECK-LABEL: name: test_anyext_s8_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: S_ENDPGM 0, implicit [[COPY1]](s32)
+ ; CHECK: S_ENDPGM 0, implicit [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
%2:_(s32) = G_ANYEXT %1
@@ -633,10 +624,8 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -660,8 +649,7 @@ body: |
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-LABEL: name: test_anyext_s112_to_s128
; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY [[COPY]](s128)
- ; CHECK: S_ENDPGM 0, implicit [[COPY1]](s128)
+ ; CHECK: S_ENDPGM 0, implicit [[COPY]](s128)
%0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s112) = G_TRUNC %0
%2:_(s128) = G_ANYEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
index c0472236bb099..32759efe54a54 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
@@ -2,7 +2,6 @@
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -global-isel-abort=0 -o - %s | FileCheck -check-prefix=SI %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=0 -o - %s | FileCheck -check-prefix=VI %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -O0 -run-pass=legalizer -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
---
name: test_ashr_s32_s32
@@ -95,24 +94,21 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)
; SI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; VI-LABEL: name: test_ashr_s64_s16
; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)
; VI: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
; GFX9-LABEL: name: test_ashr_s64_s16
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[AND]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
@@ -131,11 +127,9 @@ body: |
; SI-LABEL: name: test_ashr_s16_s32
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[COPY1]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; SI: $vgpr0 = COPY [[COPY3]](s32)
+ ; SI: $vgpr0 = COPY [[ASHR]](s32)
; VI-LABEL: name: test_ashr_s16_s32
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -170,13 +164,10 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[ASHR]](s32)
; VI-LABEL: name: test_ashr_s16_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -212,13 +203,10 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[ASHR]](s32)
; VI-LABEL: name: test_ashr_s16_i8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -258,19 +246,15 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[ASHR]](s32)
; VI-LABEL: name: test_ashr_i8_i8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C1]](s16)
@@ -283,10 +267,8 @@ body: |
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[TRUNC1]](s16)
@@ -311,19 +293,15 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 7
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[ASHR]](s32)
; VI-LABEL: name: test_ashr_s7_s7
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C1]](s16)
@@ -336,10 +314,8 @@ body: |
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 7
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[TRUNC1]](s16)
@@ -364,35 +340,26 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 24
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 24
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[ASHR]](s32)
; VI-LABEL: name: test_ashr_s24_s24
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; VI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 24
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; VI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 24
; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; VI: $vgpr0 = COPY [[COPY4]](s32)
+ ; VI: $vgpr0 = COPY [[ASHR]](s32)
; GFX9-LABEL: name: test_ashr_s24_s24
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 24
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 24
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX9: $vgpr0 = COPY [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s24) = G_TRUNC %0
@@ -412,24 +379,21 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[AND]](s32)
; SI: $vgpr0 = COPY [[ASHR]](s32)
; VI-LABEL: name: test_ashr_s32_s24
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[AND]](s32)
; VI: $vgpr0 = COPY [[ASHR]](s32)
; GFX9-LABEL: name: test_ashr_s32_s24
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[AND]](s32)
; GFX9: $vgpr0 = COPY [[ASHR]](s32)
%0:_(s32) = COPY $vgpr0
@@ -628,20 +592,14 @@ body: |
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[AND1]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -690,17 +648,13 @@ body: |
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[UV]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[UV1]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -767,20 +721,14 @@ body: |
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[AND1]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 16
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
; SI: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[AND2]](s32)
; SI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; SI: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
@@ -791,24 +739,18 @@ body: |
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; SI: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL]]
; SI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ASHR2]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ASHR2]], [[C1]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL1]]
; SI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL2]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -853,15 +795,12 @@ body: |
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ASHR2]](s16)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -894,15 +833,10 @@ body: |
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR1]](s16)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[COPY4]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[BITCAST1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR1]](s32), [[BITCAST2]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
@@ -937,37 +871,25 @@ body: |
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
; SI: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
; SI: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[AND1]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 16
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
; SI: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[AND2]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 16
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 16
; SI: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[AND3]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[ASHR2]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[ASHR3]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ASHR2]], [[C1]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ASHR3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL1]]
; SI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
index d43f596ee946b..41ce98298a01e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
@@ -357,13 +357,7 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[LSHR]](s32), [[LSHR1]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(s32) = COPY $vgpr0
%1:_(s24) = G_TRUNC %0
@@ -386,10 +380,7 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; CHECK: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[LSHR]](s32), [[UV1]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s48) = G_TRUNC %0
@@ -427,8 +418,7 @@ body: |
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[OR2]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s8>) = G_TRUNC %0
%2:_(s24) = G_BITCAST %1
@@ -446,21 +436,17 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
- ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s16>) = G_TRUNC %0
%2:_(s48) = G_BITCAST %1
@@ -482,11 +468,7 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[LSHR]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
@@ -557,11 +539,7 @@ body: |
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD1]](s16)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD2]](s16)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD3]](s16)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32), [[ANYEXT3]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<4 x s8>) = G_BITCAST %0
@@ -593,17 +571,13 @@ body: |
; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[UV7]](s32)
; CHECK: [[ADD3:%[0-9]+]]:_(s16) = G_ADD [[TRUNC6]], [[TRUNC7]]
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[ADD]](s16)
- ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY1]], [[C]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[ADD1]](s16)
- ; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[ADD]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[ADD1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C1]](s16)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[ADD2]](s16)
- ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[ADD3]](s16)
- ; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[ADD2]], [[C]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[ADD3]], [[C]]
; CHECK: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C1]](s16)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -683,15 +657,7 @@ body: |
; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD5]](s16)
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD6]](s16)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD7]](s16)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[ANYEXT4]](s32)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[ANYEXT5]](s32)
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[ANYEXT6]](s32)
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[ANYEXT7]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32), [[ANYEXT3]](s32), [[ANYEXT4]](s32), [[ANYEXT5]](s32), [[ANYEXT6]](s32), [[ANYEXT7]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<8 x s32>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<8 x s4>) = G_BITCAST %0
@@ -735,35 +701,27 @@ body: |
; CHECK: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[UV15]](s32)
; CHECK: [[ADD7:%[0-9]+]]:_(s16) = G_ADD [[TRUNC14]], [[TRUNC15]]
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
- ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[ADD]](s16)
- ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY1]], [[C]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[ADD1]](s16)
- ; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[ADD]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[ADD1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C1]](s16)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[ADD2]](s16)
- ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[ADD2]], [[C]]
; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND2]], [[C2]](s16)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[SHL1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[ADD3]](s16)
- ; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[ADD3]], [[C]]
; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 12
; CHECK: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C3]](s16)
; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[SHL2]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[ADD4]](s16)
- ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY5]], [[C]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s16) = COPY [[ADD5]](s16)
- ; CHECK: [[AND5:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[ADD4]], [[C]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s16) = G_AND [[ADD5]], [[C]]
; CHECK: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C1]](s16)
; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL3]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s16) = COPY [[ADD6]](s16)
- ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[ADD6]], [[C]]
; CHECK: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND6]], [[C2]](s16)
; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[OR3]], [[SHL4]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s16) = COPY [[ADD7]](s16)
- ; CHECK: [[AND7:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s16) = G_AND [[ADD7]], [[C]]
; CHECK: [[SHL5:%[0-9]+]]:_(s16) = G_SHL [[AND7]], [[C3]](s16)
; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[OR4]], [[SHL5]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
@@ -916,36 +874,28 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<8 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<8 x s32>)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV12]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV13]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV12]], [[C]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[UV13]], [[C]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV14]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[UV14]], [[C]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C2]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV15]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[UV15]], [[C]]
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C3]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -1103,59 +1053,43 @@ body: |
; CHECK: [[ANYEXT14:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD14]](s16)
; CHECK: [[ANYEXT15:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD15]](s16)
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C7]]
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C7]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C7]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C7]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C7]]
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C7]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C7]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C7]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[ANYEXT4]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C7]]
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[ANYEXT5]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C7]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C7]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C7]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C3]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[ANYEXT6]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C7]]
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[ANYEXT7]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C7]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[C7]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT7]], [[C7]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C3]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CHECK: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
- ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[ANYEXT8]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C7]]
- ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[ANYEXT9]](s32)
- ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C7]]
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ANYEXT8]], [[C7]]
+ ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ANYEXT9]], [[C7]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C3]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[ANYEXT10]](s32)
- ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C7]]
- ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[ANYEXT11]](s32)
- ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C7]]
+ ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[ANYEXT10]], [[C7]]
+ ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[ANYEXT11]], [[C7]]
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C3]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
- ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[ANYEXT12]](s32)
- ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C7]]
- ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[ANYEXT13]](s32)
- ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C7]]
+ ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[ANYEXT12]], [[C7]]
+ ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[ANYEXT13]], [[C7]]
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C3]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL6]]
; CHECK: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR6]](s32)
- ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[ANYEXT14]](s32)
- ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C7]]
- ; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[ANYEXT15]](s32)
- ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C7]]
+ ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[ANYEXT14]], [[C7]]
+ ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[ANYEXT15]], [[C7]]
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C3]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND14]], [[SHL7]]
; CHECK: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR7]](s32)
@@ -1188,39 +1122,31 @@ body: |
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C3]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C5]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C6]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C7]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
@@ -1233,34 +1159,26 @@ body: |
; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; CHECK: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV15]](<2 x s16>)
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL7]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C3]](s32)
; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
; CHECK: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C4]](s32)
; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[SHL9]]
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C1]]
; CHECK: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C]](s32)
; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C1]]
+ ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C5]](s32)
; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C1]]
+ ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C1]]
; CHECK: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C6]](s32)
; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR11]], [[SHL12]]
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C1]]
+ ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C1]]
; CHECK: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C7]](s32)
; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR6]](s32), [[OR13]](s32)
@@ -1292,30 +1210,14 @@ body: |
; CHECK: [[LSHR3:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[LSHR4:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC2]], [[C1]](s16)
; CHECK: [[LSHR5:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC3]], [[C1]](s16)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
- ; CHECK: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[COPY1]], [[COPY2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[LSHR2]](s16)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[LSHR2]](s16)
- ; CHECK: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[COPY3]], [[COPY4]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
- ; CHECK: [[ADD2:%[0-9]+]]:_(s16) = G_ADD [[COPY5]], [[COPY6]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s16) = COPY [[LSHR3]](s16)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s16) = COPY [[LSHR3]](s16)
- ; CHECK: [[ADD3:%[0-9]+]]:_(s16) = G_ADD [[COPY7]], [[COPY8]]
- ; CHECK: [[COPY9:%[0-9]+]]:_(s16) = COPY [[TRUNC2]](s16)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s16) = COPY [[TRUNC2]](s16)
- ; CHECK: [[ADD4:%[0-9]+]]:_(s16) = G_ADD [[COPY9]], [[COPY10]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s16) = COPY [[LSHR4]](s16)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s16) = COPY [[LSHR4]](s16)
- ; CHECK: [[ADD5:%[0-9]+]]:_(s16) = G_ADD [[COPY11]], [[COPY12]]
- ; CHECK: [[COPY13:%[0-9]+]]:_(s16) = COPY [[TRUNC3]](s16)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s16) = COPY [[TRUNC3]](s16)
- ; CHECK: [[ADD6:%[0-9]+]]:_(s16) = G_ADD [[COPY13]], [[COPY14]]
- ; CHECK: [[COPY15:%[0-9]+]]:_(s16) = COPY [[LSHR5]](s16)
- ; CHECK: [[COPY16:%[0-9]+]]:_(s16) = COPY [[LSHR5]](s16)
- ; CHECK: [[ADD7:%[0-9]+]]:_(s16) = G_ADD [[COPY15]], [[COPY16]]
+ ; CHECK: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[TRUNC]]
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[LSHR2]], [[LSHR2]]
+ ; CHECK: [[ADD2:%[0-9]+]]:_(s16) = G_ADD [[TRUNC1]], [[TRUNC1]]
+ ; CHECK: [[ADD3:%[0-9]+]]:_(s16) = G_ADD [[LSHR3]], [[LSHR3]]
+ ; CHECK: [[ADD4:%[0-9]+]]:_(s16) = G_ADD [[TRUNC2]], [[TRUNC2]]
+ ; CHECK: [[ADD5:%[0-9]+]]:_(s16) = G_ADD [[LSHR4]], [[LSHR4]]
+ ; CHECK: [[ADD6:%[0-9]+]]:_(s16) = G_ADD [[TRUNC3]], [[TRUNC3]]
+ ; CHECK: [[ADD7:%[0-9]+]]:_(s16) = G_ADD [[LSHR5]], [[LSHR5]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD1]](s16)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD2]](s16)
@@ -1425,51 +1327,39 @@ body: |
; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr8_vgpr9_vgpr10_vgpr11
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[C]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[UV6]], [[C]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C2]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[UV7]], [[C]]
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C3]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CHECK: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<4 x s32>)
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV8]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV9]](s32)
- ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV8]], [[C]]
+ ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[UV9]], [[C]]
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C1]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV10]](s32)
- ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C]]
+ ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[UV10]], [[C]]
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C2]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV11]](s32)
- ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C]]
+ ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[UV11]], [[C]]
; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C3]](s32)
; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -1512,23 +1402,17 @@ body: |
; CHECK: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[UV11]](s32)
; CHECK: [[ADD5:%[0-9]+]]:_(s16) = G_ADD [[TRUNC10]], [[TRUNC11]]
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[ADD]](s16)
- ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY1]], [[C]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[ADD1]](s16)
- ; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[ADD]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[ADD1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C1]](s16)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[ADD2]](s16)
- ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[ADD3]](s16)
- ; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[ADD2]], [[C]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[ADD3]], [[C]]
; CHECK: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C1]](s16)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL1]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[ADD4]](s16)
- ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY5]], [[C]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s16) = COPY [[ADD5]](s16)
- ; CHECK: [[AND5:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[ADD4]], [[C]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s16) = G_AND [[ADD5]], [[C]]
; CHECK: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C1]](s16)
; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
@@ -1586,25 +1470,19 @@ body: |
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD2]](s16)
; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT4]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ANYEXT5]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C1]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C1]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -1651,54 +1529,22 @@ body: |
; CHECK: [[LSHR9:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC5]], [[C1]](s16)
; CHECK: [[LSHR10:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC6]], [[C1]](s16)
; CHECK: [[LSHR11:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC7]], [[C1]](s16)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
- ; CHECK: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[COPY1]], [[COPY2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[LSHR2]](s16)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[LSHR2]](s16)
- ; CHECK: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[COPY3]], [[COPY4]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
- ; CHECK: [[ADD2:%[0-9]+]]:_(s16) = G_ADD [[COPY5]], [[COPY6]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s16) = COPY [[LSHR3]](s16)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s16) = COPY [[LSHR3]](s16)
- ; CHECK: [[ADD3:%[0-9]+]]:_(s16) = G_ADD [[COPY7]], [[COPY8]]
- ; CHECK: [[COPY9:%[0-9]+]]:_(s16) = COPY [[TRUNC2]](s16)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s16) = COPY [[TRUNC2]](s16)
- ; CHECK: [[ADD4:%[0-9]+]]:_(s16) = G_ADD [[COPY9]], [[COPY10]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s16) = COPY [[LSHR4]](s16)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s16) = COPY [[LSHR4]](s16)
- ; CHECK: [[ADD5:%[0-9]+]]:_(s16) = G_ADD [[COPY11]], [[COPY12]]
- ; CHECK: [[COPY13:%[0-9]+]]:_(s16) = COPY [[TRUNC3]](s16)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s16) = COPY [[TRUNC3]](s16)
- ; CHECK: [[ADD6:%[0-9]+]]:_(s16) = G_ADD [[COPY13]], [[COPY14]]
- ; CHECK: [[COPY15:%[0-9]+]]:_(s16) = COPY [[LSHR5]](s16)
- ; CHECK: [[COPY16:%[0-9]+]]:_(s16) = COPY [[LSHR5]](s16)
- ; CHECK: [[ADD7:%[0-9]+]]:_(s16) = G_ADD [[COPY15]], [[COPY16]]
- ; CHECK: [[COPY17:%[0-9]+]]:_(s16) = COPY [[TRUNC4]](s16)
- ; CHECK: [[COPY18:%[0-9]+]]:_(s16) = COPY [[TRUNC4]](s16)
- ; CHECK: [[ADD8:%[0-9]+]]:_(s16) = G_ADD [[COPY17]], [[COPY18]]
- ; CHECK: [[COPY19:%[0-9]+]]:_(s16) = COPY [[LSHR8]](s16)
- ; CHECK: [[COPY20:%[0-9]+]]:_(s16) = COPY [[LSHR8]](s16)
- ; CHECK: [[ADD9:%[0-9]+]]:_(s16) = G_ADD [[COPY19]], [[COPY20]]
- ; CHECK: [[COPY21:%[0-9]+]]:_(s16) = COPY [[TRUNC5]](s16)
- ; CHECK: [[COPY22:%[0-9]+]]:_(s16) = COPY [[TRUNC5]](s16)
- ; CHECK: [[ADD10:%[0-9]+]]:_(s16) = G_ADD [[COPY21]], [[COPY22]]
- ; CHECK: [[COPY23:%[0-9]+]]:_(s16) = COPY [[LSHR9]](s16)
- ; CHECK: [[COPY24:%[0-9]+]]:_(s16) = COPY [[LSHR9]](s16)
- ; CHECK: [[ADD11:%[0-9]+]]:_(s16) = G_ADD [[COPY23]], [[COPY24]]
- ; CHECK: [[COPY25:%[0-9]+]]:_(s16) = COPY [[TRUNC6]](s16)
- ; CHECK: [[COPY26:%[0-9]+]]:_(s16) = COPY [[TRUNC6]](s16)
- ; CHECK: [[ADD12:%[0-9]+]]:_(s16) = G_ADD [[COPY25]], [[COPY26]]
- ; CHECK: [[COPY27:%[0-9]+]]:_(s16) = COPY [[LSHR10]](s16)
- ; CHECK: [[COPY28:%[0-9]+]]:_(s16) = COPY [[LSHR10]](s16)
- ; CHECK: [[ADD13:%[0-9]+]]:_(s16) = G_ADD [[COPY27]], [[COPY28]]
- ; CHECK: [[COPY29:%[0-9]+]]:_(s16) = COPY [[TRUNC7]](s16)
- ; CHECK: [[COPY30:%[0-9]+]]:_(s16) = COPY [[TRUNC7]](s16)
- ; CHECK: [[ADD14:%[0-9]+]]:_(s16) = G_ADD [[COPY29]], [[COPY30]]
- ; CHECK: [[COPY31:%[0-9]+]]:_(s16) = COPY [[LSHR11]](s16)
- ; CHECK: [[COPY32:%[0-9]+]]:_(s16) = COPY [[LSHR11]](s16)
- ; CHECK: [[ADD15:%[0-9]+]]:_(s16) = G_ADD [[COPY31]], [[COPY32]]
+ ; CHECK: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[TRUNC]]
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[LSHR2]], [[LSHR2]]
+ ; CHECK: [[ADD2:%[0-9]+]]:_(s16) = G_ADD [[TRUNC1]], [[TRUNC1]]
+ ; CHECK: [[ADD3:%[0-9]+]]:_(s16) = G_ADD [[LSHR3]], [[LSHR3]]
+ ; CHECK: [[ADD4:%[0-9]+]]:_(s16) = G_ADD [[TRUNC2]], [[TRUNC2]]
+ ; CHECK: [[ADD5:%[0-9]+]]:_(s16) = G_ADD [[LSHR4]], [[LSHR4]]
+ ; CHECK: [[ADD6:%[0-9]+]]:_(s16) = G_ADD [[TRUNC3]], [[TRUNC3]]
+ ; CHECK: [[ADD7:%[0-9]+]]:_(s16) = G_ADD [[LSHR5]], [[LSHR5]]
+ ; CHECK: [[ADD8:%[0-9]+]]:_(s16) = G_ADD [[TRUNC4]], [[TRUNC4]]
+ ; CHECK: [[ADD9:%[0-9]+]]:_(s16) = G_ADD [[LSHR8]], [[LSHR8]]
+ ; CHECK: [[ADD10:%[0-9]+]]:_(s16) = G_ADD [[TRUNC5]], [[TRUNC5]]
+ ; CHECK: [[ADD11:%[0-9]+]]:_(s16) = G_ADD [[LSHR9]], [[LSHR9]]
+ ; CHECK: [[ADD12:%[0-9]+]]:_(s16) = G_ADD [[TRUNC6]], [[TRUNC6]]
+ ; CHECK: [[ADD13:%[0-9]+]]:_(s16) = G_ADD [[LSHR10]], [[LSHR10]]
+ ; CHECK: [[ADD14:%[0-9]+]]:_(s16) = G_ADD [[TRUNC7]], [[TRUNC7]]
+ ; CHECK: [[ADD15:%[0-9]+]]:_(s16) = G_ADD [[LSHR11]], [[LSHR11]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD1]](s16)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD2]](s16)
@@ -1715,23 +1561,7 @@ body: |
; CHECK: [[ANYEXT13:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD13]](s16)
; CHECK: [[ANYEXT14:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD14]](s16)
; CHECK: [[ANYEXT15:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD15]](s16)
- ; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[COPY35:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[COPY36:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
- ; CHECK: [[COPY37:%[0-9]+]]:_(s32) = COPY [[ANYEXT4]](s32)
- ; CHECK: [[COPY38:%[0-9]+]]:_(s32) = COPY [[ANYEXT5]](s32)
- ; CHECK: [[COPY39:%[0-9]+]]:_(s32) = COPY [[ANYEXT6]](s32)
- ; CHECK: [[COPY40:%[0-9]+]]:_(s32) = COPY [[ANYEXT7]](s32)
- ; CHECK: [[COPY41:%[0-9]+]]:_(s32) = COPY [[ANYEXT8]](s32)
- ; CHECK: [[COPY42:%[0-9]+]]:_(s32) = COPY [[ANYEXT9]](s32)
- ; CHECK: [[COPY43:%[0-9]+]]:_(s32) = COPY [[ANYEXT10]](s32)
- ; CHECK: [[COPY44:%[0-9]+]]:_(s32) = COPY [[ANYEXT11]](s32)
- ; CHECK: [[COPY45:%[0-9]+]]:_(s32) = COPY [[ANYEXT12]](s32)
- ; CHECK: [[COPY46:%[0-9]+]]:_(s32) = COPY [[ANYEXT13]](s32)
- ; CHECK: [[COPY47:%[0-9]+]]:_(s32) = COPY [[ANYEXT14]](s32)
- ; CHECK: [[COPY48:%[0-9]+]]:_(s32) = COPY [[ANYEXT15]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[COPY33]](s32), [[COPY34]](s32), [[COPY35]](s32), [[COPY36]](s32), [[COPY37]](s32), [[COPY38]](s32), [[COPY39]](s32), [[COPY40]](s32), [[COPY41]](s32), [[COPY42]](s32), [[COPY43]](s32), [[COPY44]](s32), [[COPY45]](s32), [[COPY46]](s32), [[COPY47]](s32), [[COPY48]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32), [[ANYEXT3]](s32), [[ANYEXT4]](s32), [[ANYEXT5]](s32), [[ANYEXT6]](s32), [[ANYEXT7]](s32), [[ANYEXT8]](s32), [[ANYEXT9]](s32), [[ANYEXT10]](s32), [[ANYEXT11]](s32), [[ANYEXT12]](s32), [[ANYEXT13]](s32), [[ANYEXT14]](s32), [[ANYEXT15]](s32)
; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<16 x s32>)
%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<16 x s8>) = G_BITCAST %0
@@ -1914,23 +1744,7 @@ body: |
; CHECK: [[ANYEXT13:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD13]](s16)
; CHECK: [[ANYEXT14:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD14]](s16)
; CHECK: [[ANYEXT15:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD15]](s16)
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[ANYEXT4]](s32)
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[ANYEXT5]](s32)
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[ANYEXT6]](s32)
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[ANYEXT7]](s32)
- ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[ANYEXT8]](s32)
- ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[ANYEXT9]](s32)
- ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[ANYEXT10]](s32)
- ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[ANYEXT11]](s32)
- ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[ANYEXT12]](s32)
- ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[ANYEXT13]](s32)
- ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[ANYEXT14]](s32)
- ; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[ANYEXT15]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32), [[COPY32]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32), [[ANYEXT3]](s32), [[ANYEXT4]](s32), [[ANYEXT5]](s32), [[ANYEXT6]](s32), [[ANYEXT7]](s32), [[ANYEXT8]](s32), [[ANYEXT9]](s32), [[ANYEXT10]](s32), [[ANYEXT11]](s32), [[ANYEXT12]](s32), [[ANYEXT13]](s32), [[ANYEXT14]](s32), [[ANYEXT15]](s32)
; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<16 x s32>)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<16 x s8>) = G_BITCAST %0
@@ -1949,66 +1763,50 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<16 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<16 x s32>)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV20]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV21]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV20]], [[C]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[UV21]], [[C]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV22]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[UV22]], [[C]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C2]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV23]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[UV23]], [[C]]
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C3]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CHECK: [[UV32:%[0-9]+]]:_(s32), [[UV33:%[0-9]+]]:_(s32), [[UV34:%[0-9]+]]:_(s32), [[UV35:%[0-9]+]]:_(s32), [[UV36:%[0-9]+]]:_(s32), [[UV37:%[0-9]+]]:_(s32), [[UV38:%[0-9]+]]:_(s32), [[UV39:%[0-9]+]]:_(s32), [[UV40:%[0-9]+]]:_(s32), [[UV41:%[0-9]+]]:_(s32), [[UV42:%[0-9]+]]:_(s32), [[UV43:%[0-9]+]]:_(s32), [[UV44:%[0-9]+]]:_(s32), [[UV45:%[0-9]+]]:_(s32), [[UV46:%[0-9]+]]:_(s32), [[UV47:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<16 x s32>)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV40]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV41]](s32)
- ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV40]], [[C]]
+ ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[UV41]], [[C]]
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C1]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV42]](s32)
- ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+ ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[UV42]], [[C]]
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C2]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV43]](s32)
- ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
+ ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[UV43]], [[C]]
; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C3]](s32)
; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CHECK: [[UV48:%[0-9]+]]:_(s32), [[UV49:%[0-9]+]]:_(s32), [[UV50:%[0-9]+]]:_(s32), [[UV51:%[0-9]+]]:_(s32), [[UV52:%[0-9]+]]:_(s32), [[UV53:%[0-9]+]]:_(s32), [[UV54:%[0-9]+]]:_(s32), [[UV55:%[0-9]+]]:_(s32), [[UV56:%[0-9]+]]:_(s32), [[UV57:%[0-9]+]]:_(s32), [[UV58:%[0-9]+]]:_(s32), [[UV59:%[0-9]+]]:_(s32), [[UV60:%[0-9]+]]:_(s32), [[UV61:%[0-9]+]]:_(s32), [[UV62:%[0-9]+]]:_(s32), [[UV63:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<16 x s32>)
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV60]](s32)
- ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C]]
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV61]](s32)
- ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C]]
+ ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV60]], [[C]]
+ ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[UV61]], [[C]]
; CHECK: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C1]](s32)
; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[UV62]](s32)
- ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C]]
+ ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[UV62]], [[C]]
; CHECK: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C2]](s32)
; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[UV63]](s32)
- ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C]]
+ ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[UV63]], [[C]]
; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C3]](s32)
; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -2054,54 +1852,22 @@ body: |
; CHECK: [[LSHR9:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC5]], [[C1]](s16)
; CHECK: [[LSHR10:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC6]], [[C1]](s16)
; CHECK: [[LSHR11:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC7]], [[C1]](s16)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
- ; CHECK: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[COPY1]], [[COPY2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[LSHR4]](s16)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[LSHR4]](s16)
- ; CHECK: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[COPY3]], [[COPY4]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
- ; CHECK: [[ADD2:%[0-9]+]]:_(s16) = G_ADD [[COPY5]], [[COPY6]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s16) = COPY [[LSHR5]](s16)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s16) = COPY [[LSHR5]](s16)
- ; CHECK: [[ADD3:%[0-9]+]]:_(s16) = G_ADD [[COPY7]], [[COPY8]]
- ; CHECK: [[COPY9:%[0-9]+]]:_(s16) = COPY [[TRUNC2]](s16)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s16) = COPY [[TRUNC2]](s16)
- ; CHECK: [[ADD4:%[0-9]+]]:_(s16) = G_ADD [[COPY9]], [[COPY10]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s16) = COPY [[LSHR6]](s16)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s16) = COPY [[LSHR6]](s16)
- ; CHECK: [[ADD5:%[0-9]+]]:_(s16) = G_ADD [[COPY11]], [[COPY12]]
- ; CHECK: [[COPY13:%[0-9]+]]:_(s16) = COPY [[TRUNC3]](s16)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s16) = COPY [[TRUNC3]](s16)
- ; CHECK: [[ADD6:%[0-9]+]]:_(s16) = G_ADD [[COPY13]], [[COPY14]]
- ; CHECK: [[COPY15:%[0-9]+]]:_(s16) = COPY [[LSHR7]](s16)
- ; CHECK: [[COPY16:%[0-9]+]]:_(s16) = COPY [[LSHR7]](s16)
- ; CHECK: [[ADD7:%[0-9]+]]:_(s16) = G_ADD [[COPY15]], [[COPY16]]
- ; CHECK: [[COPY17:%[0-9]+]]:_(s16) = COPY [[TRUNC4]](s16)
- ; CHECK: [[COPY18:%[0-9]+]]:_(s16) = COPY [[TRUNC4]](s16)
- ; CHECK: [[ADD8:%[0-9]+]]:_(s16) = G_ADD [[COPY17]], [[COPY18]]
- ; CHECK: [[COPY19:%[0-9]+]]:_(s16) = COPY [[LSHR8]](s16)
- ; CHECK: [[COPY20:%[0-9]+]]:_(s16) = COPY [[LSHR8]](s16)
- ; CHECK: [[ADD9:%[0-9]+]]:_(s16) = G_ADD [[COPY19]], [[COPY20]]
- ; CHECK: [[COPY21:%[0-9]+]]:_(s16) = COPY [[TRUNC5]](s16)
- ; CHECK: [[COPY22:%[0-9]+]]:_(s16) = COPY [[TRUNC5]](s16)
- ; CHECK: [[ADD10:%[0-9]+]]:_(s16) = G_ADD [[COPY21]], [[COPY22]]
- ; CHECK: [[COPY23:%[0-9]+]]:_(s16) = COPY [[LSHR9]](s16)
- ; CHECK: [[COPY24:%[0-9]+]]:_(s16) = COPY [[LSHR9]](s16)
- ; CHECK: [[ADD11:%[0-9]+]]:_(s16) = G_ADD [[COPY23]], [[COPY24]]
- ; CHECK: [[COPY25:%[0-9]+]]:_(s16) = COPY [[TRUNC6]](s16)
- ; CHECK: [[COPY26:%[0-9]+]]:_(s16) = COPY [[TRUNC6]](s16)
- ; CHECK: [[ADD12:%[0-9]+]]:_(s16) = G_ADD [[COPY25]], [[COPY26]]
- ; CHECK: [[COPY27:%[0-9]+]]:_(s16) = COPY [[LSHR10]](s16)
- ; CHECK: [[COPY28:%[0-9]+]]:_(s16) = COPY [[LSHR10]](s16)
- ; CHECK: [[ADD13:%[0-9]+]]:_(s16) = G_ADD [[COPY27]], [[COPY28]]
- ; CHECK: [[COPY29:%[0-9]+]]:_(s16) = COPY [[TRUNC7]](s16)
- ; CHECK: [[COPY30:%[0-9]+]]:_(s16) = COPY [[TRUNC7]](s16)
- ; CHECK: [[ADD14:%[0-9]+]]:_(s16) = G_ADD [[COPY29]], [[COPY30]]
- ; CHECK: [[COPY31:%[0-9]+]]:_(s16) = COPY [[LSHR11]](s16)
- ; CHECK: [[COPY32:%[0-9]+]]:_(s16) = COPY [[LSHR11]](s16)
- ; CHECK: [[ADD15:%[0-9]+]]:_(s16) = G_ADD [[COPY31]], [[COPY32]]
+ ; CHECK: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[TRUNC]]
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[LSHR4]], [[LSHR4]]
+ ; CHECK: [[ADD2:%[0-9]+]]:_(s16) = G_ADD [[TRUNC1]], [[TRUNC1]]
+ ; CHECK: [[ADD3:%[0-9]+]]:_(s16) = G_ADD [[LSHR5]], [[LSHR5]]
+ ; CHECK: [[ADD4:%[0-9]+]]:_(s16) = G_ADD [[TRUNC2]], [[TRUNC2]]
+ ; CHECK: [[ADD5:%[0-9]+]]:_(s16) = G_ADD [[LSHR6]], [[LSHR6]]
+ ; CHECK: [[ADD6:%[0-9]+]]:_(s16) = G_ADD [[TRUNC3]], [[TRUNC3]]
+ ; CHECK: [[ADD7:%[0-9]+]]:_(s16) = G_ADD [[LSHR7]], [[LSHR7]]
+ ; CHECK: [[ADD8:%[0-9]+]]:_(s16) = G_ADD [[TRUNC4]], [[TRUNC4]]
+ ; CHECK: [[ADD9:%[0-9]+]]:_(s16) = G_ADD [[LSHR8]], [[LSHR8]]
+ ; CHECK: [[ADD10:%[0-9]+]]:_(s16) = G_ADD [[TRUNC5]], [[TRUNC5]]
+ ; CHECK: [[ADD11:%[0-9]+]]:_(s16) = G_ADD [[LSHR9]], [[LSHR9]]
+ ; CHECK: [[ADD12:%[0-9]+]]:_(s16) = G_ADD [[TRUNC6]], [[TRUNC6]]
+ ; CHECK: [[ADD13:%[0-9]+]]:_(s16) = G_ADD [[LSHR10]], [[LSHR10]]
+ ; CHECK: [[ADD14:%[0-9]+]]:_(s16) = G_ADD [[TRUNC7]], [[TRUNC7]]
+ ; CHECK: [[ADD15:%[0-9]+]]:_(s16) = G_ADD [[LSHR11]], [[LSHR11]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD1]](s16)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD2]](s16)
@@ -2118,23 +1884,7 @@ body: |
; CHECK: [[ANYEXT13:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD13]](s16)
; CHECK: [[ANYEXT14:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD14]](s16)
; CHECK: [[ANYEXT15:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD15]](s16)
- ; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[COPY35:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[COPY36:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
- ; CHECK: [[COPY37:%[0-9]+]]:_(s32) = COPY [[ANYEXT4]](s32)
- ; CHECK: [[COPY38:%[0-9]+]]:_(s32) = COPY [[ANYEXT5]](s32)
- ; CHECK: [[COPY39:%[0-9]+]]:_(s32) = COPY [[ANYEXT6]](s32)
- ; CHECK: [[COPY40:%[0-9]+]]:_(s32) = COPY [[ANYEXT7]](s32)
- ; CHECK: [[COPY41:%[0-9]+]]:_(s32) = COPY [[ANYEXT8]](s32)
- ; CHECK: [[COPY42:%[0-9]+]]:_(s32) = COPY [[ANYEXT9]](s32)
- ; CHECK: [[COPY43:%[0-9]+]]:_(s32) = COPY [[ANYEXT10]](s32)
- ; CHECK: [[COPY44:%[0-9]+]]:_(s32) = COPY [[ANYEXT11]](s32)
- ; CHECK: [[COPY45:%[0-9]+]]:_(s32) = COPY [[ANYEXT12]](s32)
- ; CHECK: [[COPY46:%[0-9]+]]:_(s32) = COPY [[ANYEXT13]](s32)
- ; CHECK: [[COPY47:%[0-9]+]]:_(s32) = COPY [[ANYEXT14]](s32)
- ; CHECK: [[COPY48:%[0-9]+]]:_(s32) = COPY [[ANYEXT15]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[COPY33]](s32), [[COPY34]](s32), [[COPY35]](s32), [[COPY36]](s32), [[COPY37]](s32), [[COPY38]](s32), [[COPY39]](s32), [[COPY40]](s32), [[COPY41]](s32), [[COPY42]](s32), [[COPY43]](s32), [[COPY44]](s32), [[COPY45]](s32), [[COPY46]](s32), [[COPY47]](s32), [[COPY48]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32), [[ANYEXT3]](s32), [[ANYEXT4]](s32), [[ANYEXT5]](s32), [[ANYEXT6]](s32), [[ANYEXT7]](s32), [[ANYEXT8]](s32), [[ANYEXT9]](s32), [[ANYEXT10]](s32), [[ANYEXT11]](s32), [[ANYEXT12]](s32), [[ANYEXT13]](s32), [[ANYEXT14]](s32), [[ANYEXT15]](s32)
; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<16 x s32>)
%0:_(<8 x s16>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<16 x s8>) = G_BITCAST %0
@@ -2320,13 +2070,9 @@ body: |
; CHECK: [[LSHR3:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[LSHR4:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC2]], [[C1]](s16)
; CHECK: [[LSHR5:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC3]], [[C1]](s16)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR3]](s16)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR4]](s16)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR5]](s16)
; CHECK: [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[UV5]](s32)
@@ -2339,13 +2085,9 @@ body: |
; CHECK: [[LSHR9:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC5]], [[C1]](s16)
; CHECK: [[LSHR10:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC6]], [[C1]](s16)
; CHECK: [[LSHR11:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC7]], [[C1]](s16)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR8]](s16)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR9]](s16)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR10]](s16)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR11]](s16)
; CHECK: [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](s64)
; CHECK: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[UV7]](s32)
@@ -2358,96 +2100,68 @@ body: |
; CHECK: [[LSHR15:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC9]], [[C1]](s16)
; CHECK: [[LSHR16:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC10]], [[C1]](s16)
; CHECK: [[LSHR17:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC11]], [[C1]](s16)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
; CHECK: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR14]](s16)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
; CHECK: [[ANYEXT9:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR15]](s16)
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV8]](s32)
; CHECK: [[ANYEXT10:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR16]](s16)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
; CHECK: [[ANYEXT11:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR17]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C2]]
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C2]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C2]]
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C2]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C2]]
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C2]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[C2]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C2]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C2]]
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C2]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C2]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CHECK: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C2]]
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[ANYEXT4]](s32)
- ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C2]]
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C2]]
+ ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C2]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
- ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C2]]
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[ANYEXT5]](s32)
- ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C2]]
+ ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C2]]
+ ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C2]]
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
- ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
- ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C2]]
- ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[ANYEXT6]](s32)
- ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C2]]
+ ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV6]], [[C2]]
+ ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[C2]]
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL6]]
; CHECK: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR6]](s32)
- ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
- ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C2]]
- ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[ANYEXT7]](s32)
- ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C2]]
+ ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C2]]
+ ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[ANYEXT7]], [[C2]]
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND14]], [[SHL7]]
; CHECK: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR7]](s32)
- ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C2]]
- ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[ANYEXT8]](s32)
- ; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C2]]
+ ; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[UV7]], [[C2]]
+ ; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[ANYEXT8]], [[C2]]
; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C]](s32)
; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL8]]
; CHECK: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR8]](s32)
- ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; CHECK: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C2]]
- ; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[ANYEXT9]](s32)
- ; CHECK: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C2]]
+ ; CHECK: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C2]]
+ ; CHECK: [[AND19:%[0-9]+]]:_(s32) = G_AND [[ANYEXT9]], [[C2]]
; CHECK: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C]](s32)
; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND18]], [[SHL9]]
; CHECK: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR9]](s32)
- ; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
- ; CHECK: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY33]], [[C2]]
- ; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[ANYEXT10]](s32)
- ; CHECK: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY34]], [[C2]]
+ ; CHECK: [[AND20:%[0-9]+]]:_(s32) = G_AND [[UV8]], [[C2]]
+ ; CHECK: [[AND21:%[0-9]+]]:_(s32) = G_AND [[ANYEXT10]], [[C2]]
; CHECK: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C]](s32)
; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL10]]
; CHECK: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR10]](s32)
- ; CHECK: [[COPY35:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; CHECK: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY35]], [[C2]]
- ; CHECK: [[COPY36:%[0-9]+]]:_(s32) = COPY [[ANYEXT11]](s32)
- ; CHECK: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY36]], [[C2]]
+ ; CHECK: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C2]]
+ ; CHECK: [[AND23:%[0-9]+]]:_(s32) = G_AND [[ANYEXT11]], [[C2]]
; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C]](s32)
; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[AND22]], [[SHL11]]
; CHECK: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR11]](s32)
@@ -2487,29 +2201,21 @@ body: |
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
- ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
- ; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C2]](s16)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[TRUNC2]](s16)
- ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C1]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[TRUNC3]](s16)
- ; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY5]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C2]](s16)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL1]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s16) = COPY [[TRUNC4]](s16)
- ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C1]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s16) = COPY [[TRUNC5]](s16)
- ; CHECK: [[AND5:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C1]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC5]], [[C1]]
; CHECK: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C2]](s16)
; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL2]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s16) = COPY [[TRUNC6]](s16)
- ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C1]]
- ; CHECK: [[COPY9:%[0-9]+]]:_(s16) = COPY [[TRUNC7]](s16)
- ; CHECK: [[AND7:%[0-9]+]]:_(s16) = G_AND [[COPY9]], [[C1]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C1]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s16) = G_AND [[TRUNC7]], [[C1]]
; CHECK: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[AND7]], [[C2]](s16)
; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[SHL3]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -2539,28 +2245,20 @@ body: |
; CHECK: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST7]](s32)
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
; CHECK: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR7]](s32)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s16) = COPY [[TRUNC8]](s16)
- ; CHECK: [[AND8:%[0-9]+]]:_(s16) = G_AND [[COPY10]], [[C1]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s16) = COPY [[TRUNC9]](s16)
- ; CHECK: [[AND9:%[0-9]+]]:_(s16) = G_AND [[COPY11]], [[C1]]
+ ; CHECK: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C1]]
+ ; CHECK: [[AND9:%[0-9]+]]:_(s16) = G_AND [[TRUNC9]], [[C1]]
; CHECK: [[SHL6:%[0-9]+]]:_(s16) = G_SHL [[AND9]], [[C2]](s16)
; CHECK: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[SHL6]]
- ; CHECK: [[COPY12:%[0-9]+]]:_(s16) = COPY [[TRUNC10]](s16)
- ; CHECK: [[AND10:%[0-9]+]]:_(s16) = G_AND [[COPY12]], [[C1]]
- ; CHECK: [[COPY13:%[0-9]+]]:_(s16) = COPY [[TRUNC11]](s16)
- ; CHECK: [[AND11:%[0-9]+]]:_(s16) = G_AND [[COPY13]], [[C1]]
+ ; CHECK: [[AND10:%[0-9]+]]:_(s16) = G_AND [[TRUNC10]], [[C1]]
+ ; CHECK: [[AND11:%[0-9]+]]:_(s16) = G_AND [[TRUNC11]], [[C1]]
; CHECK: [[SHL7:%[0-9]+]]:_(s16) = G_SHL [[AND11]], [[C2]](s16)
; CHECK: [[OR7:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[SHL7]]
- ; CHECK: [[COPY14:%[0-9]+]]:_(s16) = COPY [[TRUNC12]](s16)
- ; CHECK: [[AND12:%[0-9]+]]:_(s16) = G_AND [[COPY14]], [[C1]]
- ; CHECK: [[COPY15:%[0-9]+]]:_(s16) = COPY [[TRUNC13]](s16)
- ; CHECK: [[AND13:%[0-9]+]]:_(s16) = G_AND [[COPY15]], [[C1]]
+ ; CHECK: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC12]], [[C1]]
+ ; CHECK: [[AND13:%[0-9]+]]:_(s16) = G_AND [[TRUNC13]], [[C1]]
; CHECK: [[SHL8:%[0-9]+]]:_(s16) = G_SHL [[AND13]], [[C2]](s16)
; CHECK: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[SHL8]]
- ; CHECK: [[COPY16:%[0-9]+]]:_(s16) = COPY [[TRUNC14]](s16)
- ; CHECK: [[AND14:%[0-9]+]]:_(s16) = G_AND [[COPY16]], [[C1]]
- ; CHECK: [[COPY17:%[0-9]+]]:_(s16) = COPY [[TRUNC15]](s16)
- ; CHECK: [[AND15:%[0-9]+]]:_(s16) = G_AND [[COPY17]], [[C1]]
+ ; CHECK: [[AND14:%[0-9]+]]:_(s16) = G_AND [[TRUNC14]], [[C1]]
+ ; CHECK: [[AND15:%[0-9]+]]:_(s16) = G_AND [[TRUNC15]], [[C1]]
; CHECK: [[SHL9:%[0-9]+]]:_(s16) = G_SHL [[AND15]], [[C2]](s16)
; CHECK: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[SHL9]]
; CHECK: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
@@ -2589,28 +2287,20 @@ body: |
; CHECK: [[TRUNC22:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST11]](s32)
; CHECK: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST11]], [[C]](s32)
; CHECK: [[TRUNC23:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR11]](s32)
- ; CHECK: [[COPY18:%[0-9]+]]:_(s16) = COPY [[TRUNC16]](s16)
- ; CHECK: [[AND16:%[0-9]+]]:_(s16) = G_AND [[COPY18]], [[C1]]
- ; CHECK: [[COPY19:%[0-9]+]]:_(s16) = COPY [[TRUNC17]](s16)
- ; CHECK: [[AND17:%[0-9]+]]:_(s16) = G_AND [[COPY19]], [[C1]]
+ ; CHECK: [[AND16:%[0-9]+]]:_(s16) = G_AND [[TRUNC16]], [[C1]]
+ ; CHECK: [[AND17:%[0-9]+]]:_(s16) = G_AND [[TRUNC17]], [[C1]]
; CHECK: [[SHL12:%[0-9]+]]:_(s16) = G_SHL [[AND17]], [[C2]](s16)
; CHECK: [[OR12:%[0-9]+]]:_(s16) = G_OR [[AND16]], [[SHL12]]
- ; CHECK: [[COPY20:%[0-9]+]]:_(s16) = COPY [[TRUNC18]](s16)
- ; CHECK: [[AND18:%[0-9]+]]:_(s16) = G_AND [[COPY20]], [[C1]]
- ; CHECK: [[COPY21:%[0-9]+]]:_(s16) = COPY [[TRUNC19]](s16)
- ; CHECK: [[AND19:%[0-9]+]]:_(s16) = G_AND [[COPY21]], [[C1]]
+ ; CHECK: [[AND18:%[0-9]+]]:_(s16) = G_AND [[TRUNC18]], [[C1]]
+ ; CHECK: [[AND19:%[0-9]+]]:_(s16) = G_AND [[TRUNC19]], [[C1]]
; CHECK: [[SHL13:%[0-9]+]]:_(s16) = G_SHL [[AND19]], [[C2]](s16)
; CHECK: [[OR13:%[0-9]+]]:_(s16) = G_OR [[AND18]], [[SHL13]]
- ; CHECK: [[COPY22:%[0-9]+]]:_(s16) = COPY [[TRUNC20]](s16)
- ; CHECK: [[AND20:%[0-9]+]]:_(s16) = G_AND [[COPY22]], [[C1]]
- ; CHECK: [[COPY23:%[0-9]+]]:_(s16) = COPY [[TRUNC21]](s16)
- ; CHECK: [[AND21:%[0-9]+]]:_(s16) = G_AND [[COPY23]], [[C1]]
+ ; CHECK: [[AND20:%[0-9]+]]:_(s16) = G_AND [[TRUNC20]], [[C1]]
+ ; CHECK: [[AND21:%[0-9]+]]:_(s16) = G_AND [[TRUNC21]], [[C1]]
; CHECK: [[SHL14:%[0-9]+]]:_(s16) = G_SHL [[AND21]], [[C2]](s16)
; CHECK: [[OR14:%[0-9]+]]:_(s16) = G_OR [[AND20]], [[SHL14]]
- ; CHECK: [[COPY24:%[0-9]+]]:_(s16) = COPY [[TRUNC22]](s16)
- ; CHECK: [[AND22:%[0-9]+]]:_(s16) = G_AND [[COPY24]], [[C1]]
- ; CHECK: [[COPY25:%[0-9]+]]:_(s16) = COPY [[TRUNC23]](s16)
- ; CHECK: [[AND23:%[0-9]+]]:_(s16) = G_AND [[COPY25]], [[C1]]
+ ; CHECK: [[AND22:%[0-9]+]]:_(s16) = G_AND [[TRUNC22]], [[C1]]
+ ; CHECK: [[AND23:%[0-9]+]]:_(s16) = G_AND [[TRUNC23]], [[C1]]
; CHECK: [[SHL15:%[0-9]+]]:_(s16) = G_SHL [[AND23]], [[C2]](s16)
; CHECK: [[OR15:%[0-9]+]]:_(s16) = G_OR [[AND22]], [[SHL15]]
; CHECK: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[OR12]](s16)
@@ -2655,30 +2345,14 @@ body: |
; CHECK: [[LSHR3:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[LSHR4:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC2]], [[C1]](s16)
; CHECK: [[LSHR5:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC3]], [[C1]](s16)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
- ; CHECK: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[COPY1]], [[COPY2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[LSHR2]](s16)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[LSHR2]](s16)
- ; CHECK: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[COPY3]], [[COPY4]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
- ; CHECK: [[ADD2:%[0-9]+]]:_(s16) = G_ADD [[COPY5]], [[COPY6]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s16) = COPY [[LSHR3]](s16)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s16) = COPY [[LSHR3]](s16)
- ; CHECK: [[ADD3:%[0-9]+]]:_(s16) = G_ADD [[COPY7]], [[COPY8]]
- ; CHECK: [[COPY9:%[0-9]+]]:_(s16) = COPY [[TRUNC2]](s16)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s16) = COPY [[TRUNC2]](s16)
- ; CHECK: [[ADD4:%[0-9]+]]:_(s16) = G_ADD [[COPY9]], [[COPY10]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s16) = COPY [[LSHR4]](s16)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s16) = COPY [[LSHR4]](s16)
- ; CHECK: [[ADD5:%[0-9]+]]:_(s16) = G_ADD [[COPY11]], [[COPY12]]
- ; CHECK: [[COPY13:%[0-9]+]]:_(s16) = COPY [[TRUNC3]](s16)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s16) = COPY [[TRUNC3]](s16)
- ; CHECK: [[ADD6:%[0-9]+]]:_(s16) = G_ADD [[COPY13]], [[COPY14]]
- ; CHECK: [[COPY15:%[0-9]+]]:_(s16) = COPY [[LSHR5]](s16)
- ; CHECK: [[COPY16:%[0-9]+]]:_(s16) = COPY [[LSHR5]](s16)
- ; CHECK: [[ADD7:%[0-9]+]]:_(s16) = G_ADD [[COPY15]], [[COPY16]]
+ ; CHECK: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[TRUNC]], [[TRUNC]]
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[LSHR2]], [[LSHR2]]
+ ; CHECK: [[ADD2:%[0-9]+]]:_(s16) = G_ADD [[TRUNC1]], [[TRUNC1]]
+ ; CHECK: [[ADD3:%[0-9]+]]:_(s16) = G_ADD [[LSHR3]], [[LSHR3]]
+ ; CHECK: [[ADD4:%[0-9]+]]:_(s16) = G_ADD [[TRUNC2]], [[TRUNC2]]
+ ; CHECK: [[ADD5:%[0-9]+]]:_(s16) = G_ADD [[LSHR4]], [[LSHR4]]
+ ; CHECK: [[ADD6:%[0-9]+]]:_(s16) = G_ADD [[TRUNC3]], [[TRUNC3]]
+ ; CHECK: [[ADD7:%[0-9]+]]:_(s16) = G_ADD [[LSHR5]], [[LSHR5]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s16)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD1]](s16)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD2]](s16)
@@ -2688,31 +2362,23 @@ body: |
; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD6]](s16)
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD7]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C2]]
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C2]]
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C2]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C2]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[ANYEXT4]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C2]]
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[ANYEXT5]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C2]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C2]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C2]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[ANYEXT6]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C2]]
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[ANYEXT7]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C2]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[C2]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT7]], [[C2]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
@@ -2740,10 +2406,8 @@ body: |
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
- ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY1]], [[C1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
- ; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C2]](s16)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
@@ -2752,10 +2416,8 @@ body: |
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST1]](s32)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[TRUNC2]](s16)
- ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[TRUNC3]](s16)
- ; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C2]](s16)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[UV8:%[0-9]+]]:_(<2 x s16>), [[UV9:%[0-9]+]]:_(<2 x s16>), [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
@@ -2763,10 +2425,8 @@ body: |
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST2]](s32)
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[TRUNC4]](s16)
- ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY5]], [[C1]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s16) = COPY [[TRUNC5]](s16)
- ; CHECK: [[AND5:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C1]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC5]], [[C1]]
; CHECK: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C2]](s16)
; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>), [[UV14:%[0-9]+]]:_(<2 x s16>), [[UV15:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
@@ -2774,10 +2434,8 @@ body: |
; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST3]](s32)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s16) = COPY [[TRUNC6]](s16)
- ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C1]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s16) = COPY [[TRUNC7]](s16)
- ; CHECK: [[AND7:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C1]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C1]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s16) = G_AND [[TRUNC7]], [[C1]]
; CHECK: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[AND7]], [[C2]](s16)
; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[SHL3]]
; CHECK: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[OR]], [[OR]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
index c365bdcbfab75..a5aab05db0219 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
@@ -9,12 +9,10 @@ body: |
liveins: $vgpr0
; CHECK-LABEL: name: bitreverse_s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY1]]
+ ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
%2:_(s8) = G_BITREVERSE %1
@@ -30,12 +28,10 @@ body: |
liveins: $vgpr0
; CHECK-LABEL: name: bitreverse_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY1]]
+ ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s16) = G_BITREVERSE %1
@@ -51,12 +47,10 @@ body: |
liveins: $vgpr0
; CHECK-LABEL: name: bitreverse_s24
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY1]]
+ ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s24) = G_TRUNC %0
%2:_(s24) = G_BITREVERSE %1
@@ -90,17 +84,13 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY1]]
+ ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[BITCAST]]
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE]], [[C]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[BITREVERSE1:%[0-9]+]]:_(s32) = G_BITREVERSE [[COPY2]]
+ ; CHECK: [[BITREVERSE1:%[0-9]+]]:_(s32) = G_BITREVERSE [[LSHR]]
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITREVERSE1]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
index 61a08e5e73944..74322df42f411 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
@@ -13,19 +13,12 @@ body: |
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[AND]](s32)
- ; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; GFX7: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32)
- ; GFX7: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX7: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; GFX7: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[COPY6]]
- ; GFX7: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; GFX7: $vgpr0 = COPY [[COPY7]](s32)
+ ; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
+ ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
+ ; GFX7: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
+ ; GFX7: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
+ ; GFX7: $vgpr0 = COPY [[OR]](s32)
; GFX8-LABEL: name: bswap_s8
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
@@ -50,14 +43,12 @@ body: |
; GFX7-LABEL: name: bswap_s16
; GFX7: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; GFX7: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
- ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX7: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
+ ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
+ ; GFX7: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; GFX7: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX7: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC1]], [[TRUNC]]
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -86,27 +77,18 @@ body: |
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[AND]](s32)
- ; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; GFX7: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32)
- ; GFX7: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX7: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; GFX7: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[COPY6]]
- ; GFX7: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; GFX7: $vgpr0 = COPY [[COPY7]](s32)
+ ; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
+ ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
+ ; GFX7: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
+ ; GFX7: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
+ ; GFX7: $vgpr0 = COPY [[OR]](s32)
; GFX8-LABEL: name: bswap_s24
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
+ ; GFX8: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s32)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: $vgpr0 = COPY [[COPY2]](s32)
+ ; GFX8: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s24) = G_TRUNC %0
%2:_(s24) = G_BSWAP %1
@@ -145,24 +127,20 @@ body: |
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX7: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32)
+ ; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C1]](s32)
; GFX7: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
- ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
- ; GFX7: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
+ ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
+ ; GFX7: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; GFX7: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; GFX7: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC1]], [[TRUNC]]
- ; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX7: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX7: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[COPY4]](s32)
+ ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX7: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[COPY2]](s32)
; GFX7: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
- ; GFX7: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX7: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
- ; GFX7: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY6]](s32)
+ ; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX7: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; GFX7: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
; GFX7: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC3]], [[TRUNC2]]
; GFX7: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -191,34 +169,28 @@ body: |
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; GFX7: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
- ; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX7: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX7: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY4]](s32)
+ ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
+ ; GFX7: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY3]](s32)
; GFX7: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX7: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC1]], [[TRUNC]]
- ; GFX7: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX7: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX7: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[COPY6]](s32)
+ ; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX7: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY4]](s32)
; GFX7: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
- ; GFX7: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX7: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; GFX7: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY8]](s32)
+ ; GFX7: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; GFX7: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY5]](s32)
; GFX7: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; GFX7: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC3]], [[TRUNC2]]
- ; GFX7: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX7: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX7: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY11]], [[COPY10]](s32)
+ ; GFX7: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX7: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[COPY6]](s32)
; GFX7: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
- ; GFX7: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX7: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
- ; GFX7: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY12]](s32)
+ ; GFX7: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX7: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY7]](s32)
; GFX7: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
; GFX7: [[OR2:%[0-9]+]]:_(s16) = G_OR [[TRUNC5]], [[TRUNC4]]
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -232,16 +204,13 @@ body: |
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
@@ -253,12 +222,9 @@ body: |
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C1]](s32)
; GFX8: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[BSWAP1]](<2 x s16>)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; GFX8: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX8: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX8: $vgpr0 = COPY [[COPY6]](s32)
- ; GFX8: $vgpr1 = COPY [[COPY7]](s32)
- ; GFX8: $vgpr2 = COPY [[COPY8]](s32)
+ ; GFX8: $vgpr0 = COPY [[BITCAST2]](s32)
+ ; GFX8: $vgpr1 = COPY [[LSHR]](s32)
+ ; GFX8: $vgpr2 = COPY [[BITCAST3]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2
@@ -292,44 +258,36 @@ body: |
; GFX7: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX7: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32)
+ ; GFX7: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C1]](s32)
; GFX7: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
- ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; GFX7: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
- ; GFX7: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
+ ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
+ ; GFX7: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; GFX7: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
; GFX7: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC1]], [[TRUNC]]
- ; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX7: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX7: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[COPY4]](s32)
+ ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX7: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[COPY2]](s32)
; GFX7: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
- ; GFX7: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX7: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
- ; GFX7: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY6]](s32)
+ ; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX7: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; GFX7: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
; GFX7: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC3]], [[TRUNC2]]
- ; GFX7: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX7: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX7: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[COPY8]](s32)
+ ; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX7: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[COPY4]](s32)
; GFX7: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
- ; GFX7: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX7: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C2]]
- ; GFX7: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY10]](s32)
+ ; GFX7: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
+ ; GFX7: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
; GFX7: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](s32)
; GFX7: [[OR2:%[0-9]+]]:_(s16) = G_OR [[TRUNC5]], [[TRUNC4]]
- ; GFX7: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX7: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX7: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY13]], [[COPY12]](s32)
+ ; GFX7: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX7: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[COPY6]](s32)
; GFX7: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
- ; GFX7: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX7: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX7: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C2]]
- ; GFX7: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY14]](s32)
+ ; GFX7: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX7: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; GFX7: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY7]](s32)
; GFX7: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](s32)
; GFX7: [[OR3:%[0-9]+]]:_(s16) = G_OR [[TRUNC7]], [[TRUNC6]]
; GFX7: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
index dd147ae14964e..8b23d471c087f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
@@ -14,10 +14,8 @@ body: |
; GFX78: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX78: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX78: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX78: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX78: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX78: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX78: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX78: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -26,9 +24,7 @@ body: |
; GFX9-LABEL: name: build_vector_v2s16
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
; GFX9: S_NOP 0, implicit [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -51,25 +47,19 @@ body: |
; GFX78: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX78: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX78: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX78: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
- ; GFX78: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX78: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX78: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX78: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX78: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX78: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
- ; GFX78: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+ ; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX78: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; GFX78: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX78: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX78: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX78: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
- ; GFX78: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX78: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
+ ; GFX78: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX78: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX78: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; GFX78: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX78: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -81,15 +71,9 @@ body: |
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: S_NOP 0, implicit [[CONCAT_VECTORS]](<6 x s16>)
%0:_(s32) = COPY $vgpr0
@@ -115,18 +99,14 @@ body: |
; GFX78: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX78: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX78: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX78: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
- ; GFX78: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX78: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX78: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX78: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX78: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX78: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
- ; GFX78: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
+ ; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX78: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; GFX78: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX78: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -137,12 +117,8 @@ body: |
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: S_NOP 0, implicit [[CONCAT_VECTORS]](<4 x s16>)
%0:_(s32) = COPY $vgpr0
@@ -172,39 +148,29 @@ body: |
; GFX78: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX78: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX78: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX78: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
- ; GFX78: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+ ; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX78: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX78: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX78: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX78: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX78: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
- ; GFX78: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
+ ; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX78: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; GFX78: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX78: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX78: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; GFX78: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
- ; GFX78: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX78: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+ ; GFX78: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX78: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX78: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; GFX78: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX78: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; GFX78: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX78: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
- ; GFX78: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX78: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
+ ; GFX78: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX78: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX78: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C1]](s32)
; GFX78: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX78: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
- ; GFX78: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX78: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C]]
- ; GFX78: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; GFX78: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C]]
+ ; GFX78: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX78: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX78: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C1]](s32)
; GFX78: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; GFX78: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
@@ -218,21 +184,11 @@ body: |
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<10 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>), [[BUILD_VECTOR_TRUNC4]](<2 x s16>)
; GFX9: S_NOP 0, implicit [[CONCAT_VECTORS]](<10 x s16>)
%0:_(s32) = COPY $vgpr0
@@ -267,53 +223,39 @@ body: |
; GFX78: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX78: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX78: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX78: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
- ; GFX78: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
+ ; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX78: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX78: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX78: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX78: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX78: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
- ; GFX78: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+ ; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX78: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; GFX78: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX78: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX78: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; GFX78: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
- ; GFX78: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; GFX78: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
+ ; GFX78: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX78: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; GFX78: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; GFX78: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX78: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; GFX78: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
- ; GFX78: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C]]
- ; GFX78: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX78: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C]]
+ ; GFX78: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+ ; GFX78: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX78: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C1]](s32)
; GFX78: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX78: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
- ; GFX78: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX78: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C]]
- ; GFX78: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX78: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C]]
+ ; GFX78: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX78: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX78: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C1]](s32)
; GFX78: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; GFX78: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; GFX78: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX78: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C]]
- ; GFX78: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; GFX78: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C]]
+ ; GFX78: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX78: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; GFX78: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C1]](s32)
; GFX78: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; GFX78: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
- ; GFX78: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; GFX78: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C]]
- ; GFX78: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
- ; GFX78: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C]]
+ ; GFX78: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; GFX78: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
; GFX78: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C1]](s32)
; GFX78: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL6]]
; GFX78: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR6]](s32)
@@ -329,27 +271,13 @@ body: |
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX9: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<14 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>), [[BUILD_VECTOR_TRUNC4]](<2 x s16>), [[BUILD_VECTOR_TRUNC5]](<2 x s16>), [[BUILD_VECTOR_TRUNC6]](<2 x s16>)
; GFX9: S_NOP 0, implicit [[CONCAT_VECTORS]](<14 x s16>)
%0:_(s32) = COPY $vgpr0
@@ -387,32 +315,24 @@ body: |
; GFX78: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX78: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
; GFX78: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX78: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
- ; GFX78: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
+ ; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX78: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX78: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX78: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX78: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX78: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
- ; GFX78: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+ ; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX78: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; GFX78: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX78: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX78: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; GFX78: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
- ; GFX78: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; GFX78: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C]]
+ ; GFX78: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX78: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; GFX78: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; GFX78: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX78: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; GFX78: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
- ; GFX78: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C]]
- ; GFX78: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
- ; GFX78: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C]]
+ ; GFX78: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+ ; GFX78: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
; GFX78: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C1]](s32)
; GFX78: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX78: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
@@ -427,18 +347,10 @@ body: |
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>)
; GFX9: S_NOP 0, implicit [[CONCAT_VECTORS]](<8 x s16>)
%0:_(s32) = COPY $vgpr0
@@ -485,60 +397,44 @@ body: |
; GFX78: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr14
; GFX78: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr15
; GFX78: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX78: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C]]
- ; GFX78: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C]]
+ ; GFX78: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX78: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX78: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX78: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX78: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX78: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX78: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C]]
- ; GFX78: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C]]
+ ; GFX78: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX78: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX78: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; GFX78: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX78: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX78: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; GFX78: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C]]
- ; GFX78: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; GFX78: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C]]
+ ; GFX78: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX78: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; GFX78: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; GFX78: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX78: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; GFX78: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
- ; GFX78: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C]]
- ; GFX78: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
- ; GFX78: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C]]
+ ; GFX78: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+ ; GFX78: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
; GFX78: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C1]](s32)
; GFX78: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX78: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
- ; GFX78: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
- ; GFX78: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C]]
- ; GFX78: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX78: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C]]
+ ; GFX78: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
+ ; GFX78: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
; GFX78: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C1]](s32)
; GFX78: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; GFX78: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; GFX78: [[COPY26:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX78: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C]]
- ; GFX78: [[COPY27:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
- ; GFX78: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C]]
+ ; GFX78: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+ ; GFX78: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
; GFX78: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C1]](s32)
; GFX78: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; GFX78: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
- ; GFX78: [[COPY28:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX78: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C]]
- ; GFX78: [[COPY29:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX78: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C]]
+ ; GFX78: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
+ ; GFX78: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C]]
; GFX78: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C1]](s32)
; GFX78: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL6]]
; GFX78: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR6]](s32)
- ; GFX78: [[COPY30:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX78: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C]]
- ; GFX78: [[COPY31:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX78: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C]]
+ ; GFX78: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C]]
+ ; GFX78: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C]]
; GFX78: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C1]](s32)
; GFX78: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND14]], [[SHL7]]
; GFX78: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR7]](s32)
@@ -561,30 +457,14 @@ body: |
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr13
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr14
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr15
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
- ; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
- ; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
- ; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
- ; GFX9: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
- ; GFX9: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY24]](s32), [[COPY25]](s32)
- ; GFX9: [[COPY26:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX9: [[COPY27:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY26]](s32), [[COPY27]](s32)
- ; GFX9: [[COPY28:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY29:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY28]](s32), [[COPY29]](s32)
- ; GFX9: [[COPY30:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[COPY31:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY30]](s32), [[COPY31]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>), [[BUILD_VECTOR_TRUNC4]](<2 x s16>), [[BUILD_VECTOR_TRUNC5]](<2 x s16>), [[BUILD_VECTOR_TRUNC6]](<2 x s16>), [[BUILD_VECTOR_TRUNC7]](<2 x s16>)
; GFX9: S_NOP 0, implicit [[CONCAT_VECTORS]](<16 x s16>)
%0:_(s32) = COPY $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
index 8a61d45d656c0..aa305d0324aab 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
@@ -233,24 +233,18 @@ body: |
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
index 32dff5efe5cf7..e60b213d6e09e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
@@ -60,8 +60,7 @@ body: |
; CHECK-LABEL: name: test_constant_s7
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+ ; CHECK: $vgpr0 = COPY [[C]](s32)
%0:_(s7) = G_CONSTANT i7 5
%1:_(s32) = G_ANYEXT %0
$vgpr0 = COPY %1
@@ -74,8 +73,7 @@ body: |
; CHECK-LABEL: name: test_constant_s8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+ ; CHECK: $vgpr0 = COPY [[C]](s32)
%0:_(s8) = G_CONSTANT i8 5
%1:_(s32) = G_ANYEXT %0
$vgpr0 = COPY %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
index 8ebe61b32561f..ef2e2302f55fd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
@@ -57,8 +57,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTLZ_ZERO_UNDEF]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[CTLZ_ZERO_UNDEF]], [[C]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_CTLZ_ZERO_UNDEF %0
@@ -75,14 +74,12 @@ body: |
; CHECK-LABEL: name: ctlz_zero_undef_s16_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ_ZERO_UNDEF]], [[C1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
@@ -139,20 +136,16 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s32)
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ_ZERO_UNDEF]], [[C]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[CTLZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND1]](s32)
; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[CTLZ_ZERO_UNDEF1]], [[C]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -172,14 +165,12 @@ body: |
; CHECK-LABEL: name: ctlz_zero_undef_s7_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ_ZERO_UNDEF]], [[C1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
@@ -198,8 +189,7 @@ body: |
; CHECK-LABEL: name: ctlz_zero_undef_s33_s33
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s64)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTLZ_ZERO_UNDEF]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
index ffc0790eda9b9..00b20170c42fd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
@@ -65,8 +65,7 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UMIN]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UMIN]], [[C1]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_CTLZ %0
@@ -83,16 +82,14 @@ body: |
; CHECK-LABEL: name: ctlz_s16_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMIN]], [[C2]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
@@ -155,23 +152,19 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C2]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMIN]], [[C]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[AMDGPU_FFBH_U32_1:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND1]](s32)
; CHECK: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_1]], [[C2]]
; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UMIN1]], [[C]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -191,16 +184,14 @@ body: |
; CHECK-LABEL: name: ctlz_s7_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMIN]], [[C2]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
@@ -219,8 +210,7 @@ body: |
; CHECK-LABEL: name: ctlz_s33_s33
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; CHECK: [[AMDGPU_FFBH_U32_:%[0-9]+]]:_(s32) = G_AMDGPU_FFBH_U32 [[AND]](s64)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[C1]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
index 3147ed1bf4f12..8abcac159f191 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
@@ -57,8 +57,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[CTPOP]], [[C]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_CTPOP %0
@@ -75,12 +74,10 @@ body: |
; CHECK-LABEL: name: ctpop_s16_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
@@ -137,18 +134,14 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[CTPOP1:%[0-9]+]]:_(s32) = G_CTPOP [[AND1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[CTPOP1]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTPOP1]](s32)
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -168,12 +161,10 @@ body: |
; CHECK-LABEL: name: ctpop_s7_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
@@ -192,16 +183,12 @@ body: |
; CHECK-LABEL: name: ctpop_s33_s33
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; CHECK: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s64)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTPOP]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ZEXT]](s64)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C1]](s64)
- ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
- ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ZEXT]], [[C1]]
+ ; CHECK: $vgpr0_vgpr1 = COPY [[AND1]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0
%2:_(s33) = G_CTPOP %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir
index 91de40f1f29f9..d6bb4db624e5a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir
@@ -57,8 +57,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[CTTZ_ZERO_UNDEF]], [[C]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_CTTZ_ZERO_UNDEF %0
@@ -74,12 +73,10 @@ body: |
liveins: $vgpr0
; CHECK-LABEL: name: cttz_zero_undef_s16_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY1]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
@@ -135,17 +132,13 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY1]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY3]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF1]](s32)
+ ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[BITCAST]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[LSHR]](s32)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF1]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -164,12 +157,10 @@ body: |
; CHECK-LABEL: name: cttz_zero_undef_s7_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY1]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
@@ -187,15 +178,11 @@ body: |
; CHECK-LABEL: name: cttz_zero_undef_s33_s33
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY1]](s64)
+ ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s64)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ZEXT]](s64)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C]](s64)
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
- ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ZEXT]], [[C]]
+ ; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0
%2:_(s33) = G_CTTZ_ZERO_UNDEF %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
index 4776996b43e81..dec1e4b43d623 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
@@ -65,8 +65,7 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AMDGPU_FFBL_B32_]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UMIN]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UMIN]], [[C1]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_CTTZ %0
@@ -82,14 +81,12 @@ body: |
liveins: $vgpr0
; CHECK-LABEL: name: cttz_s16_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[C]]
+ ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]]
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
@@ -151,20 +148,16 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[C1]]
+ ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[BITCAST]], [[C1]]
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY3]], [[C1]]
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[C1]]
; CHECK: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF1]](s32)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -183,14 +176,12 @@ body: |
; CHECK-LABEL: name: cttz_s7_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[C]]
+ ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]]
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
@@ -208,17 +199,13 @@ body: |
; CHECK-LABEL: name: cttz_s33_s33
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934592
- ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY1]], [[C]]
+ ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[C]]
; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s64)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTTZ_ZERO_UNDEF]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ZEXT]](s64)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C1]](s64)
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
- ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ZEXT]], [[C1]]
+ ; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0
%2:_(s33) = G_CTTZ %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
index 88a0437183d30..29876d47680f2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
@@ -205,14 +205,12 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_0_v2i8_i32
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
- ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 8
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 8
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<2 x s32>), 0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
%0:_(<2 x s8>) = G_IMPLICIT_DEF
%1:_(s32) = G_CONSTANT i32 0
%2:_(s8) = G_EXTRACT_VECTOR_ELT %0, %1
@@ -231,8 +229,7 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[DEF]](<2 x s16>)
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(<2 x s16>) = G_IMPLICIT_DEF
%1:_(s32) = G_CONSTANT i32 0
%2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
@@ -248,14 +245,12 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i32
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
- ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 1
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 1
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<2 x s32>), 0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
%0:_(<2 x s1>) = G_IMPLICIT_DEF
%1:_(s32) = G_CONSTANT i32 0
%2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1
@@ -272,14 +267,12 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_0_v2i1_i1
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
- ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 1
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 1
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<2 x s32>), 0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
%0:_(<2 x s1>) = G_IMPLICIT_DEF
%1:_(s1) = G_CONSTANT i1 false
%2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1
@@ -303,16 +296,11 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 8
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 8
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<2 x s32>), [[COPY1]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY6]](s32)
+ ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0
@@ -338,16 +326,11 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 8
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 8
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<2 x s32>), 0
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY6]](s32)
+ ; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0
@@ -374,16 +357,11 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 8
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 8
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<2 x s32>), 32
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY6]](s32)
+ ; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0
@@ -418,22 +396,13 @@ body: |
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C5]](s32)
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C6]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 4
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 4
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 4
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 4
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 4
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 4
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 4
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 4
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32), [[SEXT_INREG3]](s32)
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<4 x s32>), [[COPY1]](s32)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY10]](s32)
+ ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0
@@ -453,15 +422,13 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_v3s8_varidx_i32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
- ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 8
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 8
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 8
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[COPY1]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
+ ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = COPY $vgpr3
%2:_(<3 x s8>) = G_TRUNC %0
@@ -487,26 +454,21 @@ body: |
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C3]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[SHL3]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY6]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(<4 x s8>) = G_BITCAST %0
@@ -532,23 +494,18 @@ body: |
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C4]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C4]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C3]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY5]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(<4 x s8>) = G_BITCAST %0
%2:_(s32) = G_CONSTANT i32 0
@@ -573,23 +530,18 @@ body: |
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C3]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY5]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(<4 x s8>) = G_BITCAST %0
%2:_(s32) = G_CONSTANT i32 1
@@ -614,23 +566,18 @@ body: |
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C3]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C1]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY5]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(<4 x s8>) = G_BITCAST %0
%2:_(s32) = G_CONSTANT i32 2
@@ -655,23 +602,18 @@ body: |
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C3]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR2]], [[C2]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY5]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(<4 x s8>) = G_BITCAST %0
%2:_(s32) = G_CONSTANT i32 3
@@ -706,15 +648,13 @@ body: |
; CHECK: [[LSHR4:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC2]], [[C1]](s16)
; CHECK: [[LSHR5:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC3]], [[C1]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR3]](s16)
@@ -722,14 +662,12 @@ body: |
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR4]](s16)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C2]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C3]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR5]](s16)
@@ -744,8 +682,7 @@ body: |
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C6]](s32)
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[EVEC]], [[SHL6]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY6]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR7]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(<8 x s8>) = G_BITCAST %0
@@ -774,15 +711,13 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C2]](s16)
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C2]](s16)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
@@ -790,10 +725,9 @@ body: |
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C5]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
+ ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 0
%2:_(<8 x s8>) = G_BITCAST %0
@@ -820,15 +754,13 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
@@ -836,10 +768,9 @@ body: |
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C3]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
+ ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C3]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 1
%2:_(<8 x s8>) = G_BITCAST %0
@@ -866,15 +797,13 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
@@ -882,10 +811,9 @@ body: |
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C4]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
+ ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C4]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 3
%2:_(<8 x s8>) = G_BITCAST %0
@@ -912,15 +840,13 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
@@ -928,11 +854,10 @@ body: |
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C5]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
+ ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C5]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 4
%2:_(<8 x s8>) = G_BITCAST %0
@@ -959,15 +884,13 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
@@ -975,10 +898,9 @@ body: |
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C3]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
+ ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C3]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 5
%2:_(<8 x s8>) = G_BITCAST %0
@@ -1005,15 +927,13 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
; CHECK: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
@@ -1021,10 +941,9 @@ body: |
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C4]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
+ ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C4]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR3]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 7
%2:_(<8 x s8>) = G_BITCAST %0
@@ -1049,8 +968,7 @@ body: |
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[SHL]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
@@ -1070,8 +988,7 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 0
%2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
@@ -1091,8 +1008,7 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 1
%2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
@@ -1112,8 +1028,7 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 2
%2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
@@ -1131,15 +1046,13 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_v3s16_varidx_i32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; CHECK: [[COPY2:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
- ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<3 x s32>)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[COPY1]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
+ ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = COPY $vgpr3
%2:_(<3 x s16>) = G_TRUNC %0
@@ -1157,15 +1070,13 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_v3s16_idx0_i32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
- ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 0
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
+ ; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_CONSTANT i32 0
%2:_(<3 x s16>) = G_TRUNC %0
@@ -1183,15 +1094,13 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_v3s16_idx1_i32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
- ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 32
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
+ ; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_CONSTANT i32 1
%2:_(<3 x s16>) = G_TRUNC %0
@@ -1209,15 +1118,13 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_v3s16_idx2_i32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
- ; CHECK: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY [[COPY]](<3 x s32>)
- ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<3 x s32>)
+ ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 64
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
+ ; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_CONSTANT i32 2
%2:_(<3 x s16>) = G_TRUNC %0
@@ -1236,8 +1143,7 @@ body: |
; CHECK-LABEL: name: extract_vector_elt_v3s16_idx3_i32
; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[DEF]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s32) = G_CONSTANT i32 3
%2:_(<3 x s16>) = G_TRUNC %0
@@ -1264,8 +1170,7 @@ body: |
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[EVEC]], [[SHL]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR1]](s32)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s16) = G_EXTRACT_VECTOR_ELT %0, %1
@@ -1995,138 +1900,105 @@ body: |
; CHECK: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C29]](s32)
; CHECK: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C30]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C3]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C]]
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C]]
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C]]
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C7]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+ ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C]]
; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C8]](s32)
; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
+ ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C]]
; CHECK: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C9]](s32)
; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[SHL9]]
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C]]
+ ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C]]
; CHECK: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C10]](s32)
; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C]]
+ ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C]]
; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C11]](s32)
; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C]]
+ ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C]]
; CHECK: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C12]](s32)
; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR11]], [[SHL12]]
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C]]
+ ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C]]
; CHECK: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C13]](s32)
; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C]]
+ ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C]]
; CHECK: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C14]](s32)
; CHECK: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C]]
+ ; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C]]
; CHECK: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND16]], [[C15]](s32)
; CHECK: [[OR15:%[0-9]+]]:_(s32) = G_OR [[OR14]], [[SHL15]]
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C]]
+ ; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LSHR16]], [[C]]
; CHECK: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C16]](s32)
; CHECK: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; CHECK: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C]]
+ ; CHECK: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR17]], [[C]]
; CHECK: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C17]](s32)
; CHECK: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; CHECK: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C]]
+ ; CHECK: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR18]], [[C]]
; CHECK: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C18]](s32)
; CHECK: [[OR18:%[0-9]+]]:_(s32) = G_OR [[OR17]], [[SHL18]]
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; CHECK: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C]]
+ ; CHECK: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LSHR19]], [[C]]
; CHECK: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND20]], [[C19]](s32)
; CHECK: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; CHECK: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C]]
+ ; CHECK: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LSHR20]], [[C]]
; CHECK: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C20]](s32)
; CHECK: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; CHECK: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C]]
+ ; CHECK: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR21]], [[C]]
; CHECK: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C21]](s32)
; CHECK: [[OR21:%[0-9]+]]:_(s32) = G_OR [[OR20]], [[SHL21]]
- ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; CHECK: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C]]
+ ; CHECK: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR22]], [[C]]
; CHECK: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C22]](s32)
; CHECK: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
- ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; CHECK: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C]]
+ ; CHECK: [[AND24:%[0-9]+]]:_(s32) = G_AND [[LSHR23]], [[C]]
; CHECK: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C23]](s32)
; CHECK: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
- ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR24]](s32)
- ; CHECK: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C]]
+ ; CHECK: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LSHR24]], [[C]]
; CHECK: [[SHL24:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[C24]](s32)
; CHECK: [[OR24:%[0-9]+]]:_(s32) = G_OR [[OR23]], [[SHL24]]
- ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR25]](s32)
- ; CHECK: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C]]
+ ; CHECK: [[AND26:%[0-9]+]]:_(s32) = G_AND [[LSHR25]], [[C]]
; CHECK: [[SHL25:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C25]](s32)
; CHECK: [[OR25:%[0-9]+]]:_(s32) = G_OR [[OR24]], [[SHL25]]
- ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LSHR26]](s32)
- ; CHECK: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C]]
+ ; CHECK: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LSHR26]], [[C]]
; CHECK: [[SHL26:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[C26]](s32)
; CHECK: [[OR26:%[0-9]+]]:_(s32) = G_OR [[OR25]], [[SHL26]]
- ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR27]](s32)
- ; CHECK: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C]]
+ ; CHECK: [[AND28:%[0-9]+]]:_(s32) = G_AND [[LSHR27]], [[C]]
; CHECK: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[AND28]], [[C27]](s32)
; CHECK: [[OR27:%[0-9]+]]:_(s32) = G_OR [[OR26]], [[SHL27]]
- ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR28]](s32)
- ; CHECK: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C]]
+ ; CHECK: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LSHR28]], [[C]]
; CHECK: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[C28]](s32)
; CHECK: [[OR28:%[0-9]+]]:_(s32) = G_OR [[OR27]], [[SHL28]]
- ; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR29]](s32)
- ; CHECK: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C]]
+ ; CHECK: [[AND30:%[0-9]+]]:_(s32) = G_AND [[LSHR29]], [[C]]
; CHECK: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[C29]](s32)
; CHECK: [[OR29:%[0-9]+]]:_(s32) = G_OR [[OR28]], [[SHL29]]
- ; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[LSHR30]](s32)
- ; CHECK: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY33]], [[C]]
+ ; CHECK: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LSHR30]], [[C]]
; CHECK: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C30]](s32)
; CHECK: [[OR30:%[0-9]+]]:_(s32) = G_OR [[OR29]], [[SHL30]]
; CHECK: [[AND32:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C30]]
; CHECK: [[C31:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SHL31:%[0-9]+]]:_(s32) = G_SHL [[AND32]], [[C31]](s32)
; CHECK: [[LSHR31:%[0-9]+]]:_(s32) = G_LSHR [[OR30]], [[SHL31]](s32)
- ; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[LSHR31]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY34]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR31]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(<32 x s1>) = G_BITCAST %0
@@ -2158,46 +2030,34 @@ body: |
; CHECK: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr3
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C3]]
+ ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C3]]
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
+ ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C3]]
; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -2208,8 +2068,7 @@ body: |
; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
; CHECK: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C5]](s32)
; CHECK: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[EVEC]], [[SHL9]](s32)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY14]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR10]](s32)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<12 x s8>) = G_BITCAST %0
%2:_(s32) = COPY $vgpr3
@@ -2233,19 +2092,12 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 8
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 8
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 8
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 8
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 8
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<3 x s32>), [[COPY1]](s32)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[EVEC]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY8]](s32)
+ ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s24) = G_TRUNC %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
index 8b43fa6976337..b42568e8c5f08 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
@@ -72,8 +72,7 @@ body: |
; CHECK-LABEL: name: test_extract_s32_s48_offset0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](s64), 0
+ ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s64), 0
; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s48) = G_TRUNC %0
@@ -526,16 +525,13 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF1]](<4 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
@@ -615,8 +611,7 @@ body: |
liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s8_s16_offset0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s8) = G_EXTRACT %1, 0
@@ -669,8 +664,7 @@ body: |
liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s8_s32_offset0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 0
%2:_(s32) = G_ANYEXT %1
@@ -686,8 +680,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 1
%2:_(s32) = G_ANYEXT %1
@@ -703,8 +696,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 8
%2:_(s32) = G_ANYEXT %1
@@ -720,8 +712,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 16
%2:_(s32) = G_ANYEXT %1
@@ -737,8 +728,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 16
%2:_(s32) = G_ANYEXT %1
@@ -753,8 +743,7 @@ body: |
; CHECK-LABEL: name: test_extract_s8_p3_offset0
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[PTRTOINT]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[PTRTOINT]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 0
%2:_(s32) = G_ANYEXT %1
@@ -771,8 +760,7 @@ body: |
; CHECK: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s8) = G_EXTRACT %0, 8
%2:_(s32) = G_ANYEXT %1
@@ -786,8 +774,7 @@ body: |
liveins: $vgpr0
; CHECK-LABEL: name: test_extract_s1_s8_offset0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
%2:_(s1) = G_EXTRACT %1, 0
@@ -961,8 +948,7 @@ body: |
; CHECK-LABEL: name: extract_s16_v2s16_offset0
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[BITCAST]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 0
%2:_(s32) = G_ANYEXT %1
@@ -980,8 +966,7 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 1
%2:_(s32) = G_ANYEXT %1
@@ -999,8 +984,7 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 8
%2:_(s32) = G_ANYEXT %1
@@ -1018,8 +1002,7 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 16
%2:_(s32) = G_ANYEXT %1
@@ -1034,8 +1017,7 @@ body: |
; CHECK-LABEL: name: extract_s16_s32_offset0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 0
%2:_(s32) = G_ANYEXT %1
@@ -1052,8 +1034,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 1
%2:_(s32) = G_ANYEXT %1
@@ -1070,8 +1051,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 8
%2:_(s32) = G_ANYEXT %1
@@ -1088,8 +1068,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 16
%2:_(s32) = G_ANYEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
index d67d279852cb3..850eda73a7187 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
@@ -218,15 +218,12 @@ body: |
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
@@ -242,24 +239,18 @@ body: |
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; SI: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[FABS1]](<2 x s16>)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL2]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C1]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL3]]
; SI: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C1]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL4]]
; SI: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
@@ -275,15 +266,12 @@ body: |
; VI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
@@ -299,24 +287,18 @@ body: |
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; VI: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[FABS1]](<2 x s16>)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL2]]
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C1]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL3]]
; VI: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C1]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL4]]
; VI: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
@@ -331,12 +313,9 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[DEF2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[DEF2]](s32)
; GFX9: [[DEF3:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[FABS:%[0-9]+]]:_(<2 x s16>) = G_FABS [[BUILD_VECTOR_TRUNC]]
; GFX9: [[FABS1:%[0-9]+]]:_(<2 x s16>) = G_FABS [[BUILD_VECTOR_TRUNC1]]
@@ -348,15 +327,9 @@ body: |
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; GFX9: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[FABS1]](<2 x s16>)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST2]](s32), [[LSHR2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST3]](s32), [[BITCAST4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR4]](s32), [[BITCAST5]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>), [[BUILD_VECTOR_TRUNC4]](<2 x s16>)
; GFX9: S_NOP 0, implicit [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<3 x s16>) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
index 484860e763a58..7db972b6dc94c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
@@ -389,15 +389,12 @@ body: |
; SI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC2]](s16)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; SI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -442,15 +439,12 @@ body: |
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FADD2]](s16)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -465,23 +459,17 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[DEF]](s32)
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<6 x s16>)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST2]](s32), [[LSHR2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST3]](s32), [[DEF]](s32)
; GFX9: [[FADD:%[0-9]+]]:_(<2 x s16>) = G_FADD [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]]
; GFX9: [[FADD1:%[0-9]+]]:_(<2 x s16>) = G_FADD [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]]
; GFX9: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@@ -495,15 +483,9 @@ body: |
; GFX9: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; GFX9: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; GFX9: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST4]](s32), [[LSHR4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST5]](s32), [[BITCAST6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR6]](s32), [[BITCAST7]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC4]](<2 x s16>), [[BUILD_VECTOR_TRUNC5]](<2 x s16>), [[BUILD_VECTOR_TRUNC6]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
index 0ccf2efe6d66d..fcdadce780310 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
@@ -280,12 +280,9 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[DEF2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[DEF2]](s32)
; GFX9: [[DEF3:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[FCANONICALIZE:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[BUILD_VECTOR_TRUNC]]
; GFX9: [[FCANONICALIZE1:%[0-9]+]]:_(<2 x s16>) = G_FCANONICALIZE [[BUILD_VECTOR_TRUNC1]]
@@ -293,10 +290,7 @@ body: |
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[FCANONICALIZE1]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
+ ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[BITCAST2]](s32), [[LSHR2]](s32), [[BITCAST3]](s32)
; GFX9: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s16>) = G_IMPLICIT_DEF
%1:_(<3 x s16>) = G_FCANONICALIZE %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
index e4024067369fd..ba8abdfe9dda8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
@@ -117,9 +117,7 @@ body: |
; GFX7: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[C]](s32), [[UV1]]
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP1]](s1)
- ; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX7: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s32>)
; GFX8-LABEL: name: test_fcmp_v2s32
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -129,9 +127,7 @@ body: |
; GFX8: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[C]](s32), [[UV1]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP1]](s1)
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX8: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_fcmp_v2s32
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -164,9 +160,7 @@ body: |
; GFX7: [[FCMP1:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(oeq), [[C]](s32), [[UV1]]
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP1]](s1)
- ; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX7: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s32>)
; GFX8-LABEL: name: test_fcmp_v2s32_flags
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -176,9 +170,7 @@ body: |
; GFX8: [[FCMP1:%[0-9]+]]:_(s1) = nnan G_FCMP floatpred(oeq), [[C]](s32), [[UV1]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP1]](s1)
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX8: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_fcmp_v2s32_flags
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -215,10 +207,7 @@ body: |
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP1]](s1)
; GFX7: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP2]](s1)
- ; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
; GFX7: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
; GFX8-LABEL: name: test_fcmp_v3s32
; GFX8: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
@@ -231,10 +220,7 @@ body: |
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP1]](s1)
; GFX8: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP2]](s1)
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
; GFX8: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
; GFX9-LABEL: name: test_fcmp_v3s32
; GFX9: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
@@ -277,11 +263,7 @@ body: |
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP1]](s1)
; GFX7: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP2]](s1)
; GFX7: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP3]](s1)
- ; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
- ; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32), [[ANYEXT3]](s32)
; GFX7: S_NOP 0, implicit [[BUILD_VECTOR]](<4 x s32>)
; GFX8-LABEL: name: test_fcmp_v4s32
; GFX8: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
@@ -297,11 +279,7 @@ body: |
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP1]](s1)
; GFX8: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP2]](s1)
; GFX8: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP3]](s1)
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
- ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32), [[ANYEXT3]](s32)
; GFX8: S_NOP 0, implicit [[BUILD_VECTOR]](<4 x s32>)
; GFX9-LABEL: name: test_fcmp_v4s32
; GFX9: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
index a1f4f8eda9da7..a6ad03ebbc27c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
@@ -299,8 +299,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND2]]
@@ -313,8 +312,7 @@ body: |
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND2]]
@@ -327,8 +325,7 @@ body: |
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[AND2]]
@@ -806,8 +803,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
; SI: [[OR:%[0-9]+]]:_(s32) = nnan G_OR [[AND]], [[AND2]]
@@ -820,8 +816,7 @@ body: |
; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
; VI: [[OR:%[0-9]+]]:_(s32) = nnan G_OR [[AND]], [[AND2]]
@@ -834,8 +829,7 @@ body: |
; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C]]
; GFX9: [[OR:%[0-9]+]]:_(s32) = nnan G_OR [[AND]], [[AND2]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
index 55254db84e78f..1ebea9e479750 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
@@ -453,15 +453,12 @@ body: |
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC2]](s16)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; SI: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; SI: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -515,15 +512,12 @@ body: |
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FMA2]](s16)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -539,33 +533,24 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[DEF]](s32)
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<6 x s16>)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST2]](s32), [[LSHR2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST3]](s32), [[DEF]](s32)
; GFX9: [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>), [[UV8:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY2]](<6 x s16>)
; GFX9: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV6]](<2 x s16>)
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; GFX9: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST4]](s32), [[LSHR4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST5]](s32), [[DEF]](s32)
; GFX9: [[FMA:%[0-9]+]]:_(<2 x s16>) = G_FMA [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]], [[BUILD_VECTOR_TRUNC4]]
; GFX9: [[FMA1:%[0-9]+]]:_(<2 x s16>) = G_FMA [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]], [[BUILD_VECTOR_TRUNC5]]
; GFX9: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@@ -579,15 +564,9 @@ body: |
; GFX9: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST8]], [[C]](s32)
; GFX9: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[UV10]](<2 x s16>)
; GFX9: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST6]](s32), [[LSHR6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST7]](s32), [[BITCAST8]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR8]](s32), [[BITCAST9]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC6]](<2 x s16>), [[BUILD_VECTOR_TRUNC7]](<2 x s16>), [[BUILD_VECTOR_TRUNC8]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
index dab78056826de..beeeb33f33527 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
@@ -438,15 +438,12 @@ body: |
; SI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC2]](s16)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; SI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -497,15 +494,12 @@ body: |
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FMAXNUM_IEEE2]](s16)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -538,15 +532,9 @@ body: |
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV9]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[BITCAST2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[BITCAST3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
index 17cafbfc93571..54171e4490070 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
@@ -438,15 +438,12 @@ body: |
; SI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC2]](s16)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; SI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -497,15 +494,12 @@ body: |
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FMINNUM_IEEE2]](s16)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -538,15 +532,9 @@ body: |
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV9]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[BITCAST2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[BITCAST3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
index 909aae04304eb..378dd82eeb93e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
@@ -2,7 +2,6 @@
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=SI %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=VI %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9 %s
-# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck -check-prefix=GFX9 %s
---
name: test_fmul_s32
@@ -376,15 +375,12 @@ body: |
; SI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC2]](s16)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; SI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -429,15 +425,12 @@ body: |
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FMUL2]](s16)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -452,23 +445,17 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[DEF]](s32)
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<6 x s16>)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST2]](s32), [[LSHR2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST3]](s32), [[DEF]](s32)
; GFX9: [[FMUL:%[0-9]+]]:_(<2 x s16>) = G_FMUL [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]]
; GFX9: [[FMUL1:%[0-9]+]]:_(<2 x s16>) = G_FMUL [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]]
; GFX9: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@@ -482,15 +469,9 @@ body: |
; GFX9: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; GFX9: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; GFX9: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST4]](s32), [[LSHR4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST5]](s32), [[BITCAST6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR6]](s32), [[BITCAST7]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC4]](<2 x s16>), [[BUILD_VECTOR_TRUNC5]](<2 x s16>), [[BUILD_VECTOR_TRUNC6]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
index 93e8875b1223a..ad83c9b766c90 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
@@ -216,15 +216,12 @@ body: |
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
@@ -236,12 +233,9 @@ body: |
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; SI: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[FNEG1]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND3]](s32), [[AND4]](s32), [[AND5]](s32)
; SI: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
; VI-LABEL: name: test_fneg_v3s16
@@ -254,15 +248,12 @@ body: |
; VI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
@@ -274,12 +265,9 @@ body: |
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; VI: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[FNEG1]](<2 x s16>)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND3]](s32), [[AND4]](s32), [[AND5]](s32)
; VI: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
; GFX9-LABEL: name: test_fneg_v3s16
@@ -291,12 +279,9 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[DEF2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[DEF2]](s32)
; GFX9: [[DEF3:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[FNEG:%[0-9]+]]:_(<2 x s16>) = G_FNEG [[BUILD_VECTOR_TRUNC]]
; GFX9: [[FNEG1:%[0-9]+]]:_(<2 x s16>) = G_FNEG [[BUILD_VECTOR_TRUNC1]]
@@ -305,12 +290,9 @@ body: |
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[FNEG1]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32)
; GFX9: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s16>) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
index d6c0aafc31040..4de60409defa1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
@@ -101,8 +101,7 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[FPTOSI]](s32)
; VI-LABEL: name: test_fptosi_s16_to_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
@@ -125,13 +124,11 @@ body: |
; SI-LABEL: name: test_fptosi_s32_to_s16
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[FPTOSI]](s32)
; VI-LABEL: name: test_fptosi_s32_to_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[FPTOSI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_FPTOSI %0
%2:_(s32) = G_ANYEXT %1
@@ -147,13 +144,11 @@ body: |
; SI-LABEL: name: test_fptosi_s64_to_s16
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[FPTOSI]](s32)
; VI-LABEL: name: test_fptosi_s64_to_s16
; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[FPTOSI]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s16) = G_FPTOSI %0
%2:_(s32) = G_ANYEXT %1
@@ -608,14 +603,12 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[FPTOSI]](s32)
; VI-LABEL: name: test_fptosi_s16_to_s15
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s16)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[FPTOSI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s15) = G_FPTOSI %1
@@ -634,14 +627,12 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[FPTOSI]](s32)
; VI-LABEL: name: test_fptosi_s16_to_s17
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s16)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[FPTOSI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s17) = G_FPTOSI %1
@@ -675,8 +666,7 @@ body: |
; SI: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[ASHR]]
; SI: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[ASHR]], [[USUBO1]]
; SI: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[MV2]](s64)
- ; SI: $vgpr0_vgpr1 = COPY [[COPY1]](s64)
+ ; SI: $vgpr0_vgpr1 = COPY [[MV2]](s64)
; VI-LABEL: name: test_fptosi_s32_to_s33
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
@@ -697,8 +687,7 @@ body: |
; VI: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[ASHR]]
; VI: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[ASHR]], [[USUBO1]]
; VI: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
- ; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[MV2]](s64)
- ; VI: $vgpr0_vgpr1 = COPY [[COPY1]](s64)
+ ; VI: $vgpr0_vgpr1 = COPY [[MV2]](s64)
%0:_(s32) = COPY $vgpr0
%1:_(s33) = G_FPTOSI %0
%2:_(s64) = G_ANYEXT %1
@@ -716,14 +705,12 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[FPTOSI]](s32)
; VI-LABEL: name: test_fptosi_s16_to_s7
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s16)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[FPTOSI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s7) = G_FPTOSI %1
@@ -742,14 +729,12 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[FPTOSI]](s32)
; VI-LABEL: name: test_fptosi_s16_to_s8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s16)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[FPTOSI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s8) = G_FPTOSI %1
@@ -768,14 +753,12 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[FPTOSI]](s32)
; VI-LABEL: name: test_fptosi_s16_to_s9
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s16)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[FPTOSI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s9) = G_FPTOSI %1
@@ -792,13 +775,11 @@ body: |
; SI-LABEL: name: test_fptosi_s32_to_s15
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[FPTOSI]](s32)
; VI-LABEL: name: test_fptosi_s32_to_s15
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[FPTOSI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s15) = G_FPTOSI %0
%2:_(s32) = G_ANYEXT %1
@@ -814,13 +795,11 @@ body: |
; SI-LABEL: name: test_fptosi_s32_to_s17
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[FPTOSI]](s32)
; VI-LABEL: name: test_fptosi_s32_to_s17
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[FPTOSI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s17) = G_FPTOSI %0
%2:_(s32) = G_ANYEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
index 8bf5feb3d5e51..915a114636583 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
@@ -101,8 +101,7 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[FPTOUI]](s32)
; VI-LABEL: name: test_fptoui_s16_to_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
@@ -125,13 +124,11 @@ body: |
; SI-LABEL: name: test_fptoui_s32_to_s16
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[FPTOUI]](s32)
; VI-LABEL: name: test_fptoui_s32_to_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[FPTOUI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_FPTOUI %0
%2:_(s32) = G_ANYEXT %1
@@ -147,13 +144,11 @@ body: |
; SI-LABEL: name: test_fptoui_s64_to_s16
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[FPTOUI]](s32)
; VI-LABEL: name: test_fptoui_s64_to_s16
; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[FPTOUI]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s16) = G_FPTOUI %0
%2:_(s32) = G_ANYEXT %1
@@ -556,14 +551,12 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[FPTOUI]](s32)
; VI-LABEL: name: test_fptoui_s16_to_s15
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[TRUNC]](s16)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[FPTOUI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s15) = G_FPTOUI %1
@@ -582,14 +575,12 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[FPTOUI]](s32)
; VI-LABEL: name: test_fptoui_s16_to_s17
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[TRUNC]](s16)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[FPTOUI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s17) = G_FPTOUI %1
@@ -614,8 +605,7 @@ body: |
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FFLOOR]](s32)
; SI: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[FMA]](s32)
; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](s32), [[FPTOUI]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
- ; SI: $vgpr0_vgpr1 = COPY [[COPY1]](s64)
+ ; SI: $vgpr0_vgpr1 = COPY [[MV]](s64)
; VI-LABEL: name: test_fptoui_s32_to_s33
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[COPY]]
@@ -627,8 +617,7 @@ body: |
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FFLOOR]](s32)
; VI: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[FMA]](s32)
; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](s32), [[FPTOUI]](s32)
- ; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
- ; VI: $vgpr0_vgpr1 = COPY [[COPY1]](s64)
+ ; VI: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(s32) = COPY $vgpr0
%1:_(s33) = G_FPTOUI %0
%2:_(s64) = G_ANYEXT %1
@@ -646,14 +635,12 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[FPTOUI]](s32)
; VI-LABEL: name: test_fptoui_s16_to_s7
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[TRUNC]](s16)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[FPTOUI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s7) = G_FPTOUI %1
@@ -672,14 +659,12 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[FPTOUI]](s32)
; VI-LABEL: name: test_fptoui_s16_to_s8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[TRUNC]](s16)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[FPTOUI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s8) = G_FPTOUI %1
@@ -698,14 +683,12 @@ body: |
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[FPTOUI]](s32)
; VI-LABEL: name: test_fptoui_s16_to_s9
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[TRUNC]](s16)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[FPTOUI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s9) = G_FPTOUI %1
@@ -722,13 +705,11 @@ body: |
; SI-LABEL: name: test_fptoui_s32_to_s15
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[FPTOUI]](s32)
; VI-LABEL: name: test_fptoui_s32_to_s15
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[FPTOUI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s15) = G_FPTOUI %0
%2:_(s32) = G_ANYEXT %1
@@ -744,13 +725,11 @@ body: |
; SI-LABEL: name: test_fptoui_s32_to_s17
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[FPTOUI]](s32)
; VI-LABEL: name: test_fptoui_s32_to_s17
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[FPTOUI]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s17) = G_FPTOUI %0
%2:_(s32) = G_ANYEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
index c429b9dac0c96..c17ec7039df09 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
@@ -70,9 +70,7 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST]](<2 x s16>)
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[BITCAST1]](s32), [[LSHR]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s16>) = G_FPTRUNC %0
@@ -151,8 +149,7 @@ body: |
; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 32768
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C20]]
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SELECT3]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR7]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[OR7]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s16) = G_FPTRUNC %0
%2:_(s32) = G_ANYEXT %1
@@ -274,10 +271,8 @@ body: |
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C20]]
; CHECK: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[SELECT7]]
; CHECK: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR7]](s32)
- ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C21]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR15]](s32)
- ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C21]]
+ ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR7]], [[C21]]
+ ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[OR15]], [[C21]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C19]](s32)
; CHECK: [[OR16:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL4]]
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR16]](s32)
@@ -358,8 +353,7 @@ body: |
; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 32768
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C20]]
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SELECT3]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR7]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[OR7]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s16) = G_FPTRUNC %0
%2:_(s32) = afn G_ANYEXT %1
@@ -481,10 +475,8 @@ body: |
; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C20]]
; CHECK: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[SELECT7]]
; CHECK: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR7]](s32)
- ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C21]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR15]](s32)
- ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C21]]
+ ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[OR7]], [[C21]]
+ ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[OR15]], [[C21]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C19]](s32)
; CHECK: [[OR16:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL4]]
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR16]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
index a1cc82b8d44d0..377dba4b3bea5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
@@ -27,10 +27,8 @@ body: |
; CHECK-LABEL: name: test_freeze_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FREEZE]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
+ ; CHECK: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]]
+ ; CHECK: $vgpr0 = COPY [[FREEZE]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
%2:_(s7) = G_FREEZE %1
@@ -45,10 +43,8 @@ body: |
; CHECK-LABEL: name: test_freeze_s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FREEZE]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
+ ; CHECK: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]]
+ ; CHECK: $vgpr0 = COPY [[FREEZE]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
%2:_(s8) = G_FREEZE %1
@@ -95,10 +91,8 @@ body: |
; CHECK-LABEL: name: test_freeze_s48
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[FREEZE]](s64)
- ; CHECK: $vgpr0_vgpr1 = COPY [[COPY2]](s64)
+ ; CHECK: [[FREEZE:%[0-9]+]]:_(s64) = G_FREEZE [[COPY]]
+ ; CHECK: $vgpr0_vgpr1 = COPY [[FREEZE]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s48) = G_TRUNC %0
%2:_(s48) = G_FREEZE %1
@@ -474,12 +468,9 @@ body: |
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](s32), [[UV3]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
; CHECK: [[FREEZE:%[0-9]+]]:_(<2 x s32>) = G_FREEZE [[BUILD_VECTOR]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(<2 x s32>) = COPY [[FREEZE]](<2 x s32>)
- ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](<2 x s32>)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[FREEZE]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
%2:_(<2 x s1>) = G_ICMP intpred(ne), %0, %1
@@ -505,13 +496,9 @@ body: |
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
; CHECK: [[FREEZE:%[0-9]+]]:_(<3 x s32>) = G_FREEZE [[BUILD_VECTOR]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(<3 x s32>) = COPY [[FREEZE]](<3 x s32>)
- ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[COPY5]](<3 x s32>)
+ ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[FREEZE]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
%2:_(<3 x s1>) = G_ICMP intpred(ne), %0, %1
@@ -527,10 +514,8 @@ body: |
; CHECK-LABEL: name: test_freeze_v2s8
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY [[COPY]](<2 x s32>)
- ; CHECK: [[FREEZE:%[0-9]+]]:_(<2 x s32>) = G_FREEZE [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY [[FREEZE]](<2 x s32>)
- ; CHECK: $vgpr0_vgpr1 = COPY [[COPY2]](<2 x s32>)
+ ; CHECK: [[FREEZE:%[0-9]+]]:_(<2 x s32>) = G_FREEZE [[COPY]]
+ ; CHECK: $vgpr0_vgpr1 = COPY [[FREEZE]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s8>) = G_TRUNC %0
%2:_(<2 x s8>) = G_FREEZE %1
@@ -601,10 +586,7 @@ body: |
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV6]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
+ ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[LSHR]](s32), [[BITCAST1]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR2]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s16>) = G_TRUNC %0
@@ -656,12 +638,7 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV9]](<2 x s16>)
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
+ ; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<5 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[LSHR]](s32), [[BITCAST1]](s32), [[LSHR1]](s32), [[BITCAST2]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 = COPY [[BUILD_VECTOR3]](<5 x s32>)
%0:_(<5 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4
%1:_(<5 x s16>) = G_TRUNC %0
@@ -723,22 +700,10 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
; CHECK: [[FREEZE:%[0-9]+]]:_(<4 x s32>) = G_FREEZE [[BUILD_VECTOR]]
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[FREEZE]](<4 x s32>)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CHECK: S_ENDPGM 0, implicit [[COPY12]](s32), implicit [[COPY13]](s32), implicit [[COPY14]](s32), implicit [[COPY15]](s32)
+ ; CHECK: S_ENDPGM 0, implicit [[UV]](s32), implicit [[UV1]](s32), implicit [[UV2]](s32), implicit [[UV3]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
index 93af75e3d6ed2..77caab50d1457 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
@@ -136,17 +136,14 @@ body: |
; SI: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C1]]
; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[ZEXT]](s32)
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[ZEXT]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C2]](s32)
; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[ZEXT1]](s32)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC1]], [[TRUNC2]]
@@ -226,17 +223,14 @@ body: |
; SI: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C2]]
; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C1]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[ZEXT]](s32)
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[ZEXT]](s32)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C4]]
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32)
; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C4]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[ZEXT1]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC2]], [[TRUNC3]]
@@ -244,16 +238,13 @@ body: |
; SI: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[TRUNC1]], [[C2]]
; SI: [[AND5:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C1]]
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[ZEXT2]](s32)
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ZEXT2]](s32)
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
- ; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY7]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
+ ; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY3]](s32)
; SI: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C4]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C4]]
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[ZEXT3]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR6]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC4]], [[TRUNC5]]
@@ -406,117 +397,80 @@ body: |
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[COPY4]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY5]], [[COPY6]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[COPY8]]
+ ; SI: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY10]], [[AND2]](s32)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
- ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
- ; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[AND5]](s32)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[COPY16]]
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; SI: $vgpr0 = COPY [[COPY17]](s32)
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C3]]
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND2]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY3]](s32)
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[AND1]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[AND4]](s32)
+ ; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
+ ; SI: $vgpr0 = COPY [[OR]](s32)
; VI-LABEL: name: test_fshl_s8_s8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[COPY4]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; VI: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY5]], [[COPY6]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[COPY8]]
+ ; VI: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C3]]
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND2]](s32)
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; VI: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
- ; VI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[AND3]](s32)
- ; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND4]], [[TRUNC3]](s16)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
- ; VI: [[COPY12:%[0-9]+]]:_(s16) = COPY [[LSHR]](s16)
- ; VI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[COPY12]], [[C4]]
- ; VI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[AND5]](s32)
- ; VI: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[AND6]], [[TRUNC4]](s16)
+ ; VI: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
+ ; VI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)
+ ; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND3]], [[TRUNC3]](s16)
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[AND1]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s16) = G_AND [[LSHR]], [[C4]]
+ ; VI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[AND4]](s32)
+ ; VI: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[AND5]], [[TRUNC4]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; VI: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; VI: $vgpr0 = COPY [[COPY13]](s32)
+ ; VI: $vgpr0 = COPY [[OR]](s32)
; GFX9-LABEL: name: test_fshl_s8_s8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[COPY4]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY5]], [[COPY6]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[COPY8]]
+ ; GFX9: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C3]]
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND2]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
- ; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[AND3]](s32)
- ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND4]], [[TRUNC3]](s16)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s16) = COPY [[LSHR]](s16)
- ; GFX9: [[AND6:%[0-9]+]]:_(s16) = G_AND [[COPY12]], [[C4]]
- ; GFX9: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[AND5]](s32)
- ; GFX9: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[AND6]], [[TRUNC4]](s16)
+ ; GFX9: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
+ ; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND3]], [[TRUNC3]](s16)
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[AND1]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s16) = G_AND [[LSHR]], [[C4]]
+ ; GFX9: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[AND4]](s32)
+ ; GFX9: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[AND5]], [[TRUNC4]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY13]](s32)
+ ; GFX9: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2
@@ -541,52 +495,39 @@ body: |
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
- ; SI: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; SI: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY3]](s32)
; SI: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; SI: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
; SI: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[AND1]]
+ ; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[COPY3]]
; SI: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SUB]], [[FPTOUI]]
; SI: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI]], [[MUL]]
; SI: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI]], [[UMULH]]
; SI: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[ADD]]
- ; SI: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[AND1]]
+ ; SI: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[COPY3]]
; SI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[MUL1]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[AND1]]
- ; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND1]]
+ ; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[COPY3]]
+ ; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY3]]
; SI: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
- ; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
- ; SI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
+ ; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[COPY3]]
+ ; SI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY3]]
; SI: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; SI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY5]], [[COPY6]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[AND2]](s32)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C2]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C2]]
- ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C2]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C2]]
- ; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[AND5]](s32)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY13]], [[COPY14]]
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; SI: $vgpr0 = COPY [[COPY15]](s32)
+ ; SI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)
+ ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY4]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
+ ; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
+ ; SI: $vgpr0 = COPY [[OR]](s32)
; VI-LABEL: name: test_fshl_s24_s24
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -594,52 +535,39 @@ body: |
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
- ; VI: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; VI: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY3]](s32)
; VI: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
; VI: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; VI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[AND1]]
+ ; VI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[COPY3]]
; VI: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SUB]], [[FPTOUI]]
; VI: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI]], [[MUL]]
; VI: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI]], [[UMULH]]
; VI: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[ADD]]
- ; VI: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[AND1]]
+ ; VI: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[COPY3]]
; VI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[MUL1]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[AND1]]
- ; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND1]]
+ ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[COPY3]]
+ ; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY3]]
; VI: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
- ; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
- ; VI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
+ ; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[COPY3]]
+ ; VI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY3]]
; VI: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; VI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY5]], [[COPY6]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[AND2]](s32)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C2]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C2]]
- ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C2]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C2]]
- ; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[AND5]](s32)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY13]], [[COPY14]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; VI: $vgpr0 = COPY [[COPY15]](s32)
+ ; VI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
+ ; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)
+ ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY4]](s32)
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
+ ; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
+ ; VI: $vgpr0 = COPY [[OR]](s32)
; GFX9-LABEL: name: test_fshl_s24_s24
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -647,52 +575,39 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
- ; GFX9: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX9: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY3]](s32)
; GFX9: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
; GFX9: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; GFX9: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[AND1]]
+ ; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[COPY3]]
; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SUB]], [[FPTOUI]]
; GFX9: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI]], [[MUL]]
; GFX9: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI]], [[UMULH]]
; GFX9: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[ADD]]
- ; GFX9: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[AND1]]
+ ; GFX9: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[COPY3]]
; GFX9: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[MUL1]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[AND1]]
- ; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND1]]
+ ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[COPY3]]
+ ; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY3]]
; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
- ; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
- ; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
+ ; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[COPY3]]
+ ; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY3]]
; GFX9: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY5]], [[COPY6]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[AND2]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C2]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C2]]
- ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C2]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C2]]
- ; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[AND5]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY13]], [[COPY14]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY15]](s32)
+ ; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
+ ; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)
+ ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY4]](s32)
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
+ ; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR1]]
+ ; GFX9: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2
@@ -740,17 +655,14 @@ body: |
; SI: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C2]]
; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C1]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[ZEXT]](s32)
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[ZEXT]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C4]]
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32)
; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C4]]
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[ZEXT1]](s32)
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR7]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC3]], [[TRUNC4]]
@@ -758,16 +670,13 @@ body: |
; SI: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[TRUNC1]], [[C2]]
; SI: [[AND5:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C1]]
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[ZEXT2]](s32)
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ZEXT2]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C4]]
- ; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY10]](s32)
+ ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C4]]
+ ; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY6]](s32)
; SI: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C4]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C4]]
; SI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[ZEXT3]](s32)
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR9]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC5]], [[TRUNC6]]
@@ -775,16 +684,13 @@ body: |
; SI: [[XOR2:%[0-9]+]]:_(s16) = G_XOR [[TRUNC2]], [[C2]]
; SI: [[AND9:%[0-9]+]]:_(s16) = G_AND [[XOR2]], [[C1]]
; SI: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[AND8]](s16)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY13]], [[ZEXT4]](s32)
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[ZEXT4]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C4]]
- ; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY14]](s32)
+ ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C4]]
+ ; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY7]](s32)
; SI: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[AND9]](s16)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C4]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C4]]
; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[ZEXT5]](s32)
; SI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR11]](s32)
; SI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[TRUNC7]], [[TRUNC8]]
@@ -802,15 +708,12 @@ body: |
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ZEXT6]], [[SHL3]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; SI: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C4]]
+ ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C4]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT8]], [[SHL4]]
; SI: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C4]]
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C4]]
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C4]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C4]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND13]], [[SHL5]]
; SI: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
@@ -886,15 +789,12 @@ body: |
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C4]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C4]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; VI: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C4]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C4]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL5]]
; VI: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
@@ -914,60 +814,51 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[DEF1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
+ ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[DEF1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[COPY6]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY2]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY3]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[DEF1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST2]](s32), [[LSHR2]](s32)
+ ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[DEF1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST3]](s32), [[COPY7]](s32)
; GFX9: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[COPY4]](<2 x s16>)
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; GFX9: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[COPY5]](<2 x s16>)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST4]](s32), [[LSHR4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST5]](s32), [[DEF1]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[C1]](s32)
+ ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[C1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[BUILD_VECTOR_TRUNC4]], [[BUILD_VECTOR_TRUNC6]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[C2]](s32)
+ ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[C2]](s32)
; GFX9: [[XOR:%[0-9]+]]:_(<2 x s16>) = G_XOR [[BUILD_VECTOR_TRUNC4]], [[BUILD_VECTOR_TRUNC7]]
; GFX9: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[XOR]], [[BUILD_VECTOR_TRUNC6]]
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[C3]](s32)
+ ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[C3]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC]], [[AND]](<2 x s16>)
; GFX9: [[LSHR6:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[BUILD_VECTOR_TRUNC2]], [[BUILD_VECTOR_TRUNC8]](<2 x s16>)
; GFX9: [[LSHR7:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[LSHR6]], [[AND1]](<2 x s16>)
; GFX9: [[OR:%[0-9]+]]:_(<2 x s16>) = G_OR [[SHL]], [[LSHR7]]
- ; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC9:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
+ ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC9:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
; GFX9: [[AND2:%[0-9]+]]:_(<2 x s16>) = G_AND [[BUILD_VECTOR_TRUNC5]], [[BUILD_VECTOR_TRUNC9]]
- ; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC10:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
+ ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC10:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX9: [[XOR1:%[0-9]+]]:_(<2 x s16>) = G_XOR [[BUILD_VECTOR_TRUNC5]], [[BUILD_VECTOR_TRUNC10]]
; GFX9: [[AND3:%[0-9]+]]:_(<2 x s16>) = G_AND [[XOR1]], [[BUILD_VECTOR_TRUNC9]]
- ; GFX9: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; GFX9: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC11:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY24]](s32), [[COPY25]](s32)
+ ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC11:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC1]], [[AND2]](<2 x s16>)
; GFX9: [[LSHR8:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[BUILD_VECTOR_TRUNC3]], [[BUILD_VECTOR_TRUNC11]](<2 x s16>)
; GFX9: [[LSHR9:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[LSHR8]], [[AND3]](<2 x s16>)
@@ -983,15 +874,9 @@ body: |
; GFX9: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST8]], [[C]](s32)
; GFX9: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C]](s32)
- ; GFX9: [[COPY26:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; GFX9: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC12:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY26]](s32), [[COPY27]](s32)
- ; GFX9: [[COPY28:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; GFX9: [[COPY29:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC13:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY28]](s32), [[COPY29]](s32)
- ; GFX9: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; GFX9: [[COPY31:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC14:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY30]](s32), [[COPY31]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC12:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST6]](s32), [[LSHR10]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC13:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST7]](s32), [[BITCAST8]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC14:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR12]](s32), [[BITCAST9]](s32)
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC12]](<2 x s16>)
; GFX9: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC13]](<2 x s16>)
; GFX9: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC14]](<2 x s16>)
@@ -1053,17 +938,14 @@ body: |
; SI: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C2]]
; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C1]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[ZEXT]](s32)
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[ZEXT]](s32)
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C4]]
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32)
; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C4]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C4]]
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[ZEXT1]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR7]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC4]], [[TRUNC5]]
@@ -1071,16 +953,13 @@ body: |
; SI: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[TRUNC1]], [[C2]]
; SI: [[AND5:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C1]]
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[ZEXT2]](s32)
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ZEXT2]](s32)
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
- ; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY7]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C4]]
+ ; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY3]](s32)
; SI: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C4]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C4]]
; SI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[ZEXT3]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR9]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC6]], [[TRUNC7]]
@@ -1088,16 +967,13 @@ body: |
; SI: [[XOR2:%[0-9]+]]:_(s16) = G_XOR [[TRUNC2]], [[C2]]
; SI: [[AND9:%[0-9]+]]:_(s16) = G_AND [[XOR2]], [[C1]]
; SI: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[AND8]](s16)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY10]], [[ZEXT4]](s32)
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[ZEXT4]](s32)
; SI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C4]]
- ; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY11]](s32)
+ ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C4]]
+ ; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY4]](s32)
; SI: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[AND9]](s16)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C4]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C4]]
; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[ZEXT5]](s32)
; SI: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR11]](s32)
; SI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[TRUNC8]], [[TRUNC9]]
@@ -1105,16 +981,13 @@ body: |
; SI: [[XOR3:%[0-9]+]]:_(s16) = G_XOR [[TRUNC3]], [[C2]]
; SI: [[AND13:%[0-9]+]]:_(s16) = G_AND [[XOR3]], [[C1]]
; SI: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[AND12]](s16)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY14]], [[ZEXT6]](s32)
+ ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[ZEXT6]](s32)
; SI: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C4]]
- ; SI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY15]](s32)
+ ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
+ ; SI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY5]](s32)
; SI: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[AND13]](s16)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C4]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C4]]
; SI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND15]], [[ZEXT7]](s32)
; SI: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR13]](s32)
; SI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[TRUNC10]], [[TRUNC11]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
index 6ce6844f338f8..2de3ade06c48e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
@@ -98,16 +98,13 @@ body: |
; SI: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[C1]]
; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C2]](s32)
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s32)
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[ZEXT]](s32)
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[ZEXT]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[ZEXT1]](s32)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC1]], [[TRUNC2]]
@@ -184,17 +181,14 @@ body: |
; SI: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[C]], [[C3]]
; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C2]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[ZEXT]](s32)
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[ZEXT]](s32)
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C4]](s32)
; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C5]]
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[ZEXT1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC]], [[TRUNC1]]
@@ -202,31 +196,26 @@ body: |
; SI: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[C]], [[C3]]
; SI: [[AND5:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C2]]
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[ZEXT2]](s32)
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ZEXT2]](s32)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C5]]
- ; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY7]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]]
+ ; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY3]](s32)
; SI: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C5]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C5]]
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[ZEXT3]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC2]], [[TRUNC3]]
; SI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C1]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY11]], [[COPY10]](s32)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY13]], [[COPY12]](s32)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY15]], [[C1]](s32)
- ; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[COPY14]], [[SHL4]]
+ ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST2]], [[COPY4]](s32)
+ ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR6]], [[COPY5]](s32)
+ ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C1]](s32)
+ ; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[COPY6]], [[SHL4]]
; SI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; SI: [[XOR2:%[0-9]+]]:_(<2 x s16>) = G_XOR [[COPY2]], [[BITCAST3]]
; SI: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[XOR2]](<2 x s16>)
@@ -240,13 +229,11 @@ body: |
; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT]], [[ZEXT4]](s32)
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[SHL2]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C5]]
- ; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY16]](s32)
+ ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]]
+ ; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY8]](s32)
; SI: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[AND9]](s16)
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C5]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C5]]
; SI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[ZEXT5]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR9]](s32)
; SI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[TRUNC6]], [[TRUNC7]]
@@ -257,13 +244,11 @@ body: |
; SI: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[OR1]](s16)
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT1]], [[ZEXT6]](s32)
; SI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[SHL3]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C5]]
- ; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY19]](s32)
+ ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C5]]
+ ; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY9]](s32)
; SI: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[AND13]](s16)
- ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C5]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C5]]
; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND15]], [[ZEXT7]](s32)
; SI: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR11]](s32)
; SI: [[OR4:%[0-9]+]]:_(s16) = G_OR [[TRUNC8]], [[TRUNC9]]
@@ -442,114 +427,77 @@ body: |
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[COPY4]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY5]], [[COPY6]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[COPY8]]
+ ; SI: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY10]], [[AND2]](s32)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY12]], [[AND3]](s32)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
- ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[AND4]](s32)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[COPY16]]
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; SI: $vgpr0 = COPY [[COPY17]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY3]](s32)
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND1]], [[C3]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND2]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[AND3]](s32)
+ ; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
+ ; SI: $vgpr0 = COPY [[OR]](s32)
; VI-LABEL: name: test_fshr_s8_s8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[COPY4]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; VI: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY5]], [[COPY6]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[COPY8]]
+ ; VI: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
+ ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND2]](s32)
+ ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
- ; VI: [[COPY11:%[0-9]+]]:_(s16) = COPY [[SHL]](s16)
- ; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[AND3]](s32)
- ; VI: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[COPY11]], [[TRUNC2]](s16)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND1]], [[C3]]
+ ; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[AND2]](s32)
+ ; VI: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[SHL]], [[TRUNC2]](s16)
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; VI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C4]]
- ; VI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[AND4]](s32)
- ; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND5]], [[TRUNC4]](s16)
+ ; VI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C4]]
+ ; VI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[AND3]](s32)
+ ; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND4]], [[TRUNC4]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL1]](s16)
; VI: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; VI: $vgpr0 = COPY [[COPY13]](s32)
+ ; VI: $vgpr0 = COPY [[OR]](s32)
; GFX9-LABEL: name: test_fshr_s8_s8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[COPY4]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY5]], [[COPY6]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[COPY8]]
+ ; GFX9: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
+ ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND2]](s32)
+ ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s16) = COPY [[SHL]](s16)
- ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[AND3]](s32)
- ; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[COPY11]], [[TRUNC2]](s16)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[AND1]], [[C3]]
+ ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[AND2]](s32)
+ ; GFX9: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[SHL]], [[TRUNC2]](s16)
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C4]]
- ; GFX9: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[AND4]](s32)
- ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND5]], [[TRUNC4]](s16)
+ ; GFX9: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C4]]
+ ; GFX9: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[AND3]](s32)
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND4]], [[TRUNC4]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL1]](s16)
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[ANYEXT]], [[ANYEXT1]]
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY13]](s32)
+ ; GFX9: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2
@@ -574,51 +522,38 @@ body: |
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
- ; SI: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; SI: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY3]](s32)
; SI: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; SI: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
; SI: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[AND1]]
+ ; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[COPY3]]
; SI: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SUB]], [[FPTOUI]]
; SI: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI]], [[MUL]]
; SI: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI]], [[UMULH]]
; SI: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[ADD]]
- ; SI: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[AND1]]
+ ; SI: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[COPY3]]
; SI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[MUL1]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[AND1]]
- ; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND1]]
+ ; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[COPY3]]
+ ; SI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY3]]
; SI: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
- ; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
- ; SI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
+ ; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[COPY3]]
+ ; SI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY3]]
; SI: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; SI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY5]], [[COPY6]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[AND2]](s32)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C2]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY10]], [[AND3]](s32)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C2]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C2]]
- ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[AND4]](s32)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY13]], [[COPY14]]
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; SI: $vgpr0 = COPY [[COPY15]](s32)
+ ; SI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
+ ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY4]](s32)
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
+ ; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
+ ; SI: $vgpr0 = COPY [[OR]](s32)
; VI-LABEL: name: test_fshr_s24_s24
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -626,51 +561,38 @@ body: |
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
- ; VI: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; VI: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY3]](s32)
; VI: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
; VI: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; VI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[AND1]]
+ ; VI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[COPY3]]
; VI: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SUB]], [[FPTOUI]]
; VI: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI]], [[MUL]]
; VI: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI]], [[UMULH]]
; VI: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[ADD]]
- ; VI: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[AND1]]
+ ; VI: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[COPY3]]
; VI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[MUL1]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[AND1]]
- ; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND1]]
+ ; VI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[COPY3]]
+ ; VI: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY3]]
; VI: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
- ; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
- ; VI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
+ ; VI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[COPY3]]
+ ; VI: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY3]]
; VI: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; VI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY5]], [[COPY6]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[AND2]](s32)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C2]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY10]], [[AND3]](s32)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C2]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C2]]
- ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[AND4]](s32)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY13]], [[COPY14]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; VI: $vgpr0 = COPY [[COPY15]](s32)
+ ; VI: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
+ ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY4]](s32)
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
+ ; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
+ ; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
+ ; VI: $vgpr0 = COPY [[OR]](s32)
; GFX9-LABEL: name: test_fshr_s24_s24
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -678,51 +600,38 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
- ; GFX9: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX9: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY3]](s32)
; GFX9: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
; GFX9: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[AMDGPU_RCP_IFLAG]], [[C3]]
; GFX9: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMUL]](s32)
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[AND1]]
+ ; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[COPY3]]
; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SUB]], [[FPTOUI]]
; GFX9: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[FPTOUI]], [[MUL]]
; GFX9: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOUI]], [[UMULH]]
; GFX9: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[ADD]]
- ; GFX9: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[AND1]]
+ ; GFX9: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[UMULH1]], [[COPY3]]
; GFX9: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[MUL1]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[AND1]]
- ; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND1]]
+ ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SUB1]](s32), [[COPY3]]
+ ; GFX9: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[COPY3]]
; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SUB2]], [[SUB1]]
- ; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
- ; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
+ ; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[COPY3]]
+ ; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[COPY3]]
; GFX9: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY5]], [[COPY6]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[AND2]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C2]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY10]], [[AND3]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C2]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C2]]
- ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[AND4]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY13]], [[COPY14]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY15]](s32)
+ ; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SELECT1]]
+ ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY4]](s32)
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C2]]
+ ; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND1]](s32)
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C2]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
+ ; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]]
+ ; GFX9: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2
@@ -762,18 +671,15 @@ body: |
; SI: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[COPY5]](<2 x s16>)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C]](s32)
+ ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; SI: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
@@ -783,16 +689,13 @@ body: |
; SI: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[C3]], [[C5]]
; SI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C4]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND3]](s16)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY10]], [[ZEXT]](s32)
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[ZEXT]](s32)
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C6]](s32)
; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[ZEXT1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR7]](s32)
; SI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[TRUNC]], [[TRUNC1]]
@@ -800,29 +703,24 @@ body: |
; SI: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[C3]], [[C5]]
; SI: [[AND8:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C4]]
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND7]](s16)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY13]], [[ZEXT2]](s32)
+ ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ZEXT2]](s32)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C1]]
- ; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[COPY14]](s32)
+ ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[COPY7]](s32)
; SI: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND8]](s16)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C1]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C1]]
; SI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[ZEXT3]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR9]](s32)
; SI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[TRUNC2]], [[TRUNC3]]
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[COPY17]](s32)
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[COPY19]](s32)
- ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY22]], [[C]](s32)
- ; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[COPY21]], [[SHL6]]
+ ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[BITCAST2]], [[COPY8]](s32)
+ ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[COPY9]](s32)
+ ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY11]], [[C]](s32)
+ ; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[COPY10]], [[SHL6]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
; SI: [[XOR2:%[0-9]+]]:_(<2 x s16>) = G_XOR [[BITCAST6]], [[BITCAST8]]
; SI: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[XOR2]](<2 x s16>)
@@ -836,13 +734,11 @@ body: |
; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR2]](s16)
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT]], [[ZEXT4]](s32)
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL7]](s32)
- ; SI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; SI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[SHL4]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C1]]
- ; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND13]], [[COPY23]](s32)
+ ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[SHL4]], [[C1]]
+ ; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND13]], [[COPY12]](s32)
; SI: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[AND12]](s16)
- ; SI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C1]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C1]]
; SI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[ZEXT5]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR12]](s32)
; SI: [[OR5:%[0-9]+]]:_(s16) = G_OR [[TRUNC6]], [[TRUNC7]]
@@ -853,13 +749,11 @@ body: |
; SI: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[OR3]](s16)
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT1]], [[ZEXT6]](s32)
; SI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
- ; SI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; SI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[SHL5]](s32)
- ; SI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C1]]
- ; SI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND17]], [[COPY26]](s32)
+ ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; SI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[SHL5]], [[C1]]
+ ; SI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND17]], [[COPY13]](s32)
; SI: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[AND16]](s16)
- ; SI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; SI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C1]]
+ ; SI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C1]]
; SI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[AND18]], [[ZEXT7]](s32)
; SI: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR14]](s32)
; SI: [[OR6:%[0-9]+]]:_(s16) = G_OR [[TRUNC8]], [[TRUNC9]]
@@ -872,16 +766,13 @@ body: |
; SI: [[XOR5:%[0-9]+]]:_(s16) = G_XOR [[C3]], [[C5]]
; SI: [[AND20:%[0-9]+]]:_(s16) = G_AND [[XOR5]], [[C4]]
; SI: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[AND19]](s16)
- ; SI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[COPY29]], [[ZEXT10]](s32)
+ ; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[ZEXT10]](s32)
; SI: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[SHL10]](s32)
- ; SI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; SI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C1]]
- ; SI: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[AND21]], [[COPY30]](s32)
+ ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; SI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[AND21]], [[COPY14]](s32)
; SI: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[AND20]](s16)
- ; SI: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; SI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C1]]
+ ; SI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C1]]
; SI: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[AND22]], [[ZEXT11]](s32)
; SI: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR16]](s32)
; SI: [[OR8:%[0-9]+]]:_(s16) = G_OR [[TRUNC10]], [[TRUNC11]]
@@ -892,24 +783,22 @@ body: |
; SI: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[DEF1]], [[ZEXT12]](s32)
; SI: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[SHL11]](s32)
- ; SI: [[COPY33:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; SI: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[C2]], [[COPY33]](s32)
+ ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; SI: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[C2]], [[COPY15]](s32)
; SI: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[AND24]](s16)
- ; SI: [[COPY34:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; SI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY34]], [[C1]]
+ ; SI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LSHR17]], [[C1]]
; SI: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[AND25]], [[ZEXT13]](s32)
; SI: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR18]](s32)
; SI: [[OR9:%[0-9]+]]:_(s16) = G_OR [[TRUNC12]], [[TRUNC13]]
- ; SI: [[COPY35:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; SI: [[COPY36:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[COPY36]], [[COPY35]](s32)
- ; SI: [[COPY37:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; SI: [[COPY38:%[0-9]+]]:_(s32) = COPY [[DEF1]](s32)
- ; SI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[COPY38]], [[COPY37]](s32)
- ; SI: [[COPY39:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[COPY40:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[COPY40]], [[C]](s32)
- ; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[COPY39]], [[SHL14]]
+ ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; SI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[BITCAST3]], [[COPY16]](s32)
+ ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[DEF1]](s32)
+ ; SI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[COPY17]](s32)
+ ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; SI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C]](s32)
+ ; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[COPY19]], [[SHL14]]
; SI: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR10]](s32)
; SI: [[XOR7:%[0-9]+]]:_(<2 x s16>) = G_XOR [[BITCAST7]], [[BITCAST11]]
; SI: [[BITCAST12:%[0-9]+]]:_(s32) = G_BITCAST [[XOR7]](<2 x s16>)
@@ -923,13 +812,11 @@ body: |
; SI: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[OR8]](s16)
; SI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT2]], [[ZEXT14]](s32)
; SI: [[TRUNC16:%[0-9]+]]:_(s16) = G_TRUNC [[SHL15]](s32)
- ; SI: [[COPY41:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; SI: [[COPY42:%[0-9]+]]:_(s32) = COPY [[SHL12]](s32)
- ; SI: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY42]], [[C1]]
- ; SI: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[AND28]], [[COPY41]](s32)
+ ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; SI: [[AND28:%[0-9]+]]:_(s32) = G_AND [[SHL12]], [[C1]]
+ ; SI: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[AND28]], [[COPY21]](s32)
; SI: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[AND27]](s16)
- ; SI: [[COPY43:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; SI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY43]], [[C1]]
+ ; SI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LSHR20]], [[C1]]
; SI: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[AND29]], [[ZEXT15]](s32)
; SI: [[TRUNC17:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR21]](s32)
; SI: [[OR11:%[0-9]+]]:_(s16) = G_OR [[TRUNC16]], [[TRUNC17]]
@@ -940,13 +827,11 @@ body: |
; SI: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[OR9]](s16)
; SI: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT3]], [[ZEXT16]](s32)
; SI: [[TRUNC18:%[0-9]+]]:_(s16) = G_TRUNC [[SHL16]](s32)
- ; SI: [[COPY44:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; SI: [[COPY45:%[0-9]+]]:_(s32) = COPY [[SHL13]](s32)
- ; SI: [[AND32:%[0-9]+]]:_(s32) = G_AND [[COPY45]], [[C1]]
- ; SI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[AND32]], [[COPY44]](s32)
+ ; SI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; SI: [[AND32:%[0-9]+]]:_(s32) = G_AND [[SHL13]], [[C1]]
+ ; SI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[AND32]], [[COPY22]](s32)
; SI: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[AND31]](s16)
- ; SI: [[COPY46:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; SI: [[AND33:%[0-9]+]]:_(s32) = G_AND [[COPY46]], [[C1]]
+ ; SI: [[AND33:%[0-9]+]]:_(s32) = G_AND [[LSHR22]], [[C1]]
; SI: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[AND33]], [[ZEXT17]](s32)
; SI: [[TRUNC19:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR23]](s32)
; SI: [[OR12:%[0-9]+]]:_(s16) = G_OR [[TRUNC18]], [[TRUNC19]]
@@ -966,24 +851,18 @@ body: |
; SI: [[LSHR26:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST16]], [[C]](s32)
; SI: [[BITCAST17:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; SI: [[LSHR27:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST17]], [[C]](s32)
- ; SI: [[COPY47:%[0-9]+]]:_(s32) = COPY [[BITCAST14]](s32)
- ; SI: [[AND34:%[0-9]+]]:_(s32) = G_AND [[COPY47]], [[C1]]
- ; SI: [[COPY48:%[0-9]+]]:_(s32) = COPY [[LSHR24]](s32)
- ; SI: [[AND35:%[0-9]+]]:_(s32) = G_AND [[COPY48]], [[C1]]
+ ; SI: [[AND34:%[0-9]+]]:_(s32) = G_AND [[BITCAST14]], [[C1]]
+ ; SI: [[AND35:%[0-9]+]]:_(s32) = G_AND [[LSHR24]], [[C1]]
; SI: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND35]], [[C]](s32)
; SI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[AND34]], [[SHL18]]
; SI: [[BITCAST18:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR14]](s32)
- ; SI: [[COPY49:%[0-9]+]]:_(s32) = COPY [[BITCAST15]](s32)
- ; SI: [[AND36:%[0-9]+]]:_(s32) = G_AND [[COPY49]], [[C1]]
- ; SI: [[COPY50:%[0-9]+]]:_(s32) = COPY [[BITCAST16]](s32)
- ; SI: [[AND37:%[0-9]+]]:_(s32) = G_AND [[COPY50]], [[C1]]
+ ; SI: [[AND36:%[0-9]+]]:_(s32) = G_AND [[BITCAST15]], [[C1]]
+ ; SI: [[AND37:%[0-9]+]]:_(s32) = G_AND [[BITCAST16]], [[C1]]
; SI: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND37]], [[C]](s32)
; SI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND36]], [[SHL19]]
; SI: [[BITCAST19:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR15]](s32)
- ; SI: [[COPY51:%[0-9]+]]:_(s32) = COPY [[LSHR26]](s32)
- ; SI: [[AND38:%[0-9]+]]:_(s32) = G_AND [[COPY51]], [[C1]]
- ; SI: [[COPY52:%[0-9]+]]:_(s32) = COPY [[BITCAST17]](s32)
- ; SI: [[AND39:%[0-9]+]]:_(s32) = G_AND [[COPY52]], [[C1]]
+ ; SI: [[AND38:%[0-9]+]]:_(s32) = G_AND [[LSHR26]], [[C1]]
+ ; SI: [[AND39:%[0-9]+]]:_(s32) = G_AND [[BITCAST17]], [[C1]]
; SI: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND39]], [[C]](s32)
; SI: [[OR16:%[0-9]+]]:_(s32) = G_OR [[AND38]], [[SHL20]]
; SI: [[BITCAST20:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR16]](s32)
@@ -1019,15 +898,12 @@ body: |
; VI: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[COPY5]](<2 x s16>)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
@@ -1051,9 +927,9 @@ body: |
; VI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[SHL3]], [[LSHR9]]
; VI: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[C3]](s16)
; VI: [[SHL5:%[0-9]+]]:_(s16) = G_SHL [[TRUNC4]], [[C3]](s16)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C]](s32)
- ; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[COPY9]], [[SHL6]]
+ ; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[COPY6]], [[SHL6]]
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
; VI: [[XOR2:%[0-9]+]]:_(<2 x s16>) = G_XOR [[BITCAST6]], [[BITCAST8]]
; VI: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[XOR2]](<2 x s16>)
@@ -1095,10 +971,10 @@ body: |
; VI: [[OR9:%[0-9]+]]:_(s16) = G_OR [[SHL11]], [[LSHR18]]
; VI: [[SHL12:%[0-9]+]]:_(s16) = G_SHL [[TRUNC5]], [[C3]](s16)
; VI: [[SHL13:%[0-9]+]]:_(s16) = G_SHL [[DEF1]], [[C3]](s16)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; VI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[COPY11]], [[C]](s32)
- ; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[COPY10]], [[SHL14]]
+ ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; VI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C]](s32)
+ ; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[COPY7]], [[SHL14]]
; VI: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR10]](s32)
; VI: [[XOR7:%[0-9]+]]:_(<2 x s16>) = G_XOR [[BITCAST7]], [[BITCAST11]]
; VI: [[BITCAST12:%[0-9]+]]:_(s32) = G_BITCAST [[XOR7]](<2 x s16>)
@@ -1135,24 +1011,18 @@ body: |
; VI: [[LSHR26:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST16]], [[C]](s32)
; VI: [[BITCAST17:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; VI: [[LSHR27:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST17]], [[C]](s32)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST14]](s32)
- ; VI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR24]](s32)
- ; VI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; VI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[BITCAST14]], [[C1]]
+ ; VI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LSHR24]], [[C1]]
; VI: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND20]], [[C]](s32)
; VI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[AND19]], [[SHL18]]
; VI: [[BITCAST18:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR14]](s32)
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST15]](s32)
- ; VI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C1]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[BITCAST16]](s32)
- ; VI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C1]]
+ ; VI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[BITCAST15]], [[C1]]
+ ; VI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[BITCAST16]], [[C1]]
; VI: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C]](s32)
; VI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND21]], [[SHL19]]
; VI: [[BITCAST19:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR15]](s32)
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR26]](s32)
- ; VI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C1]]
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[BITCAST17]](s32)
- ; VI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C1]]
+ ; VI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR26]], [[C1]]
+ ; VI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[BITCAST17]], [[C1]]
; VI: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C]](s32)
; VI: [[OR16:%[0-9]+]]:_(s32) = G_OR [[AND23]], [[SHL20]]
; VI: [[BITCAST20:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR16]](s32)
@@ -1172,60 +1042,51 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[DEF1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
+ ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[DEF1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[COPY6]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY2]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY3]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[DEF1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST2]](s32), [[LSHR2]](s32)
+ ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[DEF1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST3]](s32), [[COPY7]](s32)
; GFX9: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[COPY4]](<2 x s16>)
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; GFX9: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[COPY5]](<2 x s16>)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST4]](s32), [[LSHR4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST5]](s32), [[DEF1]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[C1]](s32)
+ ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[C1]](s32)
; GFX9: [[AND:%[0-9]+]]:_(<2 x s16>) = G_AND [[BUILD_VECTOR_TRUNC4]], [[BUILD_VECTOR_TRUNC6]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[C2]](s32)
+ ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[C2]](s32)
; GFX9: [[XOR:%[0-9]+]]:_(<2 x s16>) = G_XOR [[BUILD_VECTOR_TRUNC4]], [[BUILD_VECTOR_TRUNC7]]
; GFX9: [[AND1:%[0-9]+]]:_(<2 x s16>) = G_AND [[XOR]], [[BUILD_VECTOR_TRUNC6]]
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[C3]](s32)
+ ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[C3]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC8]](<2 x s16>)
; GFX9: [[SHL1:%[0-9]+]]:_(<2 x s16>) = G_SHL [[SHL]], [[AND1]](<2 x s16>)
; GFX9: [[LSHR6:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[BUILD_VECTOR_TRUNC2]], [[AND]](<2 x s16>)
; GFX9: [[OR:%[0-9]+]]:_(<2 x s16>) = G_OR [[SHL1]], [[LSHR6]]
- ; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC9:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
+ ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC9:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
; GFX9: [[AND2:%[0-9]+]]:_(<2 x s16>) = G_AND [[BUILD_VECTOR_TRUNC5]], [[BUILD_VECTOR_TRUNC9]]
- ; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC10:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
+ ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC10:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX9: [[XOR1:%[0-9]+]]:_(<2 x s16>) = G_XOR [[BUILD_VECTOR_TRUNC5]], [[BUILD_VECTOR_TRUNC10]]
; GFX9: [[AND3:%[0-9]+]]:_(<2 x s16>) = G_AND [[XOR1]], [[BUILD_VECTOR_TRUNC9]]
- ; GFX9: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; GFX9: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC11:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY24]](s32), [[COPY25]](s32)
+ ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC11:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
; GFX9: [[SHL2:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC11]](<2 x s16>)
; GFX9: [[SHL3:%[0-9]+]]:_(<2 x s16>) = G_SHL [[SHL2]], [[AND3]](<2 x s16>)
; GFX9: [[LSHR7:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[BUILD_VECTOR_TRUNC3]], [[AND2]](<2 x s16>)
@@ -1241,15 +1102,9 @@ body: |
; GFX9: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST8]], [[C]](s32)
; GFX9: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C]](s32)
- ; GFX9: [[COPY26:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; GFX9: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC12:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY26]](s32), [[COPY27]](s32)
- ; GFX9: [[COPY28:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; GFX9: [[COPY29:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC13:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY28]](s32), [[COPY29]](s32)
- ; GFX9: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; GFX9: [[COPY31:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC14:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY30]](s32), [[COPY31]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC12:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST6]](s32), [[LSHR8]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC13:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST7]](s32), [[BITCAST8]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC14:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR10]](s32), [[BITCAST9]](s32)
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC12]](<2 x s16>)
; GFX9: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC13]](<2 x s16>)
; GFX9: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC14]](<2 x s16>)
@@ -1300,17 +1155,14 @@ body: |
; SI: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[C]], [[C3]]
; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[XOR]], [[C2]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[AND]](s16)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[ZEXT]](s32)
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[ZEXT]](s32)
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C4]](s32)
; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[AND1]](s16)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C5]]
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[ZEXT1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR3]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC]], [[TRUNC1]]
@@ -1318,31 +1170,26 @@ body: |
; SI: [[XOR1:%[0-9]+]]:_(s16) = G_XOR [[C]], [[C3]]
; SI: [[AND5:%[0-9]+]]:_(s16) = G_AND [[XOR1]], [[C2]]
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[AND4]](s16)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[ZEXT2]](s32)
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[ZEXT2]](s32)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C5]]
- ; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY7]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]]
+ ; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY3]](s32)
; SI: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[AND5]](s16)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C5]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C5]]
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[ZEXT3]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[TRUNC2]], [[TRUNC3]]
; SI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C1]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY11]], [[COPY10]](s32)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY13]], [[COPY12]](s32)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY15]], [[C1]](s32)
- ; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[COPY14]], [[SHL4]]
+ ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST2]], [[COPY4]](s32)
+ ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR6]], [[COPY5]](s32)
+ ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C1]](s32)
+ ; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[COPY6]], [[SHL4]]
; SI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; SI: [[XOR2:%[0-9]+]]:_(<2 x s16>) = G_XOR [[UV4]], [[BITCAST3]]
; SI: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[XOR2]](<2 x s16>)
@@ -1356,13 +1203,11 @@ body: |
; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT]], [[ZEXT4]](s32)
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[SHL2]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C5]]
- ; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY16]](s32)
+ ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C5]]
+ ; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY8]](s32)
; SI: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[AND9]](s16)
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C5]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C5]]
; SI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[ZEXT5]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR9]](s32)
; SI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[TRUNC6]], [[TRUNC7]]
@@ -1373,13 +1218,11 @@ body: |
; SI: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[OR1]](s16)
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT1]], [[ZEXT6]](s32)
; SI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[SHL3]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C5]]
- ; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY19]](s32)
+ ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C5]]
+ ; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY9]](s32)
; SI: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[AND13]](s16)
- ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C5]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C5]]
; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND15]], [[ZEXT7]](s32)
; SI: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR11]](s32)
; SI: [[OR4:%[0-9]+]]:_(s16) = G_OR [[TRUNC8]], [[TRUNC9]]
@@ -1396,16 +1239,13 @@ body: |
; SI: [[XOR5:%[0-9]+]]:_(s16) = G_XOR [[C]], [[C3]]
; SI: [[AND17:%[0-9]+]]:_(s16) = G_AND [[XOR5]], [[C2]]
; SI: [[ZEXT10:%[0-9]+]]:_(s32) = G_ZEXT [[AND16]](s16)
- ; SI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[COPY22]], [[ZEXT10]](s32)
+ ; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[BITCAST6]], [[ZEXT10]](s32)
; SI: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
- ; SI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; SI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C5]]
- ; SI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[AND18]], [[COPY23]](s32)
+ ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; SI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C5]]
+ ; SI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[AND18]], [[COPY10]](s32)
; SI: [[ZEXT11:%[0-9]+]]:_(s32) = G_ZEXT [[AND17]](s16)
- ; SI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; SI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C5]]
+ ; SI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C5]]
; SI: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[AND19]], [[ZEXT11]](s32)
; SI: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR15]](s32)
; SI: [[OR6:%[0-9]+]]:_(s16) = G_OR [[TRUNC10]], [[TRUNC11]]
@@ -1413,31 +1253,26 @@ body: |
; SI: [[XOR6:%[0-9]+]]:_(s16) = G_XOR [[C]], [[C3]]
; SI: [[AND21:%[0-9]+]]:_(s16) = G_AND [[XOR6]], [[C2]]
; SI: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[AND20]](s16)
- ; SI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[COPY26]], [[ZEXT12]](s32)
+ ; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[LSHR12]], [[ZEXT12]](s32)
; SI: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[SHL9]](s32)
- ; SI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; SI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C5]]
- ; SI: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[AND22]], [[COPY27]](s32)
+ ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; SI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C5]]
+ ; SI: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[AND22]], [[COPY11]](s32)
; SI: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[AND21]](s16)
- ; SI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; SI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C5]]
+ ; SI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR16]], [[C5]]
; SI: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[AND23]], [[ZEXT13]](s32)
; SI: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR17]](s32)
; SI: [[OR7:%[0-9]+]]:_(s16) = G_OR [[TRUNC12]], [[TRUNC13]]
; SI: [[BITCAST8:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST8]], [[C1]](s32)
- ; SI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
- ; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[COPY31]], [[COPY30]](s32)
- ; SI: [[COPY32:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI: [[COPY33:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[COPY33]], [[COPY32]](s32)
- ; SI: [[COPY34:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; SI: [[COPY35:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; SI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[COPY35]], [[C1]](s32)
- ; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[COPY34]], [[SHL12]]
+ ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[BITCAST8]], [[COPY12]](s32)
+ ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[LSHR18]], [[COPY13]](s32)
+ ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; SI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[COPY15]], [[C1]](s32)
+ ; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[COPY14]], [[SHL12]]
; SI: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR8]](s32)
; SI: [[XOR7:%[0-9]+]]:_(<2 x s16>) = G_XOR [[UV5]], [[BITCAST9]]
; SI: [[BITCAST10:%[0-9]+]]:_(s32) = G_BITCAST [[XOR7]](<2 x s16>)
@@ -1451,13 +1286,11 @@ body: |
; SI: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[OR6]](s16)
; SI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT2]], [[ZEXT14]](s32)
; SI: [[TRUNC16:%[0-9]+]]:_(s16) = G_TRUNC [[SHL13]](s32)
- ; SI: [[COPY36:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI: [[COPY37:%[0-9]+]]:_(s32) = COPY [[SHL10]](s32)
- ; SI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY37]], [[C5]]
- ; SI: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[AND26]], [[COPY36]](s32)
+ ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; SI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[SHL10]], [[C5]]
+ ; SI: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[AND26]], [[COPY16]](s32)
; SI: [[ZEXT15:%[0-9]+]]:_(s32) = G_ZEXT [[AND25]](s16)
- ; SI: [[COPY38:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; SI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY38]], [[C5]]
+ ; SI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LSHR20]], [[C5]]
; SI: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[AND27]], [[ZEXT15]](s32)
; SI: [[TRUNC17:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR21]](s32)
; SI: [[OR9:%[0-9]+]]:_(s16) = G_OR [[TRUNC16]], [[TRUNC17]]
@@ -1468,13 +1301,11 @@ body: |
; SI: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[OR7]](s16)
; SI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT3]], [[ZEXT16]](s32)
; SI: [[TRUNC18:%[0-9]+]]:_(s16) = G_TRUNC [[SHL14]](s32)
- ; SI: [[COPY39:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; SI: [[COPY40:%[0-9]+]]:_(s32) = COPY [[SHL11]](s32)
- ; SI: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY40]], [[C5]]
- ; SI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[AND30]], [[COPY39]](s32)
+ ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; SI: [[AND30:%[0-9]+]]:_(s32) = G_AND [[SHL11]], [[C5]]
+ ; SI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[AND30]], [[COPY17]](s32)
; SI: [[ZEXT17:%[0-9]+]]:_(s32) = G_ZEXT [[AND29]](s16)
- ; SI: [[COPY41:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; SI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY41]], [[C5]]
+ ; SI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LSHR22]], [[C5]]
; SI: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[AND31]], [[ZEXT17]](s32)
; SI: [[TRUNC19:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR23]](s32)
; SI: [[OR10:%[0-9]+]]:_(s16) = G_OR [[TRUNC18]], [[TRUNC19]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
index 35ae08787456f..a70073351c03a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
@@ -436,15 +436,12 @@ body: |
; SI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC2]](s16)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; SI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -492,15 +489,12 @@ body: |
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FADD2]](s16)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -545,11 +539,8 @@ body: |
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD1]](s16)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX9: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD2]](s16)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[BITCAST4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR4]](s32), [[BITCAST5]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
index 1844754e15210..c4ea7de36feb0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
@@ -75,8 +75,7 @@ body: |
; GFX7: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX7: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C1]](s32), [[AND]]
; GFX7: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C]], [[TRUNC]]
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
@@ -116,10 +115,8 @@ body: |
; GFX7: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
+ ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
+ ; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
; GFX7: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; GFX7: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX7: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C2]], [[TRUNC]]
@@ -130,10 +127,8 @@ body: |
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
+ ; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
; GFX8: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C2]], [[TRUNC]]
@@ -144,10 +139,8 @@ body: |
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
+ ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
; GFX9: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C2]], [[TRUNC]]
@@ -172,43 +165,28 @@ body: |
; GFX7: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
- ; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX7: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]]
- ; GFX7: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; GFX7: $vgpr0 = COPY [[COPY5]](s32)
+ ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
+ ; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
+ ; GFX7: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
+ ; GFX7: $vgpr0 = COPY [[SELECT]](s32)
; GFX8-LABEL: name: test_icmp_s24
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]]
- ; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; GFX8: $vgpr0 = COPY [[COPY5]](s32)
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
+ ; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
+ ; GFX8: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
+ ; GFX8: $vgpr0 = COPY [[SELECT]](s32)
; GFX9-LABEL: name: test_icmp_s24
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[COPY3]], [[COPY4]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY5]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
+ ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[AND]]
+ ; GFX9: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
+ ; GFX9: $vgpr0 = COPY [[SELECT]](s32)
%0:_(s24) = G_CONSTANT i24 0
%1:_(s32) = COPY $vgpr0
%2:_(s24) = G_TRUNC %1
@@ -232,10 +210,8 @@ body: |
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
+ ; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; GFX7: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s32>)
; GFX8-LABEL: name: test_icmp_v2s32
@@ -247,10 +223,8 @@ body: |
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; GFX8: S_NOP 0, implicit [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_icmp_v2s32
@@ -292,12 +266,9 @@ body: |
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX7: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+ ; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C]]
+ ; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C]]
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32)
; GFX7: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
; GFX8-LABEL: name: test_icmp_v3s32
@@ -312,12 +283,9 @@ body: |
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX8: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C]]
+ ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C]]
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32)
; GFX8: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
; GFX9-LABEL: name: test_icmp_v3s32
@@ -365,14 +333,10 @@ body: |
; GFX7: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
; GFX7: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP3]](s1)
; GFX7: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX7: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
- ; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
- ; GFX7: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+ ; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C]]
+ ; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C]]
+ ; GFX7: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C]]
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32)
; GFX7: S_NOP 0, implicit [[BUILD_VECTOR]](<4 x s32>)
; GFX8-LABEL: name: test_icmp_v4s32
@@ -390,14 +354,10 @@ body: |
; GFX8: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
; GFX8: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP3]](s1)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
- ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C]]
+ ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C]]
+ ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C]]
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32)
; GFX8: S_NOP 0, implicit [[BUILD_VECTOR]](<4 x s32>)
; GFX9-LABEL: name: test_icmp_v4s32
@@ -657,10 +617,8 @@ body: |
; GFX7: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p3), [[UV3]]
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
- ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX7: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
- ; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX7: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
+ ; GFX7: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
+ ; GFX7: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX7: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX8-LABEL: name: test_icmp_v2p3
@@ -672,10 +630,8 @@ body: |
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p3), [[UV3]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_icmp_v2p3
@@ -712,10 +668,8 @@ body: |
; GFX7: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p999), [[UV3]]
; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX7: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
- ; GFX7: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX7: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
- ; GFX7: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX7: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
+ ; GFX7: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
+ ; GFX7: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; GFX7: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX7: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX8-LABEL: name: test_icmp_v2p999
@@ -727,10 +681,8 @@ body: |
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p999), [[UV3]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_icmp_v2p999
@@ -769,15 +721,11 @@ body: |
; GFX7: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX7: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX7: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX7: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; GFX7: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; GFX7: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; GFX7: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s32), [[AND1]]
- ; GFX7: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; GFX7: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX7: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; GFX7: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX7: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; GFX7: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND2]](s32), [[AND3]]
; GFX7: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY2]](<2 x s32>)
; GFX7: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY3]](<2 x s32>)
@@ -846,32 +794,23 @@ body: |
; GFX7-LABEL: name: test_icmp_s33
; GFX7: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX7: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; GFX7: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
; GFX7: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
- ; GFX7: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; GFX7: [[COPY2:%[0-9]+]]:_(s64) = COPY [[C]](s64)
- ; GFX7: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C1]]
- ; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[AND1]]
+ ; GFX7: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s64), [[COPY2]]
; GFX7: S_ENDPGM 0, implicit [[ICMP]](s1)
; GFX8-LABEL: name: test_icmp_s33
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; GFX8: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
; GFX8: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
- ; GFX8: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; GFX8: [[COPY2:%[0-9]+]]:_(s64) = COPY [[C]](s64)
- ; GFX8: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C1]]
- ; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[AND1]]
+ ; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s64), [[COPY2]]
; GFX8: S_ENDPGM 0, implicit [[ICMP]](s1)
; GFX9-LABEL: name: test_icmp_s33
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
- ; GFX9: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C]](s64)
- ; GFX9: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C1]]
; GFX9: [[COPY2:%[0-9]+]]:_(s64) = COPY [[C]](s64)
- ; GFX9: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C1]]
- ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND]](s64), [[AND1]]
+ ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s64), [[COPY2]]
; GFX9: S_ENDPGM 0, implicit [[ICMP]](s1)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def-s1025.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def-s1025.mir
index 035140937c42d..71d36a320ccb0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def-s1025.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def-s1025.mir
@@ -14,278 +14,216 @@ body: |
; TAHITI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; TAHITI: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; TAHITI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; TAHITI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; TAHITI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; TAHITI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; TAHITI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY]](s32)
; TAHITI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; TAHITI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; TAHITI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; TAHITI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
- ; TAHITI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY2]](s32)
+ ; TAHITI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; TAHITI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
+ ; TAHITI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY1]](s32)
; TAHITI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; TAHITI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; TAHITI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; TAHITI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
- ; TAHITI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY4]](s32)
+ ; TAHITI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; TAHITI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
+ ; TAHITI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY2]](s32)
; TAHITI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; TAHITI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; TAHITI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; TAHITI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
- ; TAHITI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY6]](s32)
+ ; TAHITI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; TAHITI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
+ ; TAHITI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY3]](s32)
; TAHITI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; TAHITI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; TAHITI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; TAHITI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C2]]
- ; TAHITI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY8]](s32)
+ ; TAHITI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; TAHITI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
+ ; TAHITI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY4]](s32)
; TAHITI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
- ; TAHITI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
- ; TAHITI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; TAHITI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C2]]
- ; TAHITI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY10]](s32)
+ ; TAHITI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
+ ; TAHITI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
+ ; TAHITI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY5]](s32)
; TAHITI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; TAHITI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; TAHITI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; TAHITI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C2]]
- ; TAHITI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY12]](s32)
+ ; TAHITI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; TAHITI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
+ ; TAHITI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY6]](s32)
; TAHITI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; TAHITI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
- ; TAHITI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; TAHITI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C2]]
- ; TAHITI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY14]](s32)
+ ; TAHITI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
+ ; TAHITI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
+ ; TAHITI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY7]](s32)
; TAHITI: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
- ; TAHITI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
- ; TAHITI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; TAHITI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C2]]
- ; TAHITI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[COPY16]](s32)
+ ; TAHITI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
+ ; TAHITI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
+ ; TAHITI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[COPY8]](s32)
; TAHITI: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; TAHITI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
- ; TAHITI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; TAHITI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C2]]
- ; TAHITI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[COPY18]](s32)
+ ; TAHITI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
+ ; TAHITI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
+ ; TAHITI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[COPY9]](s32)
; TAHITI: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
- ; TAHITI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
- ; TAHITI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; TAHITI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C2]]
- ; TAHITI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY20]](s32)
+ ; TAHITI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
+ ; TAHITI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
+ ; TAHITI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY10]](s32)
; TAHITI: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; TAHITI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
- ; TAHITI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; TAHITI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C2]]
- ; TAHITI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[COPY22]](s32)
+ ; TAHITI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
+ ; TAHITI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
+ ; TAHITI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[COPY11]](s32)
; TAHITI: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
- ; TAHITI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
- ; TAHITI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; TAHITI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C2]]
- ; TAHITI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND12]], [[COPY24]](s32)
+ ; TAHITI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
+ ; TAHITI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
+ ; TAHITI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND12]], [[COPY12]](s32)
; TAHITI: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
- ; TAHITI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; TAHITI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; TAHITI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C2]]
- ; TAHITI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[AND13]], [[COPY26]](s32)
+ ; TAHITI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; TAHITI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
+ ; TAHITI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[AND13]], [[COPY13]](s32)
; TAHITI: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; TAHITI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
- ; TAHITI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; TAHITI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C2]]
- ; TAHITI: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY28]](s32)
- ; TAHITI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; TAHITI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; TAHITI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C2]]
- ; TAHITI: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[AND15]], [[COPY30]](s32)
- ; TAHITI: [[COPY32:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; TAHITI: [[COPY33:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; TAHITI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY33]], [[C2]]
- ; TAHITI: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[AND16]], [[COPY32]](s32)
- ; TAHITI: [[COPY34:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; TAHITI: [[COPY35:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; TAHITI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY35]], [[C2]]
- ; TAHITI: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[AND17]], [[COPY34]](s32)
- ; TAHITI: [[COPY36:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; TAHITI: [[COPY37:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; TAHITI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY37]], [[C2]]
- ; TAHITI: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[AND18]], [[COPY36]](s32)
- ; TAHITI: [[COPY38:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; TAHITI: [[COPY39:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; TAHITI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY39]], [[C2]]
- ; TAHITI: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[AND19]], [[COPY38]](s32)
- ; TAHITI: [[COPY40:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
- ; TAHITI: [[COPY41:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; TAHITI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY41]], [[C2]]
- ; TAHITI: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[AND20]], [[COPY40]](s32)
- ; TAHITI: [[COPY42:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; TAHITI: [[COPY43:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; TAHITI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY43]], [[C2]]
- ; TAHITI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[AND21]], [[COPY42]](s32)
- ; TAHITI: [[COPY44:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
- ; TAHITI: [[COPY45:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; TAHITI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY45]], [[C2]]
- ; TAHITI: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[AND22]], [[COPY44]](s32)
- ; TAHITI: [[COPY46:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
- ; TAHITI: [[COPY47:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; TAHITI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY47]], [[C2]]
- ; TAHITI: [[LSHR24:%[0-9]+]]:_(s32) = G_LSHR [[AND23]], [[COPY46]](s32)
- ; TAHITI: [[COPY48:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
- ; TAHITI: [[COPY49:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; TAHITI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY49]], [[C2]]
- ; TAHITI: [[LSHR25:%[0-9]+]]:_(s32) = G_LSHR [[AND24]], [[COPY48]](s32)
- ; TAHITI: [[COPY50:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
- ; TAHITI: [[COPY51:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; TAHITI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY51]], [[C2]]
- ; TAHITI: [[LSHR26:%[0-9]+]]:_(s32) = G_LSHR [[AND25]], [[COPY50]](s32)
- ; TAHITI: [[COPY52:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
- ; TAHITI: [[COPY53:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; TAHITI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY53]], [[C2]]
- ; TAHITI: [[LSHR27:%[0-9]+]]:_(s32) = G_LSHR [[AND26]], [[COPY52]](s32)
- ; TAHITI: [[COPY54:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
- ; TAHITI: [[COPY55:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; TAHITI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY55]], [[C2]]
- ; TAHITI: [[LSHR28:%[0-9]+]]:_(s32) = G_LSHR [[AND27]], [[COPY54]](s32)
- ; TAHITI: [[COPY56:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; TAHITI: [[COPY57:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; TAHITI: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY57]], [[C2]]
- ; TAHITI: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[AND28]], [[COPY56]](s32)
- ; TAHITI: [[COPY58:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
- ; TAHITI: [[COPY59:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; TAHITI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY59]], [[C2]]
- ; TAHITI: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[AND29]], [[COPY58]](s32)
+ ; TAHITI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
+ ; TAHITI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
+ ; TAHITI: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY14]](s32)
+ ; TAHITI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; TAHITI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; TAHITI: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[AND15]], [[COPY15]](s32)
+ ; TAHITI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; TAHITI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; TAHITI: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[AND16]], [[COPY16]](s32)
+ ; TAHITI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; TAHITI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; TAHITI: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[AND17]], [[COPY17]](s32)
+ ; TAHITI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; TAHITI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; TAHITI: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[AND18]], [[COPY18]](s32)
+ ; TAHITI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; TAHITI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; TAHITI: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[AND19]], [[COPY19]](s32)
+ ; TAHITI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
+ ; TAHITI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; TAHITI: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[AND20]], [[COPY20]](s32)
+ ; TAHITI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; TAHITI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; TAHITI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[AND21]], [[COPY21]](s32)
+ ; TAHITI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
+ ; TAHITI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; TAHITI: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[AND22]], [[COPY22]](s32)
+ ; TAHITI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
+ ; TAHITI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; TAHITI: [[LSHR24:%[0-9]+]]:_(s32) = G_LSHR [[AND23]], [[COPY23]](s32)
+ ; TAHITI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
+ ; TAHITI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; TAHITI: [[LSHR25:%[0-9]+]]:_(s32) = G_LSHR [[AND24]], [[COPY24]](s32)
+ ; TAHITI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
+ ; TAHITI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; TAHITI: [[LSHR26:%[0-9]+]]:_(s32) = G_LSHR [[AND25]], [[COPY25]](s32)
+ ; TAHITI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
+ ; TAHITI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; TAHITI: [[LSHR27:%[0-9]+]]:_(s32) = G_LSHR [[AND26]], [[COPY26]](s32)
+ ; TAHITI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
+ ; TAHITI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; TAHITI: [[LSHR28:%[0-9]+]]:_(s32) = G_LSHR [[AND27]], [[COPY27]](s32)
+ ; TAHITI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
+ ; TAHITI: [[AND28:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; TAHITI: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[AND28]], [[COPY28]](s32)
+ ; TAHITI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
+ ; TAHITI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; TAHITI: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[AND29]], [[COPY29]](s32)
; TAHITI: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; TAHITI: [[COPY60:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; TAHITI: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY60]], [[C1]]
- ; TAHITI: [[COPY61:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; TAHITI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY61]], [[C1]]
+ ; TAHITI: [[AND30:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C1]]
+ ; TAHITI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; TAHITI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C1]](s32)
; TAHITI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND30]], [[SHL]]
- ; TAHITI: [[COPY62:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; TAHITI: [[AND32:%[0-9]+]]:_(s32) = G_AND [[COPY62]], [[C1]]
+ ; TAHITI: [[AND32:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; TAHITI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND32]], [[C3]](s32)
; TAHITI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; TAHITI: [[COPY63:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; TAHITI: [[AND33:%[0-9]+]]:_(s32) = G_AND [[COPY63]], [[C1]]
+ ; TAHITI: [[AND33:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
; TAHITI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND33]], [[C4]](s32)
; TAHITI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; TAHITI: [[COPY64:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; TAHITI: [[AND34:%[0-9]+]]:_(s32) = G_AND [[COPY64]], [[C1]]
+ ; TAHITI: [[AND34:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
; TAHITI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND34]], [[C5]](s32)
; TAHITI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
- ; TAHITI: [[COPY65:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; TAHITI: [[AND35:%[0-9]+]]:_(s32) = G_AND [[COPY65]], [[C1]]
+ ; TAHITI: [[AND35:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
; TAHITI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND35]], [[C6]](s32)
; TAHITI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; TAHITI: [[COPY66:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; TAHITI: [[AND36:%[0-9]+]]:_(s32) = G_AND [[COPY66]], [[C1]]
+ ; TAHITI: [[AND36:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
; TAHITI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND36]], [[C7]](s32)
; TAHITI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; TAHITI: [[COPY67:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; TAHITI: [[AND37:%[0-9]+]]:_(s32) = G_AND [[COPY67]], [[C1]]
+ ; TAHITI: [[AND37:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C1]]
; TAHITI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND37]], [[C8]](s32)
; TAHITI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
- ; TAHITI: [[COPY68:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; TAHITI: [[AND38:%[0-9]+]]:_(s32) = G_AND [[COPY68]], [[C1]]
+ ; TAHITI: [[AND38:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C1]]
; TAHITI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND38]], [[C9]](s32)
; TAHITI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; TAHITI: [[COPY69:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; TAHITI: [[AND39:%[0-9]+]]:_(s32) = G_AND [[COPY69]], [[C1]]
+ ; TAHITI: [[AND39:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C1]]
; TAHITI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND39]], [[C10]](s32)
; TAHITI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; TAHITI: [[COPY70:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; TAHITI: [[AND40:%[0-9]+]]:_(s32) = G_AND [[COPY70]], [[C1]]
+ ; TAHITI: [[AND40:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C1]]
; TAHITI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND40]], [[C11]](s32)
; TAHITI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[SHL9]]
- ; TAHITI: [[COPY71:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; TAHITI: [[AND41:%[0-9]+]]:_(s32) = G_AND [[COPY71]], [[C1]]
+ ; TAHITI: [[AND41:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C1]]
; TAHITI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND41]], [[C12]](s32)
; TAHITI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; TAHITI: [[COPY72:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; TAHITI: [[AND42:%[0-9]+]]:_(s32) = G_AND [[COPY72]], [[C1]]
+ ; TAHITI: [[AND42:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C1]]
; TAHITI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND42]], [[C13]](s32)
; TAHITI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
- ; TAHITI: [[COPY73:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; TAHITI: [[AND43:%[0-9]+]]:_(s32) = G_AND [[COPY73]], [[C1]]
+ ; TAHITI: [[AND43:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C1]]
; TAHITI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND43]], [[C14]](s32)
; TAHITI: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR11]], [[SHL12]]
- ; TAHITI: [[COPY74:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; TAHITI: [[AND44:%[0-9]+]]:_(s32) = G_AND [[COPY74]], [[C1]]
+ ; TAHITI: [[AND44:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C1]]
; TAHITI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND44]], [[C15]](s32)
; TAHITI: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; TAHITI: [[COPY75:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; TAHITI: [[AND45:%[0-9]+]]:_(s32) = G_AND [[COPY75]], [[C1]]
+ ; TAHITI: [[AND45:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C1]]
; TAHITI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND45]], [[C16]](s32)
; TAHITI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
- ; TAHITI: [[COPY76:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; TAHITI: [[AND46:%[0-9]+]]:_(s32) = G_AND [[COPY76]], [[C1]]
+ ; TAHITI: [[AND46:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; TAHITI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND46]], [[C]](s32)
; TAHITI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[OR14]], [[SHL15]]
- ; TAHITI: [[COPY77:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; TAHITI: [[AND47:%[0-9]+]]:_(s32) = G_AND [[COPY77]], [[C1]]
+ ; TAHITI: [[AND47:%[0-9]+]]:_(s32) = G_AND [[LSHR16]], [[C1]]
; TAHITI: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
; TAHITI: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND47]], [[C17]](s32)
; TAHITI: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; TAHITI: [[COPY78:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; TAHITI: [[AND48:%[0-9]+]]:_(s32) = G_AND [[COPY78]], [[C1]]
+ ; TAHITI: [[AND48:%[0-9]+]]:_(s32) = G_AND [[LSHR17]], [[C1]]
; TAHITI: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 18
; TAHITI: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND48]], [[C18]](s32)
; TAHITI: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
- ; TAHITI: [[COPY79:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; TAHITI: [[AND49:%[0-9]+]]:_(s32) = G_AND [[COPY79]], [[C1]]
+ ; TAHITI: [[AND49:%[0-9]+]]:_(s32) = G_AND [[LSHR18]], [[C1]]
; TAHITI: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 19
; TAHITI: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND49]], [[C19]](s32)
; TAHITI: [[OR18:%[0-9]+]]:_(s32) = G_OR [[OR17]], [[SHL18]]
- ; TAHITI: [[COPY80:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; TAHITI: [[AND50:%[0-9]+]]:_(s32) = G_AND [[COPY80]], [[C1]]
+ ; TAHITI: [[AND50:%[0-9]+]]:_(s32) = G_AND [[LSHR19]], [[C1]]
; TAHITI: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; TAHITI: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND50]], [[C20]](s32)
; TAHITI: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
- ; TAHITI: [[COPY81:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; TAHITI: [[AND51:%[0-9]+]]:_(s32) = G_AND [[COPY81]], [[C1]]
+ ; TAHITI: [[AND51:%[0-9]+]]:_(s32) = G_AND [[LSHR20]], [[C1]]
; TAHITI: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
; TAHITI: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND51]], [[C21]](s32)
; TAHITI: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
- ; TAHITI: [[COPY82:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; TAHITI: [[AND52:%[0-9]+]]:_(s32) = G_AND [[COPY82]], [[C1]]
+ ; TAHITI: [[AND52:%[0-9]+]]:_(s32) = G_AND [[LSHR21]], [[C1]]
; TAHITI: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 22
; TAHITI: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND52]], [[C22]](s32)
; TAHITI: [[OR21:%[0-9]+]]:_(s32) = G_OR [[OR20]], [[SHL21]]
- ; TAHITI: [[COPY83:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; TAHITI: [[AND53:%[0-9]+]]:_(s32) = G_AND [[COPY83]], [[C1]]
+ ; TAHITI: [[AND53:%[0-9]+]]:_(s32) = G_AND [[LSHR22]], [[C1]]
; TAHITI: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
; TAHITI: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND53]], [[C23]](s32)
; TAHITI: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
- ; TAHITI: [[COPY84:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; TAHITI: [[AND54:%[0-9]+]]:_(s32) = G_AND [[COPY84]], [[C1]]
+ ; TAHITI: [[AND54:%[0-9]+]]:_(s32) = G_AND [[LSHR23]], [[C1]]
; TAHITI: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; TAHITI: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND54]], [[C24]](s32)
; TAHITI: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
- ; TAHITI: [[COPY85:%[0-9]+]]:_(s32) = COPY [[LSHR24]](s32)
- ; TAHITI: [[AND55:%[0-9]+]]:_(s32) = G_AND [[COPY85]], [[C1]]
+ ; TAHITI: [[AND55:%[0-9]+]]:_(s32) = G_AND [[LSHR24]], [[C1]]
; TAHITI: [[C25:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
; TAHITI: [[SHL24:%[0-9]+]]:_(s32) = G_SHL [[AND55]], [[C25]](s32)
; TAHITI: [[OR24:%[0-9]+]]:_(s32) = G_OR [[OR23]], [[SHL24]]
- ; TAHITI: [[COPY86:%[0-9]+]]:_(s32) = COPY [[LSHR25]](s32)
- ; TAHITI: [[AND56:%[0-9]+]]:_(s32) = G_AND [[COPY86]], [[C1]]
+ ; TAHITI: [[AND56:%[0-9]+]]:_(s32) = G_AND [[LSHR25]], [[C1]]
; TAHITI: [[C26:%[0-9]+]]:_(s32) = G_CONSTANT i32 26
; TAHITI: [[SHL25:%[0-9]+]]:_(s32) = G_SHL [[AND56]], [[C26]](s32)
; TAHITI: [[OR25:%[0-9]+]]:_(s32) = G_OR [[OR24]], [[SHL25]]
- ; TAHITI: [[COPY87:%[0-9]+]]:_(s32) = COPY [[LSHR26]](s32)
- ; TAHITI: [[AND57:%[0-9]+]]:_(s32) = G_AND [[COPY87]], [[C1]]
+ ; TAHITI: [[AND57:%[0-9]+]]:_(s32) = G_AND [[LSHR26]], [[C1]]
; TAHITI: [[C27:%[0-9]+]]:_(s32) = G_CONSTANT i32 27
; TAHITI: [[SHL26:%[0-9]+]]:_(s32) = G_SHL [[AND57]], [[C27]](s32)
; TAHITI: [[OR26:%[0-9]+]]:_(s32) = G_OR [[OR25]], [[SHL26]]
- ; TAHITI: [[COPY88:%[0-9]+]]:_(s32) = COPY [[LSHR27]](s32)
- ; TAHITI: [[AND58:%[0-9]+]]:_(s32) = G_AND [[COPY88]], [[C1]]
+ ; TAHITI: [[AND58:%[0-9]+]]:_(s32) = G_AND [[LSHR27]], [[C1]]
; TAHITI: [[C28:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
; TAHITI: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[AND58]], [[C28]](s32)
; TAHITI: [[OR27:%[0-9]+]]:_(s32) = G_OR [[OR26]], [[SHL27]]
- ; TAHITI: [[COPY89:%[0-9]+]]:_(s32) = COPY [[LSHR28]](s32)
- ; TAHITI: [[AND59:%[0-9]+]]:_(s32) = G_AND [[COPY89]], [[C1]]
+ ; TAHITI: [[AND59:%[0-9]+]]:_(s32) = G_AND [[LSHR28]], [[C1]]
; TAHITI: [[C29:%[0-9]+]]:_(s32) = G_CONSTANT i32 29
; TAHITI: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[AND59]], [[C29]](s32)
; TAHITI: [[OR28:%[0-9]+]]:_(s32) = G_OR [[OR27]], [[SHL28]]
- ; TAHITI: [[COPY90:%[0-9]+]]:_(s32) = COPY [[LSHR29]](s32)
- ; TAHITI: [[AND60:%[0-9]+]]:_(s32) = G_AND [[COPY90]], [[C1]]
+ ; TAHITI: [[AND60:%[0-9]+]]:_(s32) = G_AND [[LSHR29]], [[C1]]
; TAHITI: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 30
; TAHITI: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[AND60]], [[C30]](s32)
; TAHITI: [[OR29:%[0-9]+]]:_(s32) = G_OR [[OR28]], [[SHL29]]
- ; TAHITI: [[COPY91:%[0-9]+]]:_(s32) = COPY [[LSHR30]](s32)
- ; TAHITI: [[AND61:%[0-9]+]]:_(s32) = G_AND [[COPY91]], [[C1]]
+ ; TAHITI: [[AND61:%[0-9]+]]:_(s32) = G_AND [[LSHR30]], [[C1]]
; TAHITI: [[C31:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; TAHITI: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[AND61]], [[C31]](s32)
; TAHITI: [[OR30:%[0-9]+]]:_(s32) = G_OR [[OR29]], [[SHL30]]
@@ -344,8 +282,7 @@ body: |
; FIJI: [[LSHR30:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C15]](s16)
; FIJI: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; FIJI: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; FIJI: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; FIJI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C16]]
+ ; FIJI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C16]]
; FIJI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; FIJI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C16]]
; FIJI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C16]](s32)
@@ -420,8 +357,7 @@ body: |
; FIJI: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; FIJI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C30]](s32)
; FIJI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
- ; FIJI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; FIJI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C16]]
+ ; FIJI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C16]]
; FIJI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND16]], [[C]](s32)
; FIJI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[OR14]], [[SHL15]]
; FIJI: [[ANYEXT15:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR16]](s16)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
index 4ac62b2905237..1563b4fae462f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
@@ -22,8 +22,7 @@ body: |
; CHECK-LABEL: name: test_implicit_def_s7
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+ ; CHECK: $vgpr0 = COPY [[DEF]](s32)
%0:_(s7) = G_IMPLICIT_DEF
%1:_(s32) = G_ANYEXT %0
$vgpr0 = COPY %1
@@ -36,8 +35,7 @@ body: |
; CHECK-LABEL: name: test_implicit_def_s8
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+ ; CHECK: $vgpr0 = COPY [[DEF]](s32)
%0:_(s8) = G_IMPLICIT_DEF
%1:_(s32) = G_ANYEXT %0
$vgpr0 = COPY %1
@@ -75,8 +73,7 @@ body: |
; CHECK-LABEL: name: test_implicit_def_48
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY [[DEF]](s64)
- ; CHECK: $vgpr0_vgpr1 = COPY [[COPY]](s64)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[DEF]](s64)
%0:_(s48) = G_IMPLICIT_DEF
%1:_(s64) = G_ANYEXT %0
$vgpr0_vgpr1 = COPY %1
@@ -366,8 +363,7 @@ body: |
; CHECK-LABEL: name: test_implicit_def_v2s1
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
- ; CHECK: $vgpr0_vgpr1 = COPY [[COPY]](<2 x s32>)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[DEF]](<2 x s32>)
%0:_(<2 x s1>) = G_IMPLICIT_DEF
%1:_(<2 x s32>) = G_ANYEXT %0
$vgpr0_vgpr1 = COPY %1
@@ -380,8 +376,7 @@ body: |
; CHECK-LABEL: name: test_implicit_def_v3s1
; CHECK: [[DEF:%[0-9]+]]:_(<3 x s32>) = G_IMPLICIT_DEF
- ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY [[DEF]](<3 x s32>)
- ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[COPY]](<3 x s32>)
+ ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[DEF]](<3 x s32>)
%0:_(<3 x s1>) = G_IMPLICIT_DEF
%1:_(<3 x s32>) = G_ANYEXT %0
$vgpr0_vgpr1_vgpr2 = COPY %1
@@ -394,8 +389,7 @@ body: |
; CHECK-LABEL: name: test_implicit_def_v2s8
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
- ; CHECK: $vgpr0_vgpr1 = COPY [[COPY]](<2 x s32>)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[DEF]](<2 x s32>)
%0:_(<2 x s8>) = G_IMPLICIT_DEF
%1:_(<2 x s32>) = G_ANYEXT %0
$vgpr0_vgpr1 = COPY %1
@@ -411,10 +405,7 @@ body: |
; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[DEF1]](<4 x s32>)
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s8>) = G_IMPLICIT_DEF
%1:_(<3 x s32>) = G_ANYEXT %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
index 499cd2abbaf3c..3dc195b70431a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
@@ -146,11 +146,8 @@ body: |
; CHECK-LABEL: name: insert_vector_elt_0_v2i8_i32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
- ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[INSERT:%[0-9]+]]:_(<2 x s32>) = G_INSERT [[COPY1]], [[COPY2]](s32), 0
- ; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY [[INSERT]](<2 x s32>)
- ; CHECK: $vgpr0_vgpr1 = COPY [[COPY3]](<2 x s32>)
+ ; CHECK: [[INSERT:%[0-9]+]]:_(<2 x s32>) = G_INSERT [[DEF]], [[COPY]](s32), 0
+ ; CHECK: $vgpr0_vgpr1 = COPY [[INSERT]](<2 x s32>)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
%2:_(<2 x s8>) = G_IMPLICIT_DEF
@@ -803,25 +800,20 @@ body: |
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C3]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[SHL3]](s32)
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[SHL3]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
@@ -831,18 +823,14 @@ body: |
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[OR3]], [[C]](s32)
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[OR3]], [[C1]](s32)
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[OR3]], [[C2]](s32)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[OR3]], [[C3]]
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL6]]
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C1]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL7]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C2]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL8]]
; CHECK: $vgpr0 = COPY [[OR6]](s32)
@@ -880,15 +868,13 @@ body: |
; CHECK: [[LSHR4:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC2]], [[C1]](s16)
; CHECK: [[LSHR5:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC3]], [[C1]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR3]](s16)
@@ -896,14 +882,12 @@ body: |
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR4]](s16)
; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C2]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C3]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR5]](s16)
@@ -917,8 +901,7 @@ body: |
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]]
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C6]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
+ ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[SHL6]](s32)
; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[SHL6]](s32)
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
index d461c72c6e141..563344f42ab68 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
@@ -764,8 +764,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[AND]]
@@ -789,8 +788,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -131071
@@ -815,8 +813,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C]]
@@ -1297,13 +1294,12 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -65536
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[AND]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1
@@ -1321,15 +1317,14 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -131071
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1
@@ -1347,15 +1342,14 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -16776961
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY2]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %1
@@ -1373,12 +1367,11 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C1]](s32)
+ ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; CHECK: $vgpr0 = COPY [[COPY3]](s32)
%0:_(s32) = COPY $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
index 0408d219a8fde..176e9a1a2e2f1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
@@ -706,15 +706,12 @@ body: |
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; GFX6: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FPTRUNC8]](s16)
; GFX6: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C5]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C5]]
+ ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C5]]
+ ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C5]]
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX6: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX6: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
@@ -778,15 +775,12 @@ body: |
; GFX8: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[FADD5]](s16)
; GFX8: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
+ ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C5]]
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX8: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; GFX8: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX8: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX8: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C5]]
+ ; GFX8: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C5]]
+ ; GFX8: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C5]]
; GFX8: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX8: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX8: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
@@ -847,11 +841,8 @@ body: |
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD3]](s16)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX9: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[FADD5]](s16)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[COPY1]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[BITCAST2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[BITCAST3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir
index 137d2025516a2..577decf10dfc4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir
@@ -170,8 +170,7 @@ body: |
; CHECK-LABEL: name: test_inttoptr_s29_to_p3
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 536870911
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[AND]](s32)
; CHECK: S_ENDPGM 0, implicit [[INTTOPTR]](p3)
%0:_(s32) = COPY $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
index a8cbf4f3acbcc..289bdf1bcefc1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll
@@ -582,9 +582,7 @@ define amdgpu_ps float @atomic_add_2d(<8 x i32> inreg %rsrc, i32 %data, i16 %s,
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2d), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store (s32) on custom "ImageResource")
; GFX9: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
; GFX9: SI_RETURN_TO_EPILOG implicit $vgpr0
@@ -603,9 +601,7 @@ define amdgpu_ps float @atomic_add_2d(<8 x i32> inreg %rsrc, i32 %data, i16 %s,
; GFX10NSA: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10NSA: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2d), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store (s32) on custom "ImageResource")
; GFX10NSA: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
; GFX10NSA: SI_RETURN_TO_EPILOG implicit $vgpr0
@@ -632,12 +628,9 @@ define amdgpu_ps float @atomic_add_3d(<8 x i32> inreg %rsrc, i32 %data, i16 %s,
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.3d), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store (s32) on custom "ImageResource")
; GFX9: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
@@ -658,12 +651,9 @@ define amdgpu_ps float @atomic_add_3d(<8 x i32> inreg %rsrc, i32 %data, i16 %s,
; GFX10NSA: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX10NSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
- ; GFX10NSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
; GFX10NSA: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[DEF]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.3d), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store (s32) on custom "ImageResource")
; GFX10NSA: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
@@ -691,12 +681,9 @@ define amdgpu_ps float @atomic_add_cube(<8 x i32> inreg %rsrc, i32 %data, i16 %s
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.cube), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store (s32) on custom "ImageResource")
; GFX9: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
@@ -717,12 +704,9 @@ define amdgpu_ps float @atomic_add_cube(<8 x i32> inreg %rsrc, i32 %data, i16 %s
; GFX10NSA: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX10NSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
- ; GFX10NSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
; GFX10NSA: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[DEF]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.cube), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store (s32) on custom "ImageResource")
; GFX10NSA: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
@@ -749,9 +733,7 @@ define amdgpu_ps float @atomic_add_1darray(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1darray), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store (s32) on custom "ImageResource")
; GFX9: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
; GFX9: SI_RETURN_TO_EPILOG implicit $vgpr0
@@ -770,9 +752,7 @@ define amdgpu_ps float @atomic_add_1darray(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX10NSA: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10NSA: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1darray), [[COPY8]](s32), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store (s32) on custom "ImageResource")
; GFX10NSA: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
; GFX10NSA: SI_RETURN_TO_EPILOG implicit $vgpr0
@@ -799,12 +779,9 @@ define amdgpu_ps float @atomic_add_2darray(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2darray), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store (s32) on custom "ImageResource")
; GFX9: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
@@ -825,12 +802,9 @@ define amdgpu_ps float @atomic_add_2darray(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX10NSA: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX10NSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
- ; GFX10NSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
; GFX10NSA: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[DEF]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2darray), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store (s32) on custom "ImageResource")
; GFX10NSA: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
@@ -858,12 +832,9 @@ define amdgpu_ps float @atomic_add_2dmsaa(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2dmsaa), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store (s32) on custom "ImageResource")
; GFX9: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
@@ -884,12 +855,9 @@ define amdgpu_ps float @atomic_add_2dmsaa(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX10NSA: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX10NSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
- ; GFX10NSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
; GFX10NSA: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[DEF]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2dmsaa), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store (s32) on custom "ImageResource")
; GFX10NSA: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
@@ -918,12 +886,8 @@ define amdgpu_ps float @atomic_add_2darraymsaa(<8 x i32> inreg %rsrc, i32 %data,
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2darraymsaa), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store (s32) on custom "ImageResource")
; GFX9: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
@@ -945,12 +909,8 @@ define amdgpu_ps float @atomic_add_2darraymsaa(<8 x i32> inreg %rsrc, i32 %data,
; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
- ; GFX10NSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GFX10NSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
- ; GFX10NSA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
- ; GFX10NSA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2darraymsaa), [[COPY8]](s32), [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store (s32) on custom "ImageResource")
; GFX10NSA: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
@@ -1022,9 +982,7 @@ define amdgpu_ps float @atomic_cmpswap_2d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %
; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.2d), [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store (s32) on custom "ImageResource")
; GFX9: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
; GFX9: SI_RETURN_TO_EPILOG implicit $vgpr0
@@ -1045,9 +1003,7 @@ define amdgpu_ps float @atomic_cmpswap_2d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %
; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10NSA: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
- ; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX10NSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.2d), [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store (s32) on custom "ImageResource")
; GFX10NSA: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
; GFX10NSA: SI_RETURN_TO_EPILOG implicit $vgpr0
@@ -1076,12 +1032,9 @@ define amdgpu_ps float @atomic_cmpswap_3d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %
; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.3d), [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store (s32) on custom "ImageResource")
; GFX9: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
@@ -1104,12 +1057,9 @@ define amdgpu_ps float @atomic_cmpswap_3d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %
; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10NSA: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
- ; GFX10NSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX10NSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
- ; GFX10NSA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
; GFX10NSA: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.3d), [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store (s32) on custom "ImageResource")
; GFX10NSA: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
@@ -1140,12 +1090,8 @@ define amdgpu_ps float @atomic_cmpswap_2darraymsaa(<8 x i32> inreg %rsrc, i32 %c
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.2darraymsaa), [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store (s32) on custom "ImageResource")
; GFX9: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
@@ -1169,12 +1115,8 @@ define amdgpu_ps float @atomic_cmpswap_2darraymsaa(<8 x i32> inreg %rsrc, i32 %c
; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10NSA: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX10NSA: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
- ; GFX10NSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GFX10NSA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX10NSA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10NSA: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.2darraymsaa), [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (volatile dereferenceable load store (s32) on custom "ImageResource")
; GFX10NSA: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
index dd4c713726534..d4041d1686133 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
@@ -77,9 +77,7 @@ define amdgpu_ps <4 x float> @load_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX9: $vgpr0 = COPY [[UV]](s32)
@@ -106,9 +104,7 @@ define amdgpu_ps <4 x float> @load_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords)
; GFX10NSA: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
; GFX10NSA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10NSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; GFX10NSA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10NSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10NSA: $vgpr0 = COPY [[UV]](s32)
@@ -146,12 +142,9 @@ define amdgpu_ps <4 x float> @load_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_l
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -182,12 +175,9 @@ define amdgpu_ps <4 x float> @load_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_l
; GFX10NSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX10NSA: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX10NSA: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10NSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -227,12 +217,9 @@ define amdgpu_ps <4 x float> @load_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -263,12 +250,9 @@ define amdgpu_ps <4 x float> @load_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords
; GFX10NSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX10NSA: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX10NSA: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10NSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -305,9 +289,7 @@ define amdgpu_ps <4 x float> @load_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coo
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX9: $vgpr0 = COPY [[UV]](s32)
@@ -334,9 +316,7 @@ define amdgpu_ps <4 x float> @load_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coo
; GFX10NSA: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
; GFX10NSA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10NSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; GFX10NSA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10NSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10NSA: $vgpr0 = COPY [[UV]](s32)
@@ -374,12 +354,9 @@ define amdgpu_ps <4 x float> @load_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coo
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -410,12 +387,9 @@ define amdgpu_ps <4 x float> @load_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coo
; GFX10NSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX10NSA: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX10NSA: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10NSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -455,12 +429,9 @@ define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2dmsaa), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -491,12 +462,9 @@ define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX10NSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX10NSA: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX10NSA: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2dmsaa), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10NSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -538,12 +506,8 @@ define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16>
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -576,12 +540,8 @@ define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16>
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX10NSA: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX10NSA: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX10NSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10NSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -619,9 +579,7 @@ define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX9: $vgpr0 = COPY [[UV]](s32)
@@ -648,9 +606,7 @@ define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX10NSA: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
; GFX10NSA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10NSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; GFX10NSA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10NSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10NSA: $vgpr0 = COPY [[UV]](s32)
@@ -688,12 +644,9 @@ define amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -724,12 +677,9 @@ define amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX10NSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX10NSA: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX10NSA: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10NSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -771,12 +721,8 @@ define amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -809,12 +755,8 @@ define amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX10NSA: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX10NSA: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX10NSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10NSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -857,12 +799,8 @@ define amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, <2 x i16> %co
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -895,12 +833,8 @@ define amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, <2 x i16> %co
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX10NSA: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX10NSA: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX10NSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10NSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -941,12 +875,9 @@ define amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, <2 x i16>
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -977,12 +908,9 @@ define amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, <2 x i16>
; GFX10NSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX10NSA: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX10NSA: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10NSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -1024,12 +952,8 @@ define amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, <2 x i16>
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -1062,12 +986,8 @@ define amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, <2 x i16>
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX10NSA: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX10NSA: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX10NSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10NSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -1165,9 +1085,7 @@ define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
; GFX10NSA-LABEL: name: store_2d
@@ -1194,9 +1112,7 @@ define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x
; GFX10NSA: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
; GFX10NSA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10NSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; GFX10NSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX10NSA: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10NSA: S_ENDPGM 0
main_body:
@@ -1234,12 +1150,9 @@ define amdgpu_ps void @store_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.3d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
@@ -1270,12 +1183,9 @@ define amdgpu_ps void @store_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x
; GFX10NSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX10NSA: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX10NSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX10NSA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX10NSA: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.3d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10NSA: S_ENDPGM 0
@@ -1315,12 +1225,9 @@ define amdgpu_ps void @store_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.cube), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
@@ -1351,12 +1258,9 @@ define amdgpu_ps void @store_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2
; GFX10NSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX10NSA: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX10NSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX10NSA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX10NSA: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.cube), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10NSA: S_ENDPGM 0
@@ -1393,9 +1297,7 @@ define amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata,
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
; GFX10NSA-LABEL: name: store_1darray
@@ -1422,9 +1324,7 @@ define amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata,
; GFX10NSA: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
; GFX10NSA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10NSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; GFX10NSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX10NSA: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10NSA: S_ENDPGM 0
main_body:
@@ -1462,12 +1362,9 @@ define amdgpu_ps void @store_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata,
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
@@ -1498,12 +1395,9 @@ define amdgpu_ps void @store_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata,
; GFX10NSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX10NSA: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX10NSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX10NSA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX10NSA: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10NSA: S_ENDPGM 0
@@ -1543,12 +1437,9 @@ define amdgpu_ps void @store_2dmsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, <
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2dmsaa), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
@@ -1579,12 +1470,9 @@ define amdgpu_ps void @store_2dmsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, <
; GFX10NSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX10NSA: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX10NSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX10NSA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX10NSA: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2dmsaa), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10NSA: S_ENDPGM 0
@@ -1626,12 +1514,8 @@ define amdgpu_ps void @store_2darraymsaa(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2darraymsaa), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
@@ -1664,12 +1548,8 @@ define amdgpu_ps void @store_2darraymsaa(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX10NSA: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
; GFX10NSA: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; GFX10NSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX10NSA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX10NSA: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2darraymsaa), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10NSA: S_ENDPGM 0
@@ -1707,9 +1587,7 @@ define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
; GFX10NSA-LABEL: name: store_mip_1d
@@ -1736,9 +1614,7 @@ define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <
; GFX10NSA: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY12]](<2 x s16>)
; GFX10NSA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10NSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; GFX10NSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX10NSA: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10NSA: S_ENDPGM 0
main_body:
@@ -1776,12 +1652,9 @@ define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
@@ -1812,12 +1685,9 @@ define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <
; GFX10NSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX10NSA: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX10NSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX10NSA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX10NSA: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10NSA: S_ENDPGM 0
@@ -1859,12 +1729,8 @@ define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.3d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
@@ -1897,12 +1763,8 @@ define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX10NSA: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
; GFX10NSA: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; GFX10NSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX10NSA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX10NSA: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.3d), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10NSA: S_ENDPGM 0
@@ -1945,12 +1807,8 @@ define amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata,
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.cube), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
@@ -1983,12 +1841,8 @@ define amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata,
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX10NSA: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
; GFX10NSA: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; GFX10NSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX10NSA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX10NSA: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.cube), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10NSA: S_ENDPGM 0
@@ -2029,12 +1883,9 @@ define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
@@ -2065,12 +1916,9 @@ define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX10NSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX10NSA: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX10NSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX10NSA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX10NSA: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10NSA: S_ENDPGM 0
@@ -2112,12 +1960,8 @@ define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX9: S_ENDPGM 0
@@ -2150,12 +1994,8 @@ define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vda
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX10NSA: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY13]](<2 x s16>)
; GFX10NSA: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; GFX10NSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX10NSA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX10NSA: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2darray), [[BUILD_VECTOR1]](<4 x s32>), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 3 :: (dereferenceable store (<4 x s32>) into custom "ImageResource")
; GFX10NSA: S_ENDPGM 0
@@ -3262,9 +3102,7 @@ define amdgpu_ps <4 x float> @load_2d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
; GFX9: G_STORE [[UV4]](s32), [[DEF]](p1) :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
@@ -3293,9 +3131,7 @@ define amdgpu_ps <4 x float> @load_2d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX10NSA: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
; GFX10NSA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10NSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; GFX10NSA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10NSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
; GFX10NSA: G_STORE [[UV4]](s32), [[DEF]](p1) :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
@@ -3338,12 +3174,9 @@ define amdgpu_ps <4 x float> @load_3d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF1]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
@@ -3376,12 +3209,9 @@ define amdgpu_ps <4 x float> @load_3d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coor
; GFX10NSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX10NSA: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX10NSA: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF1]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[DEF1]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10NSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
@@ -3428,12 +3258,8 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> inreg %rsrc, <2 x i
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
@@ -3468,12 +3294,8 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> inreg %rsrc, <2 x i
; GFX10NSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX10NSA: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>)
; GFX10NSA: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; GFX10NSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10NSA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX10NSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX10NSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
+ ; GFX10NSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[LSHR3]](s32)
; GFX10NSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10NSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
index eca0f9756b9a1..0941ebe8c33b9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
@@ -64,10 +64,8 @@ define amdgpu_ps <2 x half> @image_load_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load (<2 x s16>) from custom "ImageResource")
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
- ; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
+ ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -123,17 +121,13 @@ define amdgpu_ps <3 x half> @image_load_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C1]]
+ ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C1]]
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; UNPACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; UNPACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C1]]
+ ; UNPACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; UNPACKED: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -169,17 +163,13 @@ define amdgpu_ps <3 x half> @image_load_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32
; PACKED: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; PACKED: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; PACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; PACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; PACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; PACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; PACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; PACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; PACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; PACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; PACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; PACKED: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; PACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; PACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; PACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; PACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; PACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; PACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; PACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; PACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; PACKED: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -209,18 +199,14 @@ define amdgpu_ps <4 x half> @image_load_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load (<4 x s16>) from custom "ImageResource")
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
- ; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
+ ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
- ; UNPACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; UNPACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C]]
+ ; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C]]
+ ; UNPACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C]]
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -271,8 +257,7 @@ define amdgpu_ps half @image_load_tfe_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t)
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (s16) from custom "ImageResource")
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
; UNPACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: $vgpr0 = COPY [[COPY10]](s32)
+ ; UNPACKED: $vgpr0 = COPY [[UV]](s32)
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
; PACKED-LABEL: name: image_load_tfe_f16
; PACKED: bb.1 (%ir-block.0):
@@ -293,8 +278,7 @@ define amdgpu_ps half @image_load_tfe_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t)
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (s16) from custom "ImageResource")
; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
; PACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
- ; PACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; PACKED: $vgpr0 = COPY [[COPY10]](s32)
+ ; PACKED: $vgpr0 = COPY [[UV]](s32)
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
%res = call { half, i32 } @llvm.amdgcn.image.load.2d.sl_f16i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
%tex = extractvalue { half, i32 } %res, 0
@@ -323,10 +307,8 @@ define amdgpu_ps <2 x half> @image_load_tfe_v2f16(<8 x i32> inreg %rsrc, i32 %s,
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (<2 x s16>) from custom "ImageResource")
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
- ; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
+ ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -392,17 +374,13 @@ define amdgpu_ps <3 x half> @image_load_tfe_v3f16(<8 x i32> inreg %rsrc, i32 %s,
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C1]]
+ ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C1]]
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; UNPACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; UNPACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C1]]
+ ; UNPACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; UNPACKED: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -442,17 +420,13 @@ define amdgpu_ps <3 x half> @image_load_tfe_v3f16(<8 x i32> inreg %rsrc, i32 %s,
; PACKED: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; PACKED: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; PACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; PACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; PACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; PACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; PACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; PACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; PACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; PACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; PACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; PACKED: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; PACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; PACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; PACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; PACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; PACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; PACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; PACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; PACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; PACKED: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -487,18 +461,14 @@ define amdgpu_ps <4 x half> @image_load_tfe_v4f16(<8 x i32> inreg %rsrc, i32 %s,
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x s32>)
; UNPACKED: G_STORE [[UV4]](s32), [[DEF]](p1) :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
- ; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
+ ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
- ; UNPACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; UNPACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C]]
+ ; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C]]
+ ; UNPACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C]]
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -591,8 +561,7 @@ define amdgpu_ps <2 x half> @image_load_v2f16_dmask_1000(<8 x i32> inreg %rsrc,
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load (s16) from custom "ImageResource")
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[AMDGPU_INTRIN_IMAGE_LOAD]], [[C]]
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
@@ -685,16 +654,13 @@ define amdgpu_ps <3 x half> @image_load_v3f16_dmask_1100(<8 x i32> inreg %rsrc,
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C1]]
+ ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C1]]
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL1]]
; UNPACKED: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -729,17 +695,13 @@ define amdgpu_ps <3 x half> @image_load_v3f16_dmask_1100(<8 x i32> inreg %rsrc,
; PACKED: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; PACKED: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; PACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; PACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; PACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; PACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; PACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; PACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; PACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; PACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; PACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; PACKED: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; PACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; PACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; PACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; PACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; PACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; PACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; PACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; PACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; PACKED: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -775,14 +737,12 @@ define amdgpu_ps <3 x half> @image_load_v3f16_dmask_1000(<8 x i32> inreg %rsrc,
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[AMDGPU_INTRIN_IMAGE_LOAD]], [[C1]]
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL1]]
; UNPACKED: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -817,17 +777,13 @@ define amdgpu_ps <3 x half> @image_load_v3f16_dmask_1000(<8 x i32> inreg %rsrc,
; PACKED: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; PACKED: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; PACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; PACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; PACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; PACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; PACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; PACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; PACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; PACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; PACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; PACKED: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; PACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; PACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; PACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; PACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; PACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; PACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; PACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; PACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; PACKED: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -865,17 +821,13 @@ define amdgpu_ps <3 x half> @image_load_v3f16_dmask_0000(<8 x i32> inreg %rsrc,
; UNPACKED: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; UNPACKED: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; UNPACKED: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; UNPACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; UNPACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; UNPACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; UNPACKED: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -908,17 +860,13 @@ define amdgpu_ps <3 x half> @image_load_v3f16_dmask_0000(<8 x i32> inreg %rsrc,
; PACKED: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; PACKED: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; PACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; PACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; PACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; PACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; PACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; PACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; PACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; PACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; PACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; PACKED: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; PACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; PACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; PACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; PACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; PACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; PACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; PACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; PACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; PACKED: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -948,16 +896,13 @@ define amdgpu_ps <4 x half> @image_load_v4f16_dmask_1110(<8 x i32> inreg %rsrc,
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load (<3 x s16>) from custom "ImageResource", align 8)
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
- ; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
+ ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
+ ; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C]]
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
@@ -1008,10 +953,8 @@ define amdgpu_ps <4 x half> @image_load_v4f16_dmask_1100(<8 x i32> inreg %rsrc,
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load (<2 x s16>) from custom "ImageResource")
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
- ; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
+ ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -1065,8 +1008,7 @@ define amdgpu_ps <4 x half> @image_load_v4f16_dmask_1000(<8 x i32> inreg %rsrc,
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable load (s16) from custom "ImageResource")
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[AMDGPU_INTRIN_IMAGE_LOAD]], [[C]]
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
@@ -1162,8 +1104,7 @@ define amdgpu_ps half @image_load_tfe_f16_dmask_0000(<8 x i32> inreg %rsrc, i32
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (s16) from custom "ImageResource")
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
; UNPACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: $vgpr0 = COPY [[COPY10]](s32)
+ ; UNPACKED: $vgpr0 = COPY [[UV]](s32)
; UNPACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
; PACKED-LABEL: name: image_load_tfe_f16_dmask_0000
; PACKED: bb.1 (%ir-block.0):
@@ -1184,8 +1125,7 @@ define amdgpu_ps half @image_load_tfe_f16_dmask_0000(<8 x i32> inreg %rsrc, i32
; PACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (s16) from custom "ImageResource")
; PACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
; PACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
- ; PACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; PACKED: $vgpr0 = COPY [[COPY10]](s32)
+ ; PACKED: $vgpr0 = COPY [[UV]](s32)
; PACKED: SI_RETURN_TO_EPILOG implicit $vgpr0
%res = call { half, i32 } @llvm.amdgcn.image.load.2d.sl_f16i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
%tex = extractvalue { half, i32 } %res, 0
@@ -1214,8 +1154,7 @@ define amdgpu_ps <2 x half> @image_load_tfe_v2f16_dmask_1000(<8 x i32> inreg %rs
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (s16) from custom "ImageResource")
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
@@ -1273,8 +1212,7 @@ define amdgpu_ps <2 x half> @image_load_tfe_v2f16_dmask_0000(<8 x i32> inreg %rs
; UNPACKED: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0, 0 :: (dereferenceable load (s16) from custom "ImageResource")
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
@@ -1340,16 +1278,13 @@ define amdgpu_ps <3 x half> @image_load_tfe_v3f16_dmask_1100(<8 x i32> inreg %rs
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C1]]
+ ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C1]]
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL1]]
; UNPACKED: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -1388,17 +1323,13 @@ define amdgpu_ps <3 x half> @image_load_tfe_v3f16_dmask_1100(<8 x i32> inreg %rs
; PACKED: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; PACKED: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; PACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; PACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; PACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; PACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; PACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; PACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; PACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; PACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; PACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; PACKED: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; PACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; PACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; PACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; PACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; PACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; PACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; PACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; PACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; PACKED: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -1440,14 +1371,12 @@ define amdgpu_ps <3 x half> @image_load_tfe_v3f16_dmask_1000(<8 x i32> inreg %rs
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C1]]
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL1]]
; UNPACKED: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -1486,17 +1415,13 @@ define amdgpu_ps <3 x half> @image_load_tfe_v3f16_dmask_1000(<8 x i32> inreg %rs
; PACKED: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; PACKED: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; PACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; PACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; PACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; PACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; PACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; PACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; PACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; PACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; PACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; PACKED: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; PACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; PACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; PACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; PACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; PACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; PACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; PACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; PACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; PACKED: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -1538,14 +1463,12 @@ define amdgpu_ps <3 x half> @image_load_tfe_v3f16_dmask_0000(<8 x i32> inreg %rs
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C1]]
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[C2]], [[SHL1]]
; UNPACKED: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -1584,17 +1507,13 @@ define amdgpu_ps <3 x half> @image_load_tfe_v3f16_dmask_0000(<8 x i32> inreg %rs
; PACKED: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; PACKED: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; PACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; PACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; PACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; PACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; PACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; PACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; PACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; PACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; PACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; PACKED: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; PACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; PACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; PACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; PACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; PACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; PACKED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; PACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; PACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; PACKED: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -1629,16 +1548,13 @@ define amdgpu_ps <4 x half> @image_load_tfe_v4f16_dmask_1110(<8 x i32> inreg %rs
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; UNPACKED: G_STORE [[UV3]](s32), [[DEF]](p1) :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
- ; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
+ ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; UNPACKED: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
+ ; UNPACKED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C]]
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; UNPACKED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
; UNPACKED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
@@ -1698,10 +1614,8 @@ define amdgpu_ps <4 x half> @image_load_tfe_v4f16_dmask_1100(<8 x i32> inreg %rs
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
; UNPACKED: G_STORE [[UV2]](s32), [[DEF]](p1) :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
- ; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
+ ; UNPACKED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; UNPACKED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -1765,8 +1679,7 @@ define amdgpu_ps <4 x half> @image_load_tfe_v4f16_dmask_1000(<8 x i32> inreg %rs
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
; UNPACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
@@ -1829,8 +1742,7 @@ define amdgpu_ps <4 x half> @image_load_tfe_v4f16_dmask_0000(<8 x i32> inreg %rs
; UNPACKED: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
; UNPACKED: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; UNPACKED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+ ; UNPACKED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
; UNPACKED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; UNPACKED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C1]], [[C2]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
index 7f25e8e2d9dbb..7bd0a53727e4f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll
@@ -80,9 +80,7 @@ define amdgpu_ps <4 x float> @sample_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX9: $vgpr0 = COPY [[UV]](s32)
@@ -109,9 +107,7 @@ define amdgpu_ps <4 x float> @sample_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX10: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -145,12 +141,9 @@ define amdgpu_ps <4 x float> @sample_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -179,12 +172,9 @@ define amdgpu_ps <4 x float> @sample_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg %
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.3d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -219,12 +209,9 @@ define amdgpu_ps <4 x float> @sample_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -253,12 +240,9 @@ define amdgpu_ps <4 x float> @sample_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cube), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -292,9 +276,7 @@ define amdgpu_ps <4 x float> @sample_1darray(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX9: $vgpr0 = COPY [[UV]](s32)
@@ -321,9 +303,7 @@ define amdgpu_ps <4 x float> @sample_1darray(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.1darray), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -357,12 +337,9 @@ define amdgpu_ps <4 x float> @sample_2darray(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -391,12 +368,9 @@ define amdgpu_ps <4 x float> @sample_2darray(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.2darray), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -431,9 +405,8 @@ define amdgpu_ps <4 x float> @sample_c_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -462,9 +435,8 @@ define amdgpu_ps <4 x float> @sample_c_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -500,9 +472,7 @@ define amdgpu_ps <4 x float> @sample_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -532,9 +502,7 @@ define amdgpu_ps <4 x float> @sample_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -568,9 +536,7 @@ define amdgpu_ps <4 x float> @sample_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cl.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX9: $vgpr0 = COPY [[UV]](s32)
@@ -597,9 +563,7 @@ define amdgpu_ps <4 x float> @sample_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cl.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -633,12 +597,9 @@ define amdgpu_ps <4 x float> @sample_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cl.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -667,12 +628,9 @@ define amdgpu_ps <4 x float> @sample_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cl.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -708,9 +666,7 @@ define amdgpu_ps <4 x float> @sample_c_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -740,9 +696,7 @@ define amdgpu_ps <4 x float> @sample_c_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -779,12 +733,9 @@ define amdgpu_ps <4 x float> @sample_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.2d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -815,12 +766,9 @@ define amdgpu_ps <4 x float> @sample_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
- ; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -854,9 +802,8 @@ define amdgpu_ps <4 x float> @sample_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -885,9 +832,8 @@ define amdgpu_ps <4 x float> @sample_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -923,9 +869,7 @@ define amdgpu_ps <4 x float> @sample_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -955,9 +899,7 @@ define amdgpu_ps <4 x float> @sample_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -994,9 +936,8 @@ define amdgpu_ps <4 x float> @sample_c_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.1d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -1027,9 +968,8 @@ define amdgpu_ps <4 x float> @sample_c_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.1d), 15, [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -1066,9 +1006,7 @@ define amdgpu_ps <4 x float> @sample_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.2d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -1100,9 +1038,7 @@ define amdgpu_ps <4 x float> @sample_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.2d), 15, [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -1137,9 +1073,7 @@ define amdgpu_ps <4 x float> @sample_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.cl.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -1169,9 +1103,7 @@ define amdgpu_ps <4 x float> @sample_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.cl.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -1208,12 +1140,9 @@ define amdgpu_ps <4 x float> @sample_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.cl.2d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -1244,12 +1173,9 @@ define amdgpu_ps <4 x float> @sample_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
- ; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.b.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -1286,9 +1212,7 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.1d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -1320,9 +1244,7 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -1360,12 +1282,9 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.2d), 15, [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -1398,12 +1317,9 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)
- ; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.b.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -1437,13 +1353,10 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.1d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -1472,13 +1385,10 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -1515,15 +1425,9 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
- ; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
- ; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.2d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -1555,15 +1459,9 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
- ; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX10: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -1603,22 +1501,13 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
- ; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[DEF]](s32)
- ; GFX9: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY24]](s32), [[COPY25]](s32)
- ; GFX9: [[COPY26:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY26]](s32), [[DEF]](s32)
- ; GFX9: [[COPY27:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
- ; GFX9: [[COPY28:%[0-9]+]]:_(s32) = COPY [[COPY19]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY27]](s32), [[COPY28]](s32)
- ; GFX9: [[COPY29:%[0-9]+]]:_(s32) = COPY [[COPY20]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY29]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>), [[BUILD_VECTOR_TRUNC4]](<2 x s16>), [[BUILD_VECTOR_TRUNC5]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.3d), 15, [[CONCAT_VECTORS]](<12 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -1653,22 +1542,13 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
- ; GFX10: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[DEF]](s32)
- ; GFX10: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY24]](s32), [[COPY25]](s32)
- ; GFX10: [[COPY26:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY26]](s32), [[DEF]](s32)
- ; GFX10: [[COPY27:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
- ; GFX10: [[COPY28:%[0-9]+]]:_(s32) = COPY [[COPY19]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY27]](s32), [[COPY28]](s32)
- ; GFX10: [[COPY29:%[0-9]+]]:_(s32) = COPY [[COPY20]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY29]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>), [[BUILD_VECTOR_TRUNC4]](<2 x s16>), [[BUILD_VECTOR_TRUNC5]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.3d), 15, [[CONCAT_VECTORS]](<12 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -1705,13 +1585,10 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.1d), 15, [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -1742,13 +1619,10 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
- ; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -1787,15 +1661,9 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
- ; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
- ; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX9: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.2d), 15, [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -1829,15 +1697,9 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
- ; GFX10: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX10: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -1872,14 +1734,10 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.1d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -1909,14 +1767,10 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
- ; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -1954,18 +1808,11 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
- ; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
- ; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX9: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
- ; GFX9: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY25]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.2d), 15, [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -1998,18 +1845,11 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
- ; GFX10: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX10: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
- ; GFX10: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY25]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -2046,14 +1886,10 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.1d), 15, [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -2085,14 +1921,10 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
- ; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
- ; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -2132,18 +1964,11 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
- ; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
- ; GFX9: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX9: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY24]](s32), [[COPY25]](s32)
- ; GFX9: [[COPY26:%[0-9]+]]:_(s32) = COPY [[COPY19]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY26]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<10 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.2d), 15, [[CONCAT_VECTORS]](<10 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -2178,18 +2003,11 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
- ; GFX10: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX10: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY24]](s32), [[COPY25]](s32)
- ; GFX10: [[COPY26:%[0-9]+]]:_(s32) = COPY [[COPY19]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY26]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[DEF]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -2223,13 +2041,10 @@ define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.1d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -2258,13 +2073,10 @@ define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -2301,15 +2113,9 @@ define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
- ; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
- ; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.2d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -2341,15 +2147,9 @@ define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
- ; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX10: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -2385,13 +2185,10 @@ define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.1d), 15, [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -2422,13 +2219,10 @@ define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
- ; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -2467,15 +2261,9 @@ define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
- ; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
- ; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX9: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.2d), 15, [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -2509,15 +2297,9 @@ define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
- ; GFX10: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX10: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -2552,14 +2334,10 @@ define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.1d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -2589,14 +2367,10 @@ define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
- ; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -2634,18 +2408,11 @@ define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
- ; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
- ; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX9: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
- ; GFX9: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY25]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.2d), 15, [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -2678,18 +2445,11 @@ define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
- ; GFX10: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX10: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
- ; GFX10: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY25]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -2726,14 +2486,10 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.1d), 15, [[CONCAT_VECTORS]](<8 x s16>), $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -2765,14 +2521,10 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
- ; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
- ; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -2812,18 +2564,11 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
- ; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
- ; GFX9: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX9: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY24]](s32), [[COPY25]](s32)
- ; GFX9: [[COPY26:%[0-9]+]]:_(s32) = COPY [[COPY19]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY26]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<10 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.2d), 15, [[CONCAT_VECTORS]](<10 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -2858,18 +2603,11 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
- ; GFX10: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX10: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY24]](s32), [[COPY25]](s32)
- ; GFX10: [[COPY26:%[0-9]+]]:_(s32) = COPY [[COPY19]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY26]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[DEF]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -2902,9 +2640,7 @@ define amdgpu_ps <4 x float> @sample_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.l.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX9: $vgpr0 = COPY [[UV]](s32)
@@ -2931,9 +2667,7 @@ define amdgpu_ps <4 x float> @sample_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.l.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -2967,12 +2701,9 @@ define amdgpu_ps <4 x float> @sample_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.l.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -3001,12 +2732,9 @@ define amdgpu_ps <4 x float> @sample_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.l.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -3042,9 +2770,7 @@ define amdgpu_ps <4 x float> @sample_c_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -3074,9 +2800,7 @@ define amdgpu_ps <4 x float> @sample_c_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -3113,12 +2837,9 @@ define amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.2d), 15, [[CONCAT_VECTORS]](<6 x s16>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -3149,12 +2870,9 @@ define amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
- ; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.l.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -3245,9 +2963,7 @@ define amdgpu_ps <4 x float> @sample_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX9: $vgpr0 = COPY [[UV]](s32)
@@ -3274,9 +2990,7 @@ define amdgpu_ps <4 x float> @sample_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GFX10: $vgpr0 = COPY [[UV]](s32)
@@ -3310,9 +3024,8 @@ define amdgpu_ps <4 x float> @sample_c_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -3341,9 +3054,8 @@ define amdgpu_ps <4 x float> @sample_c_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.1d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -3379,9 +3091,7 @@ define amdgpu_ps <4 x float> @sample_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -3411,9 +3121,7 @@ define amdgpu_ps <4 x float> @sample_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.2d), 15, [[CONCAT_VECTORS]](<4 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -3456,18 +3164,11 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32>
; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
- ; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
- ; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX9: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
- ; GFX9: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
- ; GFX9: [[COPY26:%[0-9]+]]:_(s32) = COPY [[COPY19]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY25]](s32), [[COPY26]](s32)
- ; GFX9: [[COPY27:%[0-9]+]]:_(s32) = COPY [[COPY20]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY27]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 4, [[CONCAT_VECTORS]](<12 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (s32) from custom "ImageResource")
; GFX9: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
@@ -3500,18 +3201,11 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
- ; GFX10: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX10: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
- ; GFX10: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
- ; GFX10: [[COPY26:%[0-9]+]]:_(s32) = COPY [[COPY19]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY25]](s32), [[COPY26]](s32)
- ; GFX10: [[COPY27:%[0-9]+]]:_(s32) = COPY [[COPY20]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY27]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 4, [[CONCAT_VECTORS]](<12 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (s32) from custom "ImageResource")
; GFX10: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
@@ -3550,18 +3244,11 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4
; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
; GFX9: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
- ; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
- ; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX9: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
- ; GFX9: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
- ; GFX9: [[COPY26:%[0-9]+]]:_(s32) = COPY [[COPY19]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY25]](s32), [[COPY26]](s32)
- ; GFX9: [[COPY27:%[0-9]+]]:_(s32) = COPY [[COPY20]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY27]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[DEF]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>)
; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 6, [[CONCAT_VECTORS]](<12 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<2 x s32>) from custom "ImageResource")
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
@@ -3596,18 +3283,11 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4
; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
- ; GFX10: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX10: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
- ; GFX10: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY18]](s32)
- ; GFX10: [[COPY26:%[0-9]+]]:_(s32) = COPY [[COPY19]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY25]](s32), [[COPY26]](s32)
- ; GFX10: [[COPY27:%[0-9]+]]:_(s32) = COPY [[COPY20]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY27]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[DEF]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.o.2darray), 6, [[CONCAT_VECTORS]](<12 x s16>), $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 3 :: (dereferenceable load (<2 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
index f74d1d4686a3d..30052d6ceb389 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll
@@ -22,11 +22,9 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -64,12 +62,8 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
- ; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
@@ -111,17 +105,11 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
- ; GFX10: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[DEF]](s32)
- ; GFX10: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[COPY25:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY24]](s32), [[COPY25]](s32)
- ; GFX10: [[COPY26:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY26]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](s32)
; GFX10: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](s32)
@@ -161,11 +149,9 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -205,12 +191,8 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](s32)
; GFX10: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
@@ -247,11 +229,9 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.d.cl.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
@@ -291,12 +271,8 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](s32)
; GFX10: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](s32)
@@ -336,11 +312,9 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
- ; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](s32)
; GFX10: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.d.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
@@ -382,12 +356,8 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](s32)
; GFX10: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](s32)
; GFX10: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](s32)
@@ -425,11 +395,9 @@ define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[DEF]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -467,12 +435,8 @@ define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
- ; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.2d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
@@ -510,11 +474,9 @@ define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
; GFX10: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
@@ -554,12 +516,8 @@ define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](s32)
; GFX10: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.2d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
@@ -596,11 +554,9 @@ define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[DEF]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY14]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.cd.cl.1d), 15, [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
@@ -640,12 +596,8 @@ define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY $vgpr5
; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
- ; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](s32)
; GFX10: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](s32)
@@ -685,11 +637,9 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
; GFX10: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[DEF]](s32)
- ; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[DEF]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY15]](s32)
; GFX10: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY16]](s32)
; GFX10: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.cd.cl.1d), 15, [[BITCAST]](<2 x s16>), [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BITCAST1]](<2 x s16>), [[BITCAST2]](<2 x s16>), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0, 2 :: (dereferenceable load (<4 x s32>) from custom "ImageResource")
@@ -731,12 +681,8 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY $vgpr6
; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY $vgpr7
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
- ; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY13]](s32)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY17]](s32)
; GFX10: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](s32)
; GFX10: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](s32)
@@ -782,12 +728,8 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
- ; GFX10: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX10: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
; GFX10: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](s32)
; GFX10: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](s32)
; GFX10: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](s32)
@@ -829,12 +771,8 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4
; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY $vgpr8
; GFX10: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY12]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY13]](s32)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY14]](s32)
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY15]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
- ; GFX10: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY16]](s32)
- ; GFX10: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY17]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY16]](s32), [[COPY17]](s32)
; GFX10: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY18]](s32)
; GFX10: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY19]](s32)
; GFX10: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY20]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
index 7777e4a3ab2d2..201c5b72255ea 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
@@ -105,9 +105,7 @@ define amdgpu_ps void @image_store_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
; UNPACKED: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY10]](<2 x s16>)
; UNPACKED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; UNPACKED: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; UNPACKED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; UNPACKED: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY11]](s32), [[COPY12]](s32)
+ ; UNPACKED: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[LSHR]](s32)
; UNPACKED: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR2]](<2 x s32>), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store (<2 x s16>) into custom "ImageResource")
; UNPACKED: S_ENDPGM 0
; GFX81-LABEL: name: image_store_v2f16
@@ -196,10 +194,7 @@ define amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
; UNPACKED: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; UNPACKED: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; UNPACKED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
- ; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; UNPACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; UNPACKED: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; UNPACKED: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32)
+ ; UNPACKED: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[LSHR]](s32), [[UV1]](s32)
; UNPACKED: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR2]](<3 x s32>), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store (<3 x s16>) into custom "ImageResource", align 8)
; UNPACKED: S_ENDPGM 0
; GFX81-LABEL: name: image_store_v3f16
@@ -227,15 +222,12 @@ define amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
; GFX81: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; GFX81: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
; GFX81: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX81: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX81: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; GFX81: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX81: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; GFX81: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C1]]
+ ; GFX81: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; GFX81: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX81: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX81: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX81: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX81: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C1]]
+ ; GFX81: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C1]]
; GFX81: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX81: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; GFX81: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
@@ -269,12 +261,9 @@ define amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[UV]](s32), [[LSHR]](s32)
; GFX9: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[UV1]](s32), [[DEF1]](s32)
; GFX9: [[CONCAT_VECTORS1:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[DEF]](<2 x s16>)
; GFX9: [[UV3:%[0-9]+]]:_(<3 x s16>), [[UV4:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS1]](<6 x s16>)
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
@@ -303,12 +292,9 @@ define amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
; GFX10: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; GFX10: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
- ; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
- ; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[UV]](s32), [[LSHR]](s32)
; GFX10: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF1]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[UV1]](s32), [[DEF1]](s32)
; GFX10: [[CONCAT_VECTORS1:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[DEF]](<2 x s16>)
; GFX10: [[UV3:%[0-9]+]]:_(<3 x s16>), [[UV4:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS1]](<6 x s16>)
; GFX10: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
@@ -341,11 +327,7 @@ define amdgpu_ps void @image_store_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
; UNPACKED: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; UNPACKED: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY11]](<2 x s16>)
; UNPACKED: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; UNPACKED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; UNPACKED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; UNPACKED: [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; UNPACKED: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; UNPACKED: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
+ ; UNPACKED: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[LSHR]](s32), [[BITCAST1]](s32), [[LSHR1]](s32)
; UNPACKED: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR2]](<4 x s32>), 15, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0, 0 :: (dereferenceable store (<4 x s16>) into custom "ImageResource")
; UNPACKED: S_ENDPGM 0
; GFX81-LABEL: name: image_store_v4f16
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
index c9cc4c317efa8..307199ba0616a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
@@ -147,64 +147,40 @@ body: |
; GCN: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C2]](s32)
; GCN: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GCN: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C3]](s32)
- ; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GCN: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C1]](s32)
; GCN: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C2]](s32)
; GCN: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C3]](s32)
- ; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
; GCN: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C1]](s32)
; GCN: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C2]](s32)
; GCN: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C3]](s32)
- ; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; GCN: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GCN: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GCN: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
; GCN: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GCN: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C4]]
- ; GCN: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C4]]
+ ; GCN: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[C4]]
+ ; GCN: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; GCN: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GCN: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GCN: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GCN: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GCN: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C4]]
- ; GCN: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; GCN: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C4]]
+ ; GCN: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
+ ; GCN: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C4]]
; GCN: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GCN: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GCN: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GCN: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; GCN: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C4]]
- ; GCN: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
- ; GCN: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C4]]
+ ; GCN: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C4]]
+ ; GCN: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
; GCN: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GCN: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GCN: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; GCN: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
- ; GCN: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C4]]
- ; GCN: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
- ; GCN: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C4]]
+ ; GCN: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C4]]
+ ; GCN: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C4]]
; GCN: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GCN: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GCN: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
- ; GCN: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; GCN: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C4]]
- ; GCN: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; GCN: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C4]]
+ ; GCN: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV6]], [[C4]]
+ ; GCN: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C4]]
; GCN: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
; GCN: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; GCN: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; GCN: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
- ; GCN: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C4]]
- ; GCN: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; GCN: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C4]]
+ ; GCN: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C4]]
+ ; GCN: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C4]]
; GCN: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; GCN: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; GCN: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
index d900da6240e11..248b5b9e2d813 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
@@ -22,20 +22,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[MV]], [[C3]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 6)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C5]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C4]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C6]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C4]]
; CI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C7]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
index 0a404dc571bc7..eb5f4cdcd6c57 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
@@ -14,22 +14,19 @@ body: |
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 4)
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI: $vgpr0 = COPY [[AND]](s32)
; VI-LABEL: name: test_load_constant_s1_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 4)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; VI: $vgpr0 = COPY [[AND]](s32)
; GFX9-LABEL: name: test_load_constant_s1_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 4)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9: $vgpr0 = COPY [[AND]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s1) = G_LOAD %0 :: (load (s1), align 1, addrspace 4)
@@ -47,22 +44,19 @@ body: |
; CI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4)
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI: $vgpr0 = COPY [[AND]](s32)
; VI-LABEL: name: test_load_constant_s2_align1
; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; VI: $vgpr0 = COPY [[AND]](s32)
; GFX9-LABEL: name: test_load_constant_s2_align1
; GFX9: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9: $vgpr0 = COPY [[AND]](s32)
%0:_(p4) = COPY $vgpr0_vgpr1
%1:_(s2) = G_LOAD %0 :: (load (s2), align 1, addrspace 4)
@@ -79,18 +73,15 @@ body: |
; CI-LABEL: name: test_load_constant_s8_align4
; CI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), align 4, addrspace 4)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_constant_s8_align4
; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), align 4, addrspace 4)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_constant_s8_align4
; GFX9: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), align 4, addrspace 4)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p4) = COPY $vgpr0_vgpr1
%1:_(s8) = G_LOAD %0 :: (load (s8), align 4, addrspace 4)
%2:_(s32) = G_ANYEXT %1
@@ -106,18 +97,15 @@ body: |
; CI-LABEL: name: test_load_constant_s8_align1
; CI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_constant_s8_align1
; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_constant_s8_align1
; GFX9: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p4) = COPY $vgpr0_vgpr1
%1:_(s8) = G_LOAD %0 :: (load (s8), align 1, addrspace 4)
%2:_(s32) = G_ANYEXT %1
@@ -133,18 +121,15 @@ body: |
; CI-LABEL: name: test_load_constant_s16_align4
; CI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_constant_s16_align4
; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_constant_s16_align4
; GFX9: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), align 4, addrspace 4)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p4) = COPY $vgpr0_vgpr1
%1:_(s16) = G_LOAD %0 :: (load (s16), align 4, addrspace 4)
%2:_(s32) = G_ANYEXT %1
@@ -160,18 +145,15 @@ body: |
; CI-LABEL: name: test_load_constant_s16_align2
; CI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), addrspace 4)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_constant_s16_align2
; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), addrspace 4)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_constant_s16_align2
; GFX9: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), addrspace 4)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p4) = COPY $vgpr0_vgpr1
%1:_(s16) = G_LOAD %0 :: (load (s16), align 2, addrspace 4)
%2:_(s32) = G_ANYEXT %1
@@ -195,8 +177,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -276,10 +257,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 4)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -291,10 +270,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 4)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -306,10 +283,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 4)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -338,20 +313,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -369,20 +340,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -400,20 +367,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -432,18 +395,15 @@ body: |
; CI-LABEL: name: test_load_constant_s24_align8
; CI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s32), align 8, addrspace 4)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_constant_s24_align8
; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s32), align 8, addrspace 4)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_constant_s24_align8
; GFX9: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s32), align 8, addrspace 4)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p4) = COPY $vgpr0_vgpr1
%1:_(s24) = G_LOAD %0 :: (load (s24), align 8, addrspace 4)
%2:_(s32) = G_ANYEXT %1
@@ -459,18 +419,15 @@ body: |
; CI-LABEL: name: test_load_constant_s24_align4
; CI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s32), addrspace 4)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_constant_s24_align4
; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s32), addrspace 4)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_constant_s24_align4
; GFX9: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s32), addrspace 4)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p4) = COPY $vgpr0_vgpr1
%1:_(s24) = G_LOAD %0 :: (load (s24), align 4, addrspace 4)
%2:_(s32) = G_ANYEXT %1
@@ -501,25 +458,22 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD1]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C5]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI: $vgpr0 = COPY [[COPY5]](s32)
+ ; CI: $vgpr0 = COPY [[OR2]](s32)
; VI-LABEL: name: test_load_constant_s24_align2
; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), addrspace 4)
@@ -551,8 +505,7 @@ body: |
; VI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[OR2]](s32)
; GFX9-LABEL: name: test_load_constant_s24_align2
; GFX9: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), addrspace 4)
@@ -584,8 +537,7 @@ body: |
; GFX9: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[OR2]](s32)
%0:_(p4) = COPY $vgpr0_vgpr1
%1:_(s24) = G_LOAD %0 :: (load (s24), align 2, addrspace 4)
%2:_(s32) = G_ANYEXT %1
@@ -614,15 +566,13 @@ body: |
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -631,8 +581,7 @@ body: |
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI: $vgpr0 = COPY [[COPY4]](s32)
+ ; CI: $vgpr0 = COPY [[OR2]](s32)
; VI-LABEL: name: test_load_constant_s24_align1
; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4)
@@ -662,8 +611,7 @@ body: |
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[OR2]](s32)
; GFX9-LABEL: name: test_load_constant_s24_align1
; GFX9: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4)
@@ -693,8 +641,7 @@ body: |
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[OR2]](s32)
%0:_(p4) = COPY $vgpr0_vgpr1
%1:_(s24) = G_LOAD %0 :: (load (s24), align 1, addrspace 4)
%2:_(s32) = G_ANYEXT %1
@@ -711,22 +658,19 @@ body: |
; CI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; CI: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p4) :: (load (s64), addrspace 4)
; CI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
- ; CI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; CI: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
+ ; CI: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
; CI: $vgpr0_vgpr1 = COPY [[AND]](s64)
; VI-LABEL: name: test_load_constant_s48_align8
; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p4) :: (load (s64), addrspace 4)
; VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
- ; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; VI: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
; VI: $vgpr0_vgpr1 = COPY [[AND]](s64)
; GFX9-LABEL: name: test_load_constant_s48_align8
; GFX9: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p4) :: (load (s64), addrspace 4)
; GFX9: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
- ; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; GFX9: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
; GFX9: $vgpr0_vgpr1 = COPY [[AND]](s64)
%0:_(p4) = COPY $vgpr0_vgpr1
%1:_(s48) = G_LOAD %0 :: (load (s48), align 8, addrspace 4)
@@ -799,17 +743,13 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -827,17 +767,13 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -855,17 +791,13 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -911,31 +843,27 @@ body: |
; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -1168,10 +1096,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 4)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -1180,10 +1106,8 @@ body: |
; CI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (load (s16) from unknown-address + 4, addrspace 4)
; CI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -1191,10 +1115,8 @@ body: |
; CI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p4) :: (load (s16) from unknown-address + 8, addrspace 4)
; CI: [[PTR_ADD4:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; CI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p4) :: (load (s16) from unknown-address + 10, addrspace 4)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -1207,10 +1129,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 4)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -1219,10 +1139,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (load (s16) from unknown-address + 4, addrspace 4)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -1230,10 +1148,8 @@ body: |
; VI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p4) :: (load (s16) from unknown-address + 8, addrspace 4)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; VI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p4) :: (load (s16) from unknown-address + 10, addrspace 4)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -1246,10 +1162,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 4)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -1258,10 +1172,8 @@ body: |
; GFX9: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (load (s16) from unknown-address + 4, addrspace 4)
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -1269,10 +1181,8 @@ body: |
; GFX9: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p4) :: (load (s16) from unknown-address + 8, addrspace 4)
; GFX9: [[PTR_ADD4:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; GFX9: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p4) :: (load (s16) from unknown-address + 10, addrspace 4)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -1302,20 +1212,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1328,18 +1234,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 4)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 4)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -1351,18 +1253,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p4) :: (load (s8) from unknown-address + 10, addrspace 4)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p4) :: (load (s8) from unknown-address + 11, addrspace 4)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -1381,20 +1279,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1407,18 +1301,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 4)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 4)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -1430,18 +1320,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p4) :: (load (s8) from unknown-address + 10, addrspace 4)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p4) :: (load (s8) from unknown-address + 11, addrspace 4)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -1460,20 +1346,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1486,18 +1368,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 4)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 4)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -1509,18 +1387,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p4) :: (load (s8) from unknown-address + 10, addrspace 4)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p4) :: (load (s8) from unknown-address + 11, addrspace 4)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -1714,20 +1588,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1740,18 +1610,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 4)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 4)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -1763,18 +1629,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p4) :: (load (s8) from unknown-address + 10, addrspace 4)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p4) :: (load (s8) from unknown-address + 11, addrspace 4)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
@@ -1786,18 +1648,14 @@ body: |
; CI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p4) :: (load (s8) from unknown-address + 14, addrspace 4)
; CI: [[PTR_ADD14:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p4) :: (load (s8) from unknown-address + 15, addrspace 4)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -1816,20 +1674,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1842,18 +1696,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 4)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 4)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -1865,18 +1715,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p4) :: (load (s8) from unknown-address + 10, addrspace 4)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p4) :: (load (s8) from unknown-address + 11, addrspace 4)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
@@ -1888,18 +1734,14 @@ body: |
; VI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p4) :: (load (s8) from unknown-address + 14, addrspace 4)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; VI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p4) :: (load (s8) from unknown-address + 15, addrspace 4)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -1918,20 +1760,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1944,18 +1782,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 4)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 4)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -1967,18 +1801,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p4) :: (load (s8) from unknown-address + 10, addrspace 4)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p4) :: (load (s8) from unknown-address + 11, addrspace 4)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
@@ -1990,18 +1820,14 @@ body: |
; GFX9: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p4) :: (load (s8) from unknown-address + 14, addrspace 4)
; GFX9: [[PTR_ADD14:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; GFX9: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p4) :: (load (s8) from unknown-address + 15, addrspace 4)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX9: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX9: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX9: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX9: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX9: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX9: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -2120,31 +1946,27 @@ body: |
; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -2374,17 +2196,13 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -2402,17 +2220,13 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -2430,17 +2244,13 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -2486,31 +2296,27 @@ body: |
; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -2688,10 +2494,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 4)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -2704,10 +2508,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 4)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -2720,10 +2522,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 4)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -2753,20 +2553,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2785,20 +2581,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2817,20 +2609,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2861,8 +2649,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -2933,8 +2720,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -3002,8 +2788,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -3069,25 +2854,22 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI: $vgpr0 = COPY [[COPY5]](s32)
+ ; CI: $vgpr0 = COPY [[OR2]](s32)
; VI-LABEL: name: test_load_constant_v3s8_align4
; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s32), addrspace 4)
@@ -3116,8 +2898,7 @@ body: |
; VI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[OR2]](s32)
; GFX9-LABEL: name: test_load_constant_v3s8_align4
; GFX9: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s32), addrspace 4)
@@ -3146,8 +2927,7 @@ body: |
; GFX9: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[OR2]](s32)
%0:_(p4) = COPY $vgpr0_vgpr1
%1:_(<3 x s8>) = G_LOAD %0 :: (load (<3 x s8>), align 4, addrspace 4)
%2:_(s24) = G_BITCAST %1
@@ -3177,15 +2957,13 @@ body: |
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -3194,8 +2972,7 @@ body: |
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI: $vgpr0 = COPY [[COPY4]](s32)
+ ; CI: $vgpr0 = COPY [[OR2]](s32)
; VI-LABEL: name: test_load_constant_v3s8_align1
; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4)
@@ -3225,8 +3002,7 @@ body: |
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[OR2]](s32)
; GFX9-LABEL: name: test_load_constant_v3s8_align1
; GFX9: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 4)
@@ -3256,8 +3032,7 @@ body: |
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[OR2]](s32)
%0:_(p4) = COPY $vgpr0_vgpr1
%1:_(<3 x s8>) = G_LOAD %0 :: (load (<3 x s8>), align 1, addrspace 4)
%2:_(s24) = G_BITCAST %1
@@ -3281,18 +3056,14 @@ body: |
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CI: $vgpr0 = COPY [[OR2]](s32)
@@ -3306,18 +3077,14 @@ body: |
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; VI: $vgpr0 = COPY [[OR2]](s32)
@@ -3331,18 +3098,14 @@ body: |
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; GFX9: $vgpr0 = COPY [[OR2]](s32)
@@ -3374,18 +3137,14 @@ body: |
; CI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C2]](s32)
; CI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C3]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CI: $vgpr0 = COPY [[OR2]](s32)
@@ -3405,18 +3164,14 @@ body: |
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C2]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C3]](s32)
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C4]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; VI: $vgpr0 = COPY [[OR2]](s32)
@@ -3436,18 +3191,14 @@ body: |
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C2]](s32)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C3]](s32)
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C4]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; GFX9: $vgpr0 = COPY [[OR2]](s32)
@@ -3476,20 +3227,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3507,20 +3254,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3538,20 +3281,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3582,32 +3321,24 @@ body: |
; CI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; CI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -3626,32 +3357,24 @@ body: |
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -3670,32 +3393,24 @@ body: |
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -3722,38 +3437,22 @@ body: |
; CI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; CI: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; CI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; CI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; CI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CI: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32)
+ ; CI: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV1]](s32), [[LSHR3]](s32), [[LSHR4]](s32), [[LSHR5]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR1]](<4 x s32>)
; CI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; CI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; CI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; CI: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32)
+ ; CI: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV2]](s32), [[LSHR6]](s32), [[LSHR7]](s32), [[LSHR8]](s32)
; CI: [[TRUNC2:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR2]](<4 x s32>)
; CI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; CI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; CI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; CI: [[BUILD_VECTOR3:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32)
+ ; CI: [[BUILD_VECTOR3:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV3]](s32), [[LSHR9]](s32), [[LSHR10]](s32), [[LSHR11]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR3]](<4 x s32>)
; CI: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s8>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s8>), [[TRUNC1]](<4 x s8>), [[TRUNC2]](<4 x s8>), [[TRUNC3]](<4 x s8>)
; CI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<16 x s8>)
@@ -3767,38 +3466,22 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; VI: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32)
+ ; VI: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV1]](s32), [[LSHR3]](s32), [[LSHR4]](s32), [[LSHR5]](s32)
; VI: [[TRUNC1:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR1]](<4 x s32>)
; VI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; VI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; VI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; VI: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32)
+ ; VI: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV2]](s32), [[LSHR6]](s32), [[LSHR7]](s32), [[LSHR8]](s32)
; VI: [[TRUNC2:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR2]](<4 x s32>)
; VI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; VI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; VI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; VI: [[BUILD_VECTOR3:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32)
+ ; VI: [[BUILD_VECTOR3:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV3]](s32), [[LSHR9]](s32), [[LSHR10]](s32), [[LSHR11]](s32)
; VI: [[TRUNC3:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR3]](<4 x s32>)
; VI: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s8>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s8>), [[TRUNC1]](<4 x s8>), [[TRUNC2]](<4 x s8>), [[TRUNC3]](<4 x s8>)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[CONCAT_VECTORS]](<16 x s8>)
@@ -3812,45 +3495,29 @@ body: |
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[UV]](s32), [[LSHR]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR1]](s32), [[LSHR2]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<4 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[UV1]](s32), [[LSHR3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR4]](s32), [[LSHR5]](s32)
; GFX9: [[CONCAT_VECTORS1:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>)
; GFX9: [[TRUNC1:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS1]](<4 x s16>)
; GFX9: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; GFX9: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; GFX9: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[UV2]](s32), [[LSHR6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR7]](s32), [[LSHR8]](s32)
; GFX9: [[CONCAT_VECTORS2:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC4]](<2 x s16>), [[BUILD_VECTOR_TRUNC5]](<2 x s16>)
; GFX9: [[TRUNC2:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS2]](<4 x s16>)
; GFX9: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; GFX9: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; GFX9: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[UV3]](s32), [[LSHR9]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR10]](s32), [[LSHR11]](s32)
; GFX9: [[CONCAT_VECTORS3:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC6]](<2 x s16>), [[BUILD_VECTOR_TRUNC7]](<2 x s16>)
; GFX9: [[TRUNC3:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS3]](<4 x s16>)
; GFX9: [[CONCAT_VECTORS4:%[0-9]+]]:_(<16 x s8>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s8>), [[TRUNC1]](<4 x s8>), [[TRUNC2]](<4 x s8>), [[TRUNC3]](<4 x s8>)
@@ -3876,74 +3543,42 @@ body: |
; CI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; CI: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; CI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; CI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; CI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CI: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32)
+ ; CI: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV1]](s32), [[LSHR3]](s32), [[LSHR4]](s32), [[LSHR5]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR1]](<4 x s32>)
; CI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; CI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; CI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; CI: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32)
+ ; CI: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV2]](s32), [[LSHR6]](s32), [[LSHR7]](s32), [[LSHR8]](s32)
; CI: [[TRUNC2:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR2]](<4 x s32>)
; CI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; CI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; CI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; CI: [[BUILD_VECTOR3:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32)
+ ; CI: [[BUILD_VECTOR3:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV3]](s32), [[LSHR9]](s32), [[LSHR10]](s32), [[LSHR11]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR3]](<4 x s32>)
; CI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
; CI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C1]](s32)
; CI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C2]](s32)
- ; CI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; CI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; CI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; CI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; CI: [[BUILD_VECTOR4:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32)
+ ; CI: [[BUILD_VECTOR4:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV4]](s32), [[LSHR12]](s32), [[LSHR13]](s32), [[LSHR14]](s32)
; CI: [[TRUNC4:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR4]](<4 x s32>)
; CI: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
; CI: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C1]](s32)
; CI: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C2]](s32)
- ; CI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; CI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; CI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; CI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; CI: [[BUILD_VECTOR5:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32)
+ ; CI: [[BUILD_VECTOR5:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV5]](s32), [[LSHR15]](s32), [[LSHR16]](s32), [[LSHR17]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR5]](<4 x s32>)
; CI: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C]](s32)
; CI: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C1]](s32)
; CI: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C2]](s32)
- ; CI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; CI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; CI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; CI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; CI: [[BUILD_VECTOR6:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32)
+ ; CI: [[BUILD_VECTOR6:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV6]](s32), [[LSHR18]](s32), [[LSHR19]](s32), [[LSHR20]](s32)
; CI: [[TRUNC6:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR6]](<4 x s32>)
; CI: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C]](s32)
; CI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C1]](s32)
; CI: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C2]](s32)
- ; CI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; CI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; CI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; CI: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; CI: [[BUILD_VECTOR7:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32), [[COPY32]](s32)
+ ; CI: [[BUILD_VECTOR7:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV7]](s32), [[LSHR21]](s32), [[LSHR22]](s32), [[LSHR23]](s32)
; CI: [[TRUNC7:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR7]](<4 x s32>)
; CI: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s8>), [[TRUNC1]](<4 x s8>), [[TRUNC2]](<4 x s8>), [[TRUNC3]](<4 x s8>), [[TRUNC4]](<4 x s8>), [[TRUNC5]](<4 x s8>), [[TRUNC6]](<4 x s8>), [[TRUNC7]](<4 x s8>)
; CI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[CONCAT_VECTORS]](<32 x s8>)
@@ -3957,74 +3592,42 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; VI: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32)
+ ; VI: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV1]](s32), [[LSHR3]](s32), [[LSHR4]](s32), [[LSHR5]](s32)
; VI: [[TRUNC1:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR1]](<4 x s32>)
; VI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; VI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; VI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; VI: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32)
+ ; VI: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV2]](s32), [[LSHR6]](s32), [[LSHR7]](s32), [[LSHR8]](s32)
; VI: [[TRUNC2:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR2]](<4 x s32>)
; VI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; VI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; VI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; VI: [[BUILD_VECTOR3:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32)
+ ; VI: [[BUILD_VECTOR3:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV3]](s32), [[LSHR9]](s32), [[LSHR10]](s32), [[LSHR11]](s32)
; VI: [[TRUNC3:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR3]](<4 x s32>)
; VI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
; VI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C1]](s32)
; VI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C2]](s32)
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; VI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; VI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; VI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; VI: [[BUILD_VECTOR4:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32)
+ ; VI: [[BUILD_VECTOR4:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV4]](s32), [[LSHR12]](s32), [[LSHR13]](s32), [[LSHR14]](s32)
; VI: [[TRUNC4:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR4]](<4 x s32>)
; VI: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
; VI: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C1]](s32)
; VI: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C2]](s32)
- ; VI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; VI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; VI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; VI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; VI: [[BUILD_VECTOR5:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32)
+ ; VI: [[BUILD_VECTOR5:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV5]](s32), [[LSHR15]](s32), [[LSHR16]](s32), [[LSHR17]](s32)
; VI: [[TRUNC5:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR5]](<4 x s32>)
; VI: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C]](s32)
; VI: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C1]](s32)
; VI: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C2]](s32)
- ; VI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; VI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; VI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; VI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; VI: [[BUILD_VECTOR6:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32)
+ ; VI: [[BUILD_VECTOR6:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV6]](s32), [[LSHR18]](s32), [[LSHR19]](s32), [[LSHR20]](s32)
; VI: [[TRUNC6:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR6]](<4 x s32>)
; VI: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C]](s32)
; VI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C1]](s32)
; VI: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C2]](s32)
- ; VI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; VI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; VI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; VI: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; VI: [[BUILD_VECTOR7:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32), [[COPY32]](s32)
+ ; VI: [[BUILD_VECTOR7:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV7]](s32), [[LSHR21]](s32), [[LSHR22]](s32), [[LSHR23]](s32)
; VI: [[TRUNC7:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR7]](<4 x s32>)
; VI: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s8>), [[TRUNC1]](<4 x s8>), [[TRUNC2]](<4 x s8>), [[TRUNC3]](<4 x s8>), [[TRUNC4]](<4 x s8>), [[TRUNC5]](<4 x s8>), [[TRUNC6]](<4 x s8>), [[TRUNC7]](<4 x s8>)
; VI: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[CONCAT_VECTORS]](<32 x s8>)
@@ -4038,89 +3641,57 @@ body: |
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[UV]](s32), [[LSHR]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR1]](s32), [[LSHR2]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<4 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[UV1]](s32), [[LSHR3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR4]](s32), [[LSHR5]](s32)
; GFX9: [[CONCAT_VECTORS1:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>)
; GFX9: [[TRUNC1:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS1]](<4 x s16>)
; GFX9: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; GFX9: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; GFX9: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[UV2]](s32), [[LSHR6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR7]](s32), [[LSHR8]](s32)
; GFX9: [[CONCAT_VECTORS2:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC4]](<2 x s16>), [[BUILD_VECTOR_TRUNC5]](<2 x s16>)
; GFX9: [[TRUNC2:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS2]](<4 x s16>)
; GFX9: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; GFX9: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; GFX9: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[UV3]](s32), [[LSHR9]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR10]](s32), [[LSHR11]](s32)
; GFX9: [[CONCAT_VECTORS3:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC6]](<2 x s16>), [[BUILD_VECTOR_TRUNC7]](<2 x s16>)
; GFX9: [[TRUNC3:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS3]](<4 x s16>)
; GFX9: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
; GFX9: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C1]](s32)
; GFX9: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C2]](s32)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC9:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[UV4]](s32), [[LSHR12]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC9:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR13]](s32), [[LSHR14]](s32)
; GFX9: [[CONCAT_VECTORS4:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC8]](<2 x s16>), [[BUILD_VECTOR_TRUNC9]](<2 x s16>)
; GFX9: [[TRUNC4:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS4]](<4 x s16>)
; GFX9: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
; GFX9: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C1]](s32)
; GFX9: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C2]](s32)
- ; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC10:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
- ; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; GFX9: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC11:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC10:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[UV5]](s32), [[LSHR15]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC11:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR16]](s32), [[LSHR17]](s32)
; GFX9: [[CONCAT_VECTORS5:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC10]](<2 x s16>), [[BUILD_VECTOR_TRUNC11]](<2 x s16>)
; GFX9: [[TRUNC5:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS5]](<4 x s16>)
; GFX9: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C]](s32)
; GFX9: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C1]](s32)
; GFX9: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C2]](s32)
- ; GFX9: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; GFX9: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC12:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY25]](s32), [[COPY26]](s32)
- ; GFX9: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; GFX9: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC13:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY27]](s32), [[COPY28]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC12:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[UV6]](s32), [[LSHR18]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC13:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR19]](s32), [[LSHR20]](s32)
; GFX9: [[CONCAT_VECTORS6:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC12]](<2 x s16>), [[BUILD_VECTOR_TRUNC13]](<2 x s16>)
; GFX9: [[TRUNC6:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS6]](<4 x s16>)
; GFX9: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C]](s32)
; GFX9: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C1]](s32)
; GFX9: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C2]](s32)
- ; GFX9: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; GFX9: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC14:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY29]](s32), [[COPY30]](s32)
- ; GFX9: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; GFX9: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC15:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY31]](s32), [[COPY32]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC14:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[UV7]](s32), [[LSHR21]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC15:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR22]](s32), [[LSHR23]](s32)
; GFX9: [[CONCAT_VECTORS7:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC14]](<2 x s16>), [[BUILD_VECTOR_TRUNC15]](<2 x s16>)
; GFX9: [[TRUNC7:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS7]](<4 x s16>)
; GFX9: [[CONCAT_VECTORS8:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s8>), [[TRUNC1]](<4 x s8>), [[TRUNC2]](<4 x s8>), [[TRUNC3]](<4 x s8>), [[TRUNC4]](<4 x s8>), [[TRUNC5]](<4 x s8>), [[TRUNC6]](<4 x s8>), [[TRUNC7]](<4 x s8>)
@@ -4167,10 +3738,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 4)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -4183,10 +3752,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 4)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -4198,9 +3765,7 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 4)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(p4) = COPY $vgpr0_vgpr1
%1:_(<2 x s16>) = G_LOAD %0 :: (load (<2 x s16>), align 2, addrspace 4)
@@ -4224,8 +3789,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -4236,10 +3800,9 @@ body: |
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -4338,24 +3901,18 @@ body: |
; CI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; CI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -4378,24 +3935,18 @@ body: |
; VI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -4417,15 +3968,9 @@ body: |
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[BITCAST2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[BITCAST3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(p4) = COPY $vgpr0_vgpr1
@@ -4461,24 +4006,18 @@ body: |
; CI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -4504,24 +4043,18 @@ body: |
; VI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -4546,15 +4079,9 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C2]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[BITCAST]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(p4) = COPY $vgpr0_vgpr1
@@ -4590,24 +4117,18 @@ body: |
; CI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -4633,24 +4154,18 @@ body: |
; VI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -4675,15 +4190,9 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C2]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[BITCAST]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(p4) = COPY $vgpr0_vgpr1
@@ -4710,8 +4219,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -4722,10 +4230,9 @@ body: |
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
@@ -4735,10 +4242,9 @@ body: |
; CI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p4) :: (load (s8) from unknown-address + 5, addrspace 4)
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
@@ -4758,15 +4264,12 @@ body: |
; CI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; CI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; CI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C7]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C6]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; CI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C7]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C7]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL5]]
; CI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
@@ -4825,15 +4328,12 @@ body: |
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C6]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C6]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C6]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C6]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C5]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL5]]
; VI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
@@ -4889,11 +4389,8 @@ body: |
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[OR1]](s16)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX9: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[OR2]](s16)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[COPY1]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[BITCAST]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(p4) = COPY $vgpr0_vgpr1
@@ -4968,18 +4465,14 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -4998,18 +4491,14 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -5027,12 +4516,8 @@ body: |
; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
%0:_(p4) = COPY $vgpr0_vgpr1
@@ -5057,8 +4542,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -5069,10 +4553,9 @@ body: |
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -5088,10 +4571,9 @@ body: |
; CI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p4) :: (load (s8) from unknown-address + 5, addrspace 4)
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[PTR_ADD5:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
@@ -5100,10 +4582,9 @@ body: |
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 4)
; CI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C1]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY6]](s32)
+ ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
+ ; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY3]](s32)
; CI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; CI: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
; CI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
@@ -5316,10 +4797,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 4)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -5328,10 +4807,8 @@ body: |
; CI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (load (s16) from unknown-address + 4, addrspace 4)
; CI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -5343,10 +4820,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 4)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -5355,10 +4830,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (load (s16) from unknown-address + 4, addrspace 4)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -5370,10 +4843,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 4)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -5382,10 +4853,8 @@ body: |
; GFX9: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (load (s16) from unknown-address + 4, addrspace 4)
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -5414,20 +4883,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -5440,18 +4905,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 4)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 4)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -5469,20 +4930,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -5495,18 +4952,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 4)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 4)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -5524,20 +4977,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -5550,18 +4999,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 4)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 4)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -5845,17 +5290,13 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -5868,16 +5309,12 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s16) from unknown-address + 12, addrspace 4)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s16) from unknown-address + 14, addrspace 4)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR3]](s32)
@@ -5896,17 +5333,13 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -5919,16 +5352,12 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s16) from unknown-address + 12, addrspace 4)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s16) from unknown-address + 14, addrspace 4)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; VI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR3]](s32)
@@ -5947,17 +5376,13 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 4)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -5970,16 +5395,12 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s16) from unknown-address + 12, addrspace 4)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s16) from unknown-address + 14, addrspace 4)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX9: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR3]](s32)
@@ -6026,31 +5447,27 @@ body: |
; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -6083,34 +5500,30 @@ body: |
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p4) :: (load (s8) from unknown-address + 15, addrspace 4)
; CI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD8]](s32)
; CI: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C7]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C9]]
- ; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY8]](s32)
+ ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C9]]
+ ; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY4]](s32)
; CI: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; CI: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
; CI: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD10]](s32)
; CI: [[AND10:%[0-9]+]]:_(s16) = G_AND [[TRUNC10]], [[C7]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C9]]
- ; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY10]](s32)
+ ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C9]]
+ ; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY5]](s32)
; CI: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL7]](s32)
; CI: [[OR7:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC11]]
; CI: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD12]](s32)
; CI: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC12]], [[C7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C9]]
- ; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY12]](s32)
+ ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C9]]
+ ; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY6]](s32)
; CI: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
; CI: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[TRUNC13]]
; CI: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD14]](s32)
; CI: [[AND14:%[0-9]+]]:_(s16) = G_AND [[TRUNC14]], [[C7]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C9]]
- ; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY14]](s32)
+ ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C9]]
+ ; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY7]](s32)
; CI: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[SHL9]](s32)
; CI: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[TRUNC15]]
; CI: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
@@ -6469,31 +5882,27 @@ body: |
; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -6526,34 +5935,30 @@ body: |
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p4) :: (load (s8) from unknown-address + 15, addrspace 4)
; CI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD8]](s32)
; CI: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C7]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C9]]
- ; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY8]](s32)
+ ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C9]]
+ ; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY4]](s32)
; CI: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; CI: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
; CI: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD10]](s32)
; CI: [[AND10:%[0-9]+]]:_(s16) = G_AND [[TRUNC10]], [[C7]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C9]]
- ; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY10]](s32)
+ ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C9]]
+ ; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY5]](s32)
; CI: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL7]](s32)
; CI: [[OR7:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC11]]
; CI: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD12]](s32)
; CI: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC12]], [[C7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C9]]
- ; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY12]](s32)
+ ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C9]]
+ ; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY6]](s32)
; CI: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
; CI: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[TRUNC13]]
; CI: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD14]](s32)
; CI: [[AND14:%[0-9]+]]:_(s16) = G_AND [[TRUNC14]], [[C7]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C9]]
- ; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY14]](s32)
+ ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C9]]
+ ; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY7]](s32)
; CI: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[SHL9]](s32)
; CI: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[TRUNC15]]
; CI: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
@@ -6584,34 +5989,30 @@ body: |
; CI: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p4) :: (load (s8) from unknown-address + 23, addrspace 4)
; CI: [[TRUNC16:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD16]](s32)
; CI: [[AND16:%[0-9]+]]:_(s16) = G_AND [[TRUNC16]], [[C7]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; CI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C9]]
- ; CI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[COPY16]](s32)
+ ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C9]]
+ ; CI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[COPY8]](s32)
; CI: [[TRUNC17:%[0-9]+]]:_(s16) = G_TRUNC [[SHL12]](s32)
; CI: [[OR12:%[0-9]+]]:_(s16) = G_OR [[AND16]], [[TRUNC17]]
; CI: [[TRUNC18:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD18]](s32)
; CI: [[AND18:%[0-9]+]]:_(s16) = G_AND [[TRUNC18]], [[C7]]
- ; CI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; CI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C9]]
- ; CI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[COPY18]](s32)
+ ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C9]]
+ ; CI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[COPY9]](s32)
; CI: [[TRUNC19:%[0-9]+]]:_(s16) = G_TRUNC [[SHL13]](s32)
; CI: [[OR13:%[0-9]+]]:_(s16) = G_OR [[AND18]], [[TRUNC19]]
; CI: [[TRUNC20:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD20]](s32)
; CI: [[AND20:%[0-9]+]]:_(s16) = G_AND [[TRUNC20]], [[C7]]
- ; CI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; CI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C9]]
- ; CI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[COPY20]](s32)
+ ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C9]]
+ ; CI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[COPY10]](s32)
; CI: [[TRUNC21:%[0-9]+]]:_(s16) = G_TRUNC [[SHL14]](s32)
; CI: [[OR14:%[0-9]+]]:_(s16) = G_OR [[AND20]], [[TRUNC21]]
; CI: [[TRUNC22:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD22]](s32)
; CI: [[AND22:%[0-9]+]]:_(s16) = G_AND [[TRUNC22]], [[C7]]
- ; CI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; CI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C9]]
- ; CI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[COPY22]](s32)
+ ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C9]]
+ ; CI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[COPY11]](s32)
; CI: [[TRUNC23:%[0-9]+]]:_(s16) = G_TRUNC [[SHL15]](s32)
; CI: [[OR15:%[0-9]+]]:_(s16) = G_OR [[AND22]], [[TRUNC23]]
; CI: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[OR12]](s16)
@@ -7044,31 +6445,27 @@ body: |
; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -7101,34 +6498,30 @@ body: |
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p4) :: (load (s8) from unknown-address + 15, addrspace 4)
; CI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD8]](s32)
; CI: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C7]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C9]]
- ; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY8]](s32)
+ ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C9]]
+ ; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY4]](s32)
; CI: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; CI: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
; CI: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD10]](s32)
; CI: [[AND10:%[0-9]+]]:_(s16) = G_AND [[TRUNC10]], [[C7]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C9]]
- ; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY10]](s32)
+ ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C9]]
+ ; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY5]](s32)
; CI: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL7]](s32)
; CI: [[OR7:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC11]]
; CI: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD12]](s32)
; CI: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC12]], [[C7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C9]]
- ; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY12]](s32)
+ ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C9]]
+ ; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY6]](s32)
; CI: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
; CI: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[TRUNC13]]
; CI: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD14]](s32)
; CI: [[AND14:%[0-9]+]]:_(s16) = G_AND [[TRUNC14]], [[C7]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C9]]
- ; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY14]](s32)
+ ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C9]]
+ ; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY7]](s32)
; CI: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[SHL9]](s32)
; CI: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[TRUNC15]]
; CI: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
@@ -7159,34 +6552,30 @@ body: |
; CI: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p4) :: (load (s8) from unknown-address + 23, addrspace 4)
; CI: [[TRUNC16:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD16]](s32)
; CI: [[AND16:%[0-9]+]]:_(s16) = G_AND [[TRUNC16]], [[C7]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; CI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C9]]
- ; CI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[COPY16]](s32)
+ ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C9]]
+ ; CI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[COPY8]](s32)
; CI: [[TRUNC17:%[0-9]+]]:_(s16) = G_TRUNC [[SHL12]](s32)
; CI: [[OR12:%[0-9]+]]:_(s16) = G_OR [[AND16]], [[TRUNC17]]
; CI: [[TRUNC18:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD18]](s32)
; CI: [[AND18:%[0-9]+]]:_(s16) = G_AND [[TRUNC18]], [[C7]]
- ; CI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; CI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C9]]
- ; CI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[COPY18]](s32)
+ ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C9]]
+ ; CI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[COPY9]](s32)
; CI: [[TRUNC19:%[0-9]+]]:_(s16) = G_TRUNC [[SHL13]](s32)
; CI: [[OR13:%[0-9]+]]:_(s16) = G_OR [[AND18]], [[TRUNC19]]
; CI: [[TRUNC20:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD20]](s32)
; CI: [[AND20:%[0-9]+]]:_(s16) = G_AND [[TRUNC20]], [[C7]]
- ; CI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; CI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C9]]
- ; CI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[COPY20]](s32)
+ ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C9]]
+ ; CI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[COPY10]](s32)
; CI: [[TRUNC21:%[0-9]+]]:_(s16) = G_TRUNC [[SHL14]](s32)
; CI: [[OR14:%[0-9]+]]:_(s16) = G_OR [[AND20]], [[TRUNC21]]
; CI: [[TRUNC22:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD22]](s32)
; CI: [[AND22:%[0-9]+]]:_(s16) = G_AND [[TRUNC22]], [[C7]]
- ; CI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; CI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C9]]
- ; CI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[COPY22]](s32)
+ ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C9]]
+ ; CI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[COPY11]](s32)
; CI: [[TRUNC23:%[0-9]+]]:_(s16) = G_TRUNC [[SHL15]](s32)
; CI: [[OR15:%[0-9]+]]:_(s16) = G_OR [[AND22]], [[TRUNC23]]
; CI: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[OR12]](s16)
@@ -7217,34 +6606,30 @@ body: |
; CI: [[LOAD31:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD30]](p4) :: (load (s8) from unknown-address + 31, addrspace 4)
; CI: [[TRUNC24:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD24]](s32)
; CI: [[AND24:%[0-9]+]]:_(s16) = G_AND [[TRUNC24]], [[C7]]
- ; CI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LOAD25]](s32)
- ; CI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C9]]
- ; CI: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[COPY24]](s32)
+ ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LOAD25]], [[C9]]
+ ; CI: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[COPY12]](s32)
; CI: [[TRUNC25:%[0-9]+]]:_(s16) = G_TRUNC [[SHL18]](s32)
; CI: [[OR18:%[0-9]+]]:_(s16) = G_OR [[AND24]], [[TRUNC25]]
; CI: [[TRUNC26:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD26]](s32)
; CI: [[AND26:%[0-9]+]]:_(s16) = G_AND [[TRUNC26]], [[C7]]
- ; CI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LOAD27]](s32)
- ; CI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C9]]
- ; CI: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[COPY26]](s32)
+ ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LOAD27]], [[C9]]
+ ; CI: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[COPY13]](s32)
; CI: [[TRUNC27:%[0-9]+]]:_(s16) = G_TRUNC [[SHL19]](s32)
; CI: [[OR19:%[0-9]+]]:_(s16) = G_OR [[AND26]], [[TRUNC27]]
; CI: [[TRUNC28:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD28]](s32)
; CI: [[AND28:%[0-9]+]]:_(s16) = G_AND [[TRUNC28]], [[C7]]
- ; CI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LOAD29]](s32)
- ; CI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C9]]
- ; CI: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[COPY28]](s32)
+ ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LOAD29]], [[C9]]
+ ; CI: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[COPY14]](s32)
; CI: [[TRUNC29:%[0-9]+]]:_(s16) = G_TRUNC [[SHL20]](s32)
; CI: [[OR20:%[0-9]+]]:_(s16) = G_OR [[AND28]], [[TRUNC29]]
; CI: [[TRUNC30:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD30]](s32)
; CI: [[AND30:%[0-9]+]]:_(s16) = G_AND [[TRUNC30]], [[C7]]
- ; CI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LOAD31]](s32)
- ; CI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C9]]
- ; CI: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[COPY30]](s32)
+ ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LOAD31]], [[C9]]
+ ; CI: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[COPY15]](s32)
; CI: [[TRUNC31:%[0-9]+]]:_(s16) = G_TRUNC [[SHL21]](s32)
; CI: [[OR21:%[0-9]+]]:_(s16) = G_OR [[AND30]], [[TRUNC31]]
; CI: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[OR18]](s16)
@@ -7810,20 +7195,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7836,18 +7217,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 4)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 4)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -7859,18 +7236,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p4) :: (load (s8) from unknown-address + 10, addrspace 4)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p4) :: (load (s8) from unknown-address + 11, addrspace 4)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
@@ -7882,18 +7255,14 @@ body: |
; CI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p4) :: (load (s8) from unknown-address + 14, addrspace 4)
; CI: [[PTR_ADD14:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p4) :: (load (s8) from unknown-address + 15, addrspace 4)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -7912,20 +7281,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7938,18 +7303,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 4)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 4)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -7961,18 +7322,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p4) :: (load (s8) from unknown-address + 10, addrspace 4)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p4) :: (load (s8) from unknown-address + 11, addrspace 4)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
@@ -7984,18 +7341,14 @@ body: |
; VI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p4) :: (load (s8) from unknown-address + 14, addrspace 4)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; VI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p4) :: (load (s8) from unknown-address + 15, addrspace 4)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -8014,20 +7367,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -8040,18 +7389,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 4)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 4)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -8063,18 +7408,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p4) :: (load (s8) from unknown-address + 10, addrspace 4)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p4) :: (load (s8) from unknown-address + 11, addrspace 4)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
@@ -8086,18 +7427,14 @@ body: |
; GFX9: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p4) :: (load (s8) from unknown-address + 14, addrspace 4)
; GFX9: [[PTR_ADD14:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; GFX9: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p4) :: (load (s8) from unknown-address + 15, addrspace 4)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX9: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX9: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX9: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX9: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX9: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX9: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -8173,20 +7510,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -8200,18 +7533,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 4)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 4)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR5]](s32)
@@ -8230,20 +7559,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -8257,18 +7582,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 4)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 4)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR5]](s32)
@@ -8287,20 +7608,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 4)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -8314,18 +7631,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 4)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 4)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR5]](s32)
@@ -8567,20 +7880,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 1)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -8593,18 +7902,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 1)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -8622,20 +7927,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -8648,18 +7949,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -8677,20 +7974,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 1)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -8703,18 +7996,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 1)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -8737,10 +8026,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 1)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -8749,10 +8036,8 @@ body: |
; CI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (load (s16) from unknown-address + 4, addrspace 1)
; CI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -8764,10 +8049,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -8776,10 +8059,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (load (s16) from unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -8791,10 +8072,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 1)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -8803,10 +8082,8 @@ body: |
; GFX9: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (load (s16) from unknown-address + 4, addrspace 1)
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -8904,20 +8181,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 1)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -8930,18 +8203,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 1)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -8953,18 +8222,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p4) :: (load (s8) from unknown-address + 10, addrspace 1)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p4) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -8978,18 +8243,14 @@ body: |
; CI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p4) :: (load (s8) from unknown-address + 14, addrspace 1)
; CI: [[PTR_ADD14:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p4) :: (load (s8) from unknown-address + 15, addrspace 1)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI: [[PTR_ADD15:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD11]], [[C7]](s64)
@@ -9000,18 +8261,14 @@ body: |
; CI: [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD17]](p4) :: (load (s8) from unknown-address + 18, addrspace 1)
; CI: [[PTR_ADD18:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD15]], [[C2]](s64)
; CI: [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD18]](p4) :: (load (s8) from unknown-address + 19, addrspace 1)
- ; CI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD16]](s32)
- ; CI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; CI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; CI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; CI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LOAD16]], [[C3]]
+ ; CI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C3]]
; CI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; CI: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; CI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD18]](s32)
- ; CI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; CI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LOAD18]], [[C3]]
; CI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C5]](s32)
; CI: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; CI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; CI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; CI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C3]]
; CI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C6]](s32)
; CI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; CI: [[PTR_ADD19:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD11]], [[C8]](s64)
@@ -9022,26 +8279,22 @@ body: |
; CI: [[LOAD22:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD21]](p4) :: (load (s8) from unknown-address + 22, addrspace 1)
; CI: [[PTR_ADD22:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD19]], [[C2]](s64)
; CI: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p4) :: (load (s8) from unknown-address + 23, addrspace 1)
- ; CI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD20]](s32)
- ; CI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; CI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; CI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; CI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD20]], [[C3]]
+ ; CI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C3]]
; CI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C4]](s32)
; CI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; CI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD22]](s32)
- ; CI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; CI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD22]], [[C3]]
; CI: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C5]](s32)
; CI: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; CI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; CI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; CI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C3]]
; CI: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C6]](s32)
; CI: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; CI: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR11]](s32), [[OR14]](s32), [[OR17]](s32)
; CI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; CI: [[COPY25:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; CI: [[COPY26:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; CI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY25]](s96)
- ; CI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY26]](s96)
+ ; CI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; CI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; CI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; CI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; VI-LABEL: name: test_extload_constant_v2s96_from_24_align1
; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 1)
@@ -9055,20 +8308,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -9081,18 +8330,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -9104,18 +8349,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p4) :: (load (s8) from unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p4) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -9129,18 +8370,14 @@ body: |
; VI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p4) :: (load (s8) from unknown-address + 14, addrspace 1)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; VI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p4) :: (load (s8) from unknown-address + 15, addrspace 1)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[PTR_ADD15:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD11]], [[C7]](s64)
@@ -9151,18 +8388,14 @@ body: |
; VI: [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD17]](p4) :: (load (s8) from unknown-address + 18, addrspace 1)
; VI: [[PTR_ADD18:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD15]], [[C2]](s64)
; VI: [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD18]](p4) :: (load (s8) from unknown-address + 19, addrspace 1)
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD16]](s32)
- ; VI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; VI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; VI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; VI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LOAD16]], [[C3]]
+ ; VI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C3]]
; VI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; VI: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; VI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD18]](s32)
- ; VI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; VI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LOAD18]], [[C3]]
; VI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C5]](s32)
; VI: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; VI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; VI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; VI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C3]]
; VI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C6]](s32)
; VI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; VI: [[PTR_ADD19:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD11]], [[C8]](s64)
@@ -9173,26 +8406,22 @@ body: |
; VI: [[LOAD22:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD21]](p4) :: (load (s8) from unknown-address + 22, addrspace 1)
; VI: [[PTR_ADD22:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD19]], [[C2]](s64)
; VI: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p4) :: (load (s8) from unknown-address + 23, addrspace 1)
- ; VI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD20]](s32)
- ; VI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; VI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; VI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; VI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD20]], [[C3]]
+ ; VI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C3]]
; VI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C4]](s32)
; VI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; VI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD22]](s32)
- ; VI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; VI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD22]], [[C3]]
; VI: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C5]](s32)
; VI: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; VI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; VI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; VI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C3]]
; VI: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C6]](s32)
; VI: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; VI: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR11]](s32), [[OR14]](s32), [[OR17]](s32)
; VI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; VI: [[COPY25:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; VI: [[COPY26:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY25]](s96)
- ; VI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY26]](s96)
+ ; VI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; VI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; VI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; GFX9-LABEL: name: test_extload_constant_v2s96_from_24_align1
; GFX9: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s8), addrspace 1)
@@ -9206,20 +8435,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s8) from unknown-address + 3, addrspace 1)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -9232,18 +8457,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s8) from unknown-address + 6, addrspace 1)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -9255,18 +8476,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p4) :: (load (s8) from unknown-address + 10, addrspace 1)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p4) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -9280,18 +8497,14 @@ body: |
; GFX9: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p4) :: (load (s8) from unknown-address + 14, addrspace 1)
; GFX9: [[PTR_ADD14:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; GFX9: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p4) :: (load (s8) from unknown-address + 15, addrspace 1)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX9: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX9: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX9: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX9: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX9: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX9: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9: [[PTR_ADD15:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD11]], [[C7]](s64)
@@ -9302,18 +8515,14 @@ body: |
; GFX9: [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD17]](p4) :: (load (s8) from unknown-address + 18, addrspace 1)
; GFX9: [[PTR_ADD18:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD15]], [[C2]](s64)
; GFX9: [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD18]](p4) :: (load (s8) from unknown-address + 19, addrspace 1)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD16]](s32)
- ; GFX9: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; GFX9: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; GFX9: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LOAD16]], [[C3]]
+ ; GFX9: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C3]]
; GFX9: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; GFX9: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD18]](s32)
- ; GFX9: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; GFX9: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LOAD18]], [[C3]]
; GFX9: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C5]](s32)
; GFX9: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; GFX9: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; GFX9: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C3]]
; GFX9: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C6]](s32)
; GFX9: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; GFX9: [[PTR_ADD19:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD11]], [[C8]](s64)
@@ -9324,26 +8533,22 @@ body: |
; GFX9: [[LOAD22:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD21]](p4) :: (load (s8) from unknown-address + 22, addrspace 1)
; GFX9: [[PTR_ADD22:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD19]], [[C2]](s64)
; GFX9: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p4) :: (load (s8) from unknown-address + 23, addrspace 1)
- ; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD20]](s32)
- ; GFX9: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; GFX9: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; GFX9: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD20]], [[C3]]
+ ; GFX9: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C3]]
; GFX9: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C4]](s32)
; GFX9: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD22]](s32)
- ; GFX9: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; GFX9: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD22]], [[C3]]
; GFX9: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C5]](s32)
; GFX9: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; GFX9: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; GFX9: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; GFX9: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C3]]
; GFX9: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C6]](s32)
; GFX9: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR11]](s32), [[OR14]](s32), [[OR17]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; GFX9: [[COPY25:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; GFX9: [[COPY26:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[COPY25]](s96)
- ; GFX9: $vgpr3_vgpr4_vgpr5 = COPY [[COPY26]](s96)
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; GFX9: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
%0:_(p4) = COPY $vgpr0_vgpr1
%1:_(<2 x s96>) = G_LOAD %0 :: (load (<2 x s96>), align 1, addrspace 1)
%2:_(s96) = G_EXTRACT %1, 0
@@ -9365,10 +8570,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 1)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -9377,10 +8580,8 @@ body: |
; CI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (load (s16) from unknown-address + 4, addrspace 1)
; CI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -9388,10 +8589,8 @@ body: |
; CI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p4) :: (load (s16) from unknown-address + 8, addrspace 1)
; CI: [[PTR_ADD4:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; CI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p4) :: (load (s16) from unknown-address + 10, addrspace 1)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -9401,38 +8600,32 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s16) from unknown-address + 12, addrspace 1)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD5]], [[C]](s64)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s16) from unknown-address + 14, addrspace 1)
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI: [[PTR_ADD7:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s64)
; CI: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD7]](p4) :: (load (s16) from unknown-address + 16, addrspace 1)
; CI: [[PTR_ADD8:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD7]], [[C]](s64)
; CI: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p4) :: (load (s16) from unknown-address + 18, addrspace 1)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C1]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C1]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; CI: [[PTR_ADD9:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD5]], [[C4]](s64)
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p4) :: (load (s16) from unknown-address + 20, addrspace 1)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD9]], [[C]](s64)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p4) :: (load (s16) from unknown-address + 22, addrspace 1)
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C1]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C1]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; CI: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR3]](s32), [[OR4]](s32), [[OR5]](s32)
; CI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; CI: [[COPY13:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; CI: [[COPY14:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; CI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY13]](s96)
- ; CI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY14]](s96)
+ ; CI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; CI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; CI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; CI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; VI-LABEL: name: test_extload_constant_v2s96_from_24_align2
; VI: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), addrspace 1)
@@ -9440,10 +8633,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -9452,10 +8643,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (load (s16) from unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -9463,10 +8652,8 @@ body: |
; VI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p4) :: (load (s16) from unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; VI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p4) :: (load (s16) from unknown-address + 10, addrspace 1)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -9476,38 +8663,32 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s16) from unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD5]], [[C]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s16) from unknown-address + 14, addrspace 1)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; VI: [[PTR_ADD7:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s64)
; VI: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD7]](p4) :: (load (s16) from unknown-address + 16, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD7]], [[C]](s64)
; VI: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p4) :: (load (s16) from unknown-address + 18, addrspace 1)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C1]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C1]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; VI: [[PTR_ADD9:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD5]], [[C4]](s64)
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p4) :: (load (s16) from unknown-address + 20, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD9]], [[C]](s64)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p4) :: (load (s16) from unknown-address + 22, addrspace 1)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C1]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C1]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; VI: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR3]](s32), [[OR4]](s32), [[OR5]](s32)
; VI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; VI: [[COPY13:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; VI: [[COPY14:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY13]](s96)
- ; VI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY14]](s96)
+ ; VI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; VI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; VI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; GFX9-LABEL: name: test_extload_constant_v2s96_from_24_align2
; GFX9: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: (load (s16), addrspace 1)
@@ -9515,10 +8696,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s16) from unknown-address + 2, addrspace 1)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -9527,10 +8706,8 @@ body: |
; GFX9: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p4) :: (load (s16) from unknown-address + 4, addrspace 1)
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p4) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -9538,10 +8715,8 @@ body: |
; GFX9: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p4) :: (load (s16) from unknown-address + 8, addrspace 1)
; GFX9: [[PTR_ADD4:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; GFX9: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p4) :: (load (s16) from unknown-address + 10, addrspace 1)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -9551,38 +8726,32 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p4) :: (load (s16) from unknown-address + 12, addrspace 1)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD5]], [[C]](s64)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p4) :: (load (s16) from unknown-address + 14, addrspace 1)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX9: [[PTR_ADD7:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s64)
; GFX9: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD7]](p4) :: (load (s16) from unknown-address + 16, addrspace 1)
; GFX9: [[PTR_ADD8:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD7]], [[C]](s64)
; GFX9: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p4) :: (load (s16) from unknown-address + 18, addrspace 1)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C1]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C1]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; GFX9: [[PTR_ADD9:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD5]], [[C4]](s64)
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p4) :: (load (s16) from unknown-address + 20, addrspace 1)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p4) = G_PTR_ADD [[PTR_ADD9]], [[C]](s64)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p4) :: (load (s16) from unknown-address + 22, addrspace 1)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C1]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C1]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR3]](s32), [[OR4]](s32), [[OR5]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[COPY13]](s96)
- ; GFX9: $vgpr3_vgpr4_vgpr5 = COPY [[COPY14]](s96)
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; GFX9: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
%0:_(p4) = COPY $vgpr0_vgpr1
%1:_(<2 x s96>) = G_LOAD %0 :: (load (<2 x s96>), align 2, addrspace 1)
%2:_(s96) = G_EXTRACT %1, 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
index c9b4aad635ff2..2641427afbdab 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
@@ -14,22 +14,19 @@ body: |
; CI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI: $vgpr0 = COPY [[AND]](s32)
; VI-LABEL: name: test_load_flat_s1_align1
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; VI: $vgpr0 = COPY [[AND]](s32)
; GFX9-LABEL: name: test_load_flat_s1_align1
; GFX9: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9: $vgpr0 = COPY [[AND]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s1) = G_LOAD %0 :: (load (s1), align 1, addrspace 0)
@@ -47,22 +44,19 @@ body: |
; CI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI: $vgpr0 = COPY [[AND]](s32)
; VI-LABEL: name: test_load_flat_s2_align1
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; VI: $vgpr0 = COPY [[AND]](s32)
; GFX9-LABEL: name: test_load_flat_s2_align1
; GFX9: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9: $vgpr0 = COPY [[AND]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s2) = G_LOAD %0 :: (load (s2), align 1, addrspace 0)
@@ -79,18 +73,15 @@ body: |
; CI-LABEL: name: test_load_flat_s8_align4
; CI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8), align 4)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_flat_s8_align4
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8), align 4)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_flat_s8_align4
; GFX9: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8), align 4)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s8) = G_LOAD %0 :: (load (s8), align 4, addrspace 0)
%2:_(s32) = G_ANYEXT %1
@@ -106,18 +97,15 @@ body: |
; CI-LABEL: name: test_load_flat_s8_align1
; CI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_flat_s8_align1
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_flat_s8_align1
; GFX9: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s8) = G_LOAD %0 :: (load (s8), align 1, addrspace 0)
%2:_(s32) = G_ANYEXT %1
@@ -133,18 +121,15 @@ body: |
; CI-LABEL: name: test_load_flat_s16_align4
; CI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16), align 4)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_flat_s16_align4
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16), align 4)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_flat_s16_align4
; GFX9: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16), align 4)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s16) = G_LOAD %0 :: (load (s16), align 4, addrspace 0)
%2:_(s32) = G_ANYEXT %1
@@ -160,18 +145,15 @@ body: |
; CI-LABEL: name: test_load_flat_s16_align2
; CI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_flat_s16_align2
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_flat_s16_align2
; GFX9: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s16) = G_LOAD %0 :: (load (s16), align 2, addrspace 0)
%2:_(s32) = G_ANYEXT %1
@@ -195,8 +177,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -276,10 +257,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -291,10 +270,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -306,10 +283,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -338,20 +313,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -369,20 +340,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -400,20 +367,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -433,22 +396,19 @@ body: |
; CI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; CI: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
; CI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
- ; CI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; CI: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
+ ; CI: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
; CI: $vgpr0_vgpr1 = COPY [[AND]](s64)
; VI-LABEL: name: test_load_flat_s48_align8
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
; VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
- ; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; VI: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
; VI: $vgpr0_vgpr1 = COPY [[AND]](s64)
; GFX9-LABEL: name: test_load_flat_s48_align8
; GFX9: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
; GFX9: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
- ; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; GFX9: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
; GFX9: $vgpr0_vgpr1 = COPY [[AND]](s64)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s48) = G_LOAD %0 :: (load (s48), align 8, addrspace 0)
@@ -521,17 +481,13 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s16) from unknown-address + 6)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -549,17 +505,13 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s16) from unknown-address + 6)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -577,17 +529,13 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s16) from unknown-address + 6)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -633,31 +581,27 @@ body: |
; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -890,10 +834,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -902,10 +844,8 @@ body: |
; CI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s16) from unknown-address + 4)
; CI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s16) from unknown-address + 6)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -913,10 +853,8 @@ body: |
; CI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p0) :: (load (s16) from unknown-address + 8)
; CI: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; CI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p0) :: (load (s16) from unknown-address + 10)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -929,10 +867,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -941,10 +877,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s16) from unknown-address + 4)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s16) from unknown-address + 6)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -952,10 +886,8 @@ body: |
; VI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p0) :: (load (s16) from unknown-address + 8)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; VI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p0) :: (load (s16) from unknown-address + 10)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -968,10 +900,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -980,10 +910,8 @@ body: |
; GFX9: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s16) from unknown-address + 4)
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s16) from unknown-address + 6)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -991,10 +919,8 @@ body: |
; GFX9: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p0) :: (load (s16) from unknown-address + 8)
; GFX9: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; GFX9: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p0) :: (load (s16) from unknown-address + 10)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -1024,20 +950,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1050,18 +972,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s8) from unknown-address + 6)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s8) from unknown-address + 7)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -1073,18 +991,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p0) :: (load (s8) from unknown-address + 10)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p0) :: (load (s8) from unknown-address + 11)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -1103,20 +1017,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1129,18 +1039,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s8) from unknown-address + 6)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s8) from unknown-address + 7)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -1152,18 +1058,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p0) :: (load (s8) from unknown-address + 10)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p0) :: (load (s8) from unknown-address + 11)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -1182,20 +1084,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1208,18 +1106,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s8) from unknown-address + 6)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s8) from unknown-address + 7)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -1231,18 +1125,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p0) :: (load (s8) from unknown-address + 10)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p0) :: (load (s8) from unknown-address + 11)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -1436,20 +1326,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1462,18 +1348,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s8) from unknown-address + 6)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s8) from unknown-address + 7)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -1485,18 +1367,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p0) :: (load (s8) from unknown-address + 10)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p0) :: (load (s8) from unknown-address + 11)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
@@ -1508,18 +1386,14 @@ body: |
; CI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p0) :: (load (s8) from unknown-address + 14)
; CI: [[PTR_ADD14:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p0) :: (load (s8) from unknown-address + 15)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -1538,20 +1412,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1564,18 +1434,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s8) from unknown-address + 6)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s8) from unknown-address + 7)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -1587,18 +1453,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p0) :: (load (s8) from unknown-address + 10)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p0) :: (load (s8) from unknown-address + 11)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
@@ -1610,18 +1472,14 @@ body: |
; VI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p0) :: (load (s8) from unknown-address + 14)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; VI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p0) :: (load (s8) from unknown-address + 15)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -1640,20 +1498,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1666,18 +1520,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s8) from unknown-address + 6)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s8) from unknown-address + 7)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -1689,18 +1539,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p0) :: (load (s8) from unknown-address + 10)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p0) :: (load (s8) from unknown-address + 11)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
@@ -1712,18 +1558,14 @@ body: |
; GFX9: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p0) :: (load (s8) from unknown-address + 14)
; GFX9: [[PTR_ADD14:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; GFX9: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p0) :: (load (s8) from unknown-address + 15)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX9: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX9: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX9: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX9: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX9: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX9: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -1854,31 +1696,27 @@ body: |
; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -2108,17 +1946,13 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s16) from unknown-address + 6)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -2136,17 +1970,13 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s16) from unknown-address + 6)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -2164,17 +1994,13 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s16) from unknown-address + 6)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -2220,31 +2046,27 @@ body: |
; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -2422,10 +2244,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -2438,10 +2258,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -2454,10 +2272,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -2487,20 +2303,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2519,20 +2331,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2551,20 +2359,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2595,8 +2399,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -2667,8 +2470,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -2736,8 +2538,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -2803,25 +2604,22 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI: $vgpr0 = COPY [[COPY5]](s32)
+ ; CI: $vgpr0 = COPY [[OR2]](s32)
; VI-LABEL: name: test_load_flat_v3s8_align4
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
@@ -2850,8 +2648,7 @@ body: |
; VI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[OR2]](s32)
; GFX9-LABEL: name: test_load_flat_v3s8_align4
; GFX9: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
@@ -2880,8 +2677,7 @@ body: |
; GFX9: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[OR2]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(<3 x s8>) = G_LOAD %0 :: (load (<3 x s8>), align 4, addrspace 0)
%2:_(s24) = G_BITCAST %1
@@ -2911,15 +2707,13 @@ body: |
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -2928,8 +2722,7 @@ body: |
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI: $vgpr0 = COPY [[COPY4]](s32)
+ ; CI: $vgpr0 = COPY [[OR2]](s32)
; VI-LABEL: name: test_load_flat_v3s8_align1
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
@@ -2959,8 +2752,7 @@ body: |
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[OR2]](s32)
; GFX9-LABEL: name: test_load_flat_v3s8_align1
; GFX9: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
@@ -2990,8 +2782,7 @@ body: |
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[OR2]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(<3 x s8>) = G_LOAD %0 :: (load (<3 x s8>), align 1, addrspace 0)
%2:_(s24) = G_BITCAST %1
@@ -3015,18 +2806,14 @@ body: |
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CI: $vgpr0 = COPY [[OR2]](s32)
@@ -3040,18 +2827,14 @@ body: |
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; VI: $vgpr0 = COPY [[OR2]](s32)
@@ -3065,18 +2848,14 @@ body: |
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; GFX9: $vgpr0 = COPY [[OR2]](s32)
@@ -3108,18 +2887,14 @@ body: |
; CI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C2]](s32)
; CI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C3]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CI: $vgpr0 = COPY [[OR2]](s32)
@@ -3139,18 +2914,14 @@ body: |
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C2]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C3]](s32)
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C4]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; VI: $vgpr0 = COPY [[OR2]](s32)
@@ -3170,18 +2941,14 @@ body: |
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C2]](s32)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C3]](s32)
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C4]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; GFX9: $vgpr0 = COPY [[OR2]](s32)
@@ -3210,20 +2977,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3241,20 +3004,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3272,20 +3031,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3316,32 +3071,24 @@ body: |
; CI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; CI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -3360,32 +3107,24 @@ body: |
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -3404,32 +3143,24 @@ body: |
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -3466,60 +3197,44 @@ body: |
; CI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; CI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C]](s32)
; CI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C3]]
; CI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C1]](s32)
; CI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C3]]
; CI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C2]](s32)
; CI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -3544,60 +3259,44 @@ body: |
; VI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; VI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C1]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C2]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -3622,60 +3321,44 @@ body: |
; GFX9: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; GFX9: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
+ ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
; GFX9: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C]](s32)
; GFX9: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C3]]
; GFX9: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C1]](s32)
; GFX9: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C3]]
; GFX9: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C2]](s32)
; GFX9: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -3728,116 +3411,84 @@ body: |
; CI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C2]](s32)
; CI: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C3]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C4]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C4]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C4]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C4]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C4]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C2]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C4]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C3]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C4]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C4]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C4]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C4]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C1]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C4]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C4]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C2]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C4]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C4]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C3]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C4]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C4]]
+ ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C4]]
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C4]]
; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C1]](s32)
; CI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C4]]
+ ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C4]]
; CI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C2]](s32)
; CI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C4]]
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C4]]
; CI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C3]](s32)
; CI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
- ; CI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; CI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C4]]
- ; CI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; CI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C4]]
+ ; CI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[C4]]
+ ; CI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C4]]
; CI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C1]](s32)
; CI: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; CI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; CI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C4]]
+ ; CI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C4]]
; CI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C2]](s32)
; CI: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; CI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; CI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C4]]
+ ; CI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C4]]
; CI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C3]](s32)
; CI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
- ; CI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; CI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C4]]
- ; CI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; CI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C4]]
+ ; CI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C4]]
+ ; CI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C4]]
; CI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C1]](s32)
; CI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; CI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; CI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C4]]
+ ; CI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR16]], [[C4]]
; CI: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C2]](s32)
; CI: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; CI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; CI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C4]]
+ ; CI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR17]], [[C4]]
; CI: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C3]](s32)
; CI: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
- ; CI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; CI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C4]]
- ; CI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; CI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C4]]
+ ; CI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[UV6]], [[C4]]
+ ; CI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LSHR18]], [[C4]]
; CI: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[C1]](s32)
; CI: [[OR18:%[0-9]+]]:_(s32) = G_OR [[AND24]], [[SHL18]]
- ; CI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; CI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C4]]
+ ; CI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[LSHR19]], [[C4]]
; CI: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C2]](s32)
; CI: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
- ; CI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; CI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C4]]
+ ; CI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LSHR20]], [[C4]]
; CI: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[C3]](s32)
; CI: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
- ; CI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; CI: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C4]]
- ; CI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; CI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C4]]
+ ; CI: [[AND28:%[0-9]+]]:_(s32) = G_AND [[UV7]], [[C4]]
+ ; CI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LSHR21]], [[C4]]
; CI: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[C1]](s32)
; CI: [[OR21:%[0-9]+]]:_(s32) = G_OR [[AND28]], [[SHL21]]
- ; CI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; CI: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C4]]
+ ; CI: [[AND30:%[0-9]+]]:_(s32) = G_AND [[LSHR22]], [[C4]]
; CI: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[C2]](s32)
; CI: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
- ; CI: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; CI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C4]]
+ ; CI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LSHR23]], [[C4]]
; CI: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C3]](s32)
; CI: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32), [[OR14]](s32), [[OR17]](s32), [[OR20]](s32), [[OR23]](s32)
@@ -3878,116 +3529,84 @@ body: |
; VI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C2]](s32)
; VI: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C3]](s32)
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C4]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C4]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C4]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C4]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C4]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C4]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C2]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C4]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C3]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C4]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C4]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C4]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C4]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C1]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C4]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C4]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C2]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C4]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C4]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C3]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C4]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C4]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C4]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C4]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C1]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C4]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C4]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C2]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C4]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C4]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C3]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; VI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C4]]
- ; VI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; VI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C4]]
+ ; VI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[C4]]
+ ; VI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C4]]
; VI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C1]](s32)
; VI: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; VI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; VI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C4]]
+ ; VI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C4]]
; VI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C2]](s32)
; VI: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; VI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; VI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C4]]
+ ; VI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C4]]
; VI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C3]](s32)
; VI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
- ; VI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; VI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C4]]
- ; VI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; VI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C4]]
+ ; VI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C4]]
+ ; VI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C4]]
; VI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C1]](s32)
; VI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; VI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; VI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C4]]
+ ; VI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR16]], [[C4]]
; VI: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C2]](s32)
; VI: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; VI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; VI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C4]]
+ ; VI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR17]], [[C4]]
; VI: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C3]](s32)
; VI: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
- ; VI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; VI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C4]]
- ; VI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; VI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C4]]
+ ; VI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[UV6]], [[C4]]
+ ; VI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LSHR18]], [[C4]]
; VI: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[C1]](s32)
; VI: [[OR18:%[0-9]+]]:_(s32) = G_OR [[AND24]], [[SHL18]]
- ; VI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; VI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C4]]
+ ; VI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[LSHR19]], [[C4]]
; VI: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C2]](s32)
; VI: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
- ; VI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; VI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C4]]
+ ; VI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LSHR20]], [[C4]]
; VI: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[C3]](s32)
; VI: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
- ; VI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; VI: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C4]]
- ; VI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; VI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C4]]
+ ; VI: [[AND28:%[0-9]+]]:_(s32) = G_AND [[UV7]], [[C4]]
+ ; VI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LSHR21]], [[C4]]
; VI: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[C1]](s32)
; VI: [[OR21:%[0-9]+]]:_(s32) = G_OR [[AND28]], [[SHL21]]
- ; VI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; VI: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C4]]
+ ; VI: [[AND30:%[0-9]+]]:_(s32) = G_AND [[LSHR22]], [[C4]]
; VI: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[C2]](s32)
; VI: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
- ; VI: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; VI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C4]]
+ ; VI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LSHR23]], [[C4]]
; VI: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C3]](s32)
; VI: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32), [[OR14]](s32), [[OR17]](s32), [[OR20]](s32), [[OR23]](s32)
@@ -4028,116 +3647,84 @@ body: |
; GFX9: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C2]](s32)
; GFX9: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C3]](s32)
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C4]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C4]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C4]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C4]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C4]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C4]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C2]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C4]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C3]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C4]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C4]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C4]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C4]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C1]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C4]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C4]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C2]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C4]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C4]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C3]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C4]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C4]]
+ ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C4]]
+ ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C4]]
; GFX9: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C1]](s32)
; GFX9: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C4]]
+ ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C4]]
; GFX9: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C2]](s32)
; GFX9: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C4]]
+ ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C4]]
; GFX9: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C3]](s32)
; GFX9: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; GFX9: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C4]]
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; GFX9: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C4]]
+ ; GFX9: [[AND16:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[C4]]
+ ; GFX9: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C4]]
; GFX9: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C1]](s32)
; GFX9: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; GFX9: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C4]]
+ ; GFX9: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C4]]
; GFX9: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C2]](s32)
; GFX9: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; GFX9: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C4]]
+ ; GFX9: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C4]]
; GFX9: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C3]](s32)
; GFX9: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
- ; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; GFX9: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C4]]
- ; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; GFX9: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C4]]
+ ; GFX9: [[AND20:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C4]]
+ ; GFX9: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C4]]
; GFX9: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C1]](s32)
; GFX9: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; GFX9: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C4]]
+ ; GFX9: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR16]], [[C4]]
; GFX9: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C2]](s32)
; GFX9: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; GFX9: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; GFX9: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C4]]
+ ; GFX9: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR17]], [[C4]]
; GFX9: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C3]](s32)
; GFX9: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
- ; GFX9: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; GFX9: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C4]]
- ; GFX9: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; GFX9: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C4]]
+ ; GFX9: [[AND24:%[0-9]+]]:_(s32) = G_AND [[UV6]], [[C4]]
+ ; GFX9: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LSHR18]], [[C4]]
; GFX9: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[C1]](s32)
; GFX9: [[OR18:%[0-9]+]]:_(s32) = G_OR [[AND24]], [[SHL18]]
- ; GFX9: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; GFX9: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C4]]
+ ; GFX9: [[AND26:%[0-9]+]]:_(s32) = G_AND [[LSHR19]], [[C4]]
; GFX9: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C2]](s32)
; GFX9: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
- ; GFX9: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; GFX9: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C4]]
+ ; GFX9: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LSHR20]], [[C4]]
; GFX9: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[C3]](s32)
; GFX9: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
- ; GFX9: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; GFX9: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C4]]
- ; GFX9: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; GFX9: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C4]]
+ ; GFX9: [[AND28:%[0-9]+]]:_(s32) = G_AND [[UV7]], [[C4]]
+ ; GFX9: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LSHR21]], [[C4]]
; GFX9: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[C1]](s32)
; GFX9: [[OR21:%[0-9]+]]:_(s32) = G_OR [[AND28]], [[SHL21]]
- ; GFX9: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; GFX9: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C4]]
+ ; GFX9: [[AND30:%[0-9]+]]:_(s32) = G_AND [[LSHR22]], [[C4]]
; GFX9: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[C2]](s32)
; GFX9: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
- ; GFX9: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; GFX9: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C4]]
+ ; GFX9: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LSHR23]], [[C4]]
; GFX9: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C3]](s32)
; GFX9: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32), [[OR14]](s32), [[OR17]](s32), [[OR20]](s32), [[OR23]](s32)
@@ -4185,10 +3772,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -4201,10 +3786,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -4216,9 +3799,7 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(<2 x s16>) = G_LOAD %0 :: (load (<2 x s16>), align 2, addrspace 0)
@@ -4242,8 +3823,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -4254,10 +3834,9 @@ body: |
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -4356,24 +3935,18 @@ body: |
; CI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; CI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -4396,24 +3969,18 @@ body: |
; VI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -4435,15 +4002,9 @@ body: |
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[BITCAST2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[BITCAST3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(p0) = COPY $vgpr0_vgpr1
@@ -4479,24 +4040,18 @@ body: |
; CI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -4522,24 +4077,18 @@ body: |
; VI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -4564,15 +4113,9 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C2]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[BITCAST]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(p0) = COPY $vgpr0_vgpr1
@@ -4608,24 +4151,18 @@ body: |
; CI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -4651,24 +4188,18 @@ body: |
; VI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -4693,15 +4224,9 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C2]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[BITCAST]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(p0) = COPY $vgpr0_vgpr1
@@ -4728,8 +4253,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -4740,10 +4264,9 @@ body: |
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
@@ -4753,10 +4276,9 @@ body: |
; CI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p0) :: (load (s8) from unknown-address + 5)
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
@@ -4776,15 +4298,12 @@ body: |
; CI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; CI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; CI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C7]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C6]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; CI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C7]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C7]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL5]]
; CI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
@@ -4843,15 +4362,12 @@ body: |
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C6]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C6]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C6]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C6]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C5]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL5]]
; VI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
@@ -4907,11 +4423,8 @@ body: |
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[OR1]](s16)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX9: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[OR2]](s16)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[COPY1]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[BITCAST]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(p0) = COPY $vgpr0_vgpr1
@@ -4986,18 +4499,14 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s16) from unknown-address + 6)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -5016,18 +4525,14 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s16) from unknown-address + 6)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -5045,12 +4550,8 @@ body: |
; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s16) from unknown-address + 6)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
%0:_(p0) = COPY $vgpr0_vgpr1
@@ -5075,8 +4576,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -5087,10 +4587,9 @@ body: |
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -5106,10 +4605,9 @@ body: |
; CI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p0) :: (load (s8) from unknown-address + 5)
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
@@ -5118,10 +4616,9 @@ body: |
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s8) from unknown-address + 7)
; CI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C1]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY6]](s32)
+ ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
+ ; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY3]](s32)
; CI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; CI: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
; CI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
@@ -5638,17 +5135,13 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s16) from unknown-address + 6)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -5661,16 +5154,12 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s16) from unknown-address + 12)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s16) from unknown-address + 14)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR3]](s32)
@@ -5689,17 +5178,13 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s16) from unknown-address + 6)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -5712,16 +5197,12 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s16) from unknown-address + 12)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s16) from unknown-address + 14)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; VI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR3]](s32)
@@ -5740,17 +5221,13 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s16) from unknown-address + 6)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -5763,16 +5240,12 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s16) from unknown-address + 12)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s16) from unknown-address + 14)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX9: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR3]](s32)
@@ -5819,31 +5292,27 @@ body: |
; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -5876,34 +5345,30 @@ body: |
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p0) :: (load (s8) from unknown-address + 15)
; CI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD8]](s32)
; CI: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C7]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C9]]
- ; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY8]](s32)
+ ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C9]]
+ ; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY4]](s32)
; CI: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; CI: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
; CI: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD10]](s32)
; CI: [[AND10:%[0-9]+]]:_(s16) = G_AND [[TRUNC10]], [[C7]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C9]]
- ; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY10]](s32)
+ ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C9]]
+ ; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY5]](s32)
; CI: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL7]](s32)
; CI: [[OR7:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC11]]
; CI: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD12]](s32)
; CI: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC12]], [[C7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C9]]
- ; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY12]](s32)
+ ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C9]]
+ ; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY6]](s32)
; CI: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
; CI: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[TRUNC13]]
; CI: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD14]](s32)
; CI: [[AND14:%[0-9]+]]:_(s16) = G_AND [[TRUNC14]], [[C7]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C9]]
- ; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY14]](s32)
+ ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C9]]
+ ; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY7]](s32)
; CI: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[SHL9]](s32)
; CI: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[TRUNC15]]
; CI: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
@@ -6274,31 +5739,27 @@ body: |
; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -6331,34 +5792,30 @@ body: |
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p0) :: (load (s8) from unknown-address + 15)
; CI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD8]](s32)
; CI: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C7]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C9]]
- ; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY8]](s32)
+ ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C9]]
+ ; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY4]](s32)
; CI: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; CI: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
; CI: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD10]](s32)
; CI: [[AND10:%[0-9]+]]:_(s16) = G_AND [[TRUNC10]], [[C7]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C9]]
- ; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY10]](s32)
+ ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C9]]
+ ; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY5]](s32)
; CI: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL7]](s32)
; CI: [[OR7:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC11]]
; CI: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD12]](s32)
; CI: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC12]], [[C7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C9]]
- ; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY12]](s32)
+ ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C9]]
+ ; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY6]](s32)
; CI: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
; CI: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[TRUNC13]]
; CI: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD14]](s32)
; CI: [[AND14:%[0-9]+]]:_(s16) = G_AND [[TRUNC14]], [[C7]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C9]]
- ; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY14]](s32)
+ ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C9]]
+ ; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY7]](s32)
; CI: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[SHL9]](s32)
; CI: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[TRUNC15]]
; CI: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
@@ -6389,34 +5846,30 @@ body: |
; CI: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p0) :: (load (s8) from unknown-address + 23)
; CI: [[TRUNC16:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD16]](s32)
; CI: [[AND16:%[0-9]+]]:_(s16) = G_AND [[TRUNC16]], [[C7]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; CI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C9]]
- ; CI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[COPY16]](s32)
+ ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C9]]
+ ; CI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[COPY8]](s32)
; CI: [[TRUNC17:%[0-9]+]]:_(s16) = G_TRUNC [[SHL12]](s32)
; CI: [[OR12:%[0-9]+]]:_(s16) = G_OR [[AND16]], [[TRUNC17]]
; CI: [[TRUNC18:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD18]](s32)
; CI: [[AND18:%[0-9]+]]:_(s16) = G_AND [[TRUNC18]], [[C7]]
- ; CI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; CI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C9]]
- ; CI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[COPY18]](s32)
+ ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C9]]
+ ; CI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[COPY9]](s32)
; CI: [[TRUNC19:%[0-9]+]]:_(s16) = G_TRUNC [[SHL13]](s32)
; CI: [[OR13:%[0-9]+]]:_(s16) = G_OR [[AND18]], [[TRUNC19]]
; CI: [[TRUNC20:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD20]](s32)
; CI: [[AND20:%[0-9]+]]:_(s16) = G_AND [[TRUNC20]], [[C7]]
- ; CI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; CI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C9]]
- ; CI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[COPY20]](s32)
+ ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C9]]
+ ; CI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[COPY10]](s32)
; CI: [[TRUNC21:%[0-9]+]]:_(s16) = G_TRUNC [[SHL14]](s32)
; CI: [[OR14:%[0-9]+]]:_(s16) = G_OR [[AND20]], [[TRUNC21]]
; CI: [[TRUNC22:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD22]](s32)
; CI: [[AND22:%[0-9]+]]:_(s16) = G_AND [[TRUNC22]], [[C7]]
- ; CI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; CI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C9]]
- ; CI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[COPY22]](s32)
+ ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C9]]
+ ; CI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[COPY11]](s32)
; CI: [[TRUNC23:%[0-9]+]]:_(s16) = G_TRUNC [[SHL15]](s32)
; CI: [[OR15:%[0-9]+]]:_(s16) = G_OR [[AND22]], [[TRUNC23]]
; CI: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[OR12]](s16)
@@ -6873,31 +6326,27 @@ body: |
; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -6930,34 +6379,30 @@ body: |
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p0) :: (load (s8) from unknown-address + 15)
; CI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD8]](s32)
; CI: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C7]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C9]]
- ; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY8]](s32)
+ ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C9]]
+ ; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY4]](s32)
; CI: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; CI: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
; CI: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD10]](s32)
; CI: [[AND10:%[0-9]+]]:_(s16) = G_AND [[TRUNC10]], [[C7]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C9]]
- ; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY10]](s32)
+ ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C9]]
+ ; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY5]](s32)
; CI: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL7]](s32)
; CI: [[OR7:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC11]]
; CI: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD12]](s32)
; CI: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC12]], [[C7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C9]]
- ; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY12]](s32)
+ ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C9]]
+ ; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY6]](s32)
; CI: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
; CI: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[TRUNC13]]
; CI: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD14]](s32)
; CI: [[AND14:%[0-9]+]]:_(s16) = G_AND [[TRUNC14]], [[C7]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C9]]
- ; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY14]](s32)
+ ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C9]]
+ ; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY7]](s32)
; CI: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[SHL9]](s32)
; CI: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[TRUNC15]]
; CI: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
@@ -6989,34 +6434,30 @@ body: |
; CI: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p0) :: (load (s8) from unknown-address + 23)
; CI: [[TRUNC16:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD16]](s32)
; CI: [[AND16:%[0-9]+]]:_(s16) = G_AND [[TRUNC16]], [[C7]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; CI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C9]]
- ; CI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[COPY16]](s32)
+ ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C9]]
+ ; CI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[COPY8]](s32)
; CI: [[TRUNC17:%[0-9]+]]:_(s16) = G_TRUNC [[SHL12]](s32)
; CI: [[OR12:%[0-9]+]]:_(s16) = G_OR [[AND16]], [[TRUNC17]]
; CI: [[TRUNC18:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD18]](s32)
; CI: [[AND18:%[0-9]+]]:_(s16) = G_AND [[TRUNC18]], [[C7]]
- ; CI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; CI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C9]]
- ; CI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[COPY18]](s32)
+ ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C9]]
+ ; CI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[COPY9]](s32)
; CI: [[TRUNC19:%[0-9]+]]:_(s16) = G_TRUNC [[SHL13]](s32)
; CI: [[OR13:%[0-9]+]]:_(s16) = G_OR [[AND18]], [[TRUNC19]]
; CI: [[TRUNC20:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD20]](s32)
; CI: [[AND20:%[0-9]+]]:_(s16) = G_AND [[TRUNC20]], [[C7]]
- ; CI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; CI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C9]]
- ; CI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[COPY20]](s32)
+ ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C9]]
+ ; CI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[COPY10]](s32)
; CI: [[TRUNC21:%[0-9]+]]:_(s16) = G_TRUNC [[SHL14]](s32)
; CI: [[OR14:%[0-9]+]]:_(s16) = G_OR [[AND20]], [[TRUNC21]]
; CI: [[TRUNC22:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD22]](s32)
; CI: [[AND22:%[0-9]+]]:_(s16) = G_AND [[TRUNC22]], [[C7]]
- ; CI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; CI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C9]]
- ; CI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[COPY22]](s32)
+ ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C9]]
+ ; CI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[COPY11]](s32)
; CI: [[TRUNC23:%[0-9]+]]:_(s16) = G_TRUNC [[SHL15]](s32)
; CI: [[OR15:%[0-9]+]]:_(s16) = G_OR [[AND22]], [[TRUNC23]]
; CI: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[OR12]](s16)
@@ -7046,34 +6487,30 @@ body: |
; CI: [[LOAD31:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD30]](p0) :: (load (s8) from unknown-address + 31)
; CI: [[TRUNC24:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD24]](s32)
; CI: [[AND24:%[0-9]+]]:_(s16) = G_AND [[TRUNC24]], [[C7]]
- ; CI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LOAD25]](s32)
- ; CI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C9]]
- ; CI: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[COPY24]](s32)
+ ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LOAD25]], [[C9]]
+ ; CI: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[COPY12]](s32)
; CI: [[TRUNC25:%[0-9]+]]:_(s16) = G_TRUNC [[SHL18]](s32)
; CI: [[OR18:%[0-9]+]]:_(s16) = G_OR [[AND24]], [[TRUNC25]]
; CI: [[TRUNC26:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD26]](s32)
; CI: [[AND26:%[0-9]+]]:_(s16) = G_AND [[TRUNC26]], [[C7]]
- ; CI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LOAD27]](s32)
- ; CI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C9]]
- ; CI: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[COPY26]](s32)
+ ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LOAD27]], [[C9]]
+ ; CI: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[COPY13]](s32)
; CI: [[TRUNC27:%[0-9]+]]:_(s16) = G_TRUNC [[SHL19]](s32)
; CI: [[OR19:%[0-9]+]]:_(s16) = G_OR [[AND26]], [[TRUNC27]]
; CI: [[TRUNC28:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD28]](s32)
; CI: [[AND28:%[0-9]+]]:_(s16) = G_AND [[TRUNC28]], [[C7]]
- ; CI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LOAD29]](s32)
- ; CI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C9]]
- ; CI: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[COPY28]](s32)
+ ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LOAD29]], [[C9]]
+ ; CI: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[COPY14]](s32)
; CI: [[TRUNC29:%[0-9]+]]:_(s16) = G_TRUNC [[SHL20]](s32)
; CI: [[OR20:%[0-9]+]]:_(s16) = G_OR [[AND28]], [[TRUNC29]]
; CI: [[TRUNC30:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD30]](s32)
; CI: [[AND30:%[0-9]+]]:_(s16) = G_AND [[TRUNC30]], [[C7]]
- ; CI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LOAD31]](s32)
- ; CI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C9]]
- ; CI: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[COPY30]](s32)
+ ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LOAD31]], [[C9]]
+ ; CI: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[COPY15]](s32)
; CI: [[TRUNC31:%[0-9]+]]:_(s16) = G_TRUNC [[SHL21]](s32)
; CI: [[OR21:%[0-9]+]]:_(s16) = G_OR [[AND30]], [[TRUNC31]]
; CI: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[OR18]](s16)
@@ -7654,20 +7091,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7680,18 +7113,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s8) from unknown-address + 6)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s8) from unknown-address + 7)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -7703,18 +7132,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p0) :: (load (s8) from unknown-address + 10)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p0) :: (load (s8) from unknown-address + 11)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
@@ -7726,18 +7151,14 @@ body: |
; CI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p0) :: (load (s8) from unknown-address + 14)
; CI: [[PTR_ADD14:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p0) :: (load (s8) from unknown-address + 15)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -7756,20 +7177,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7782,18 +7199,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s8) from unknown-address + 6)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s8) from unknown-address + 7)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -7805,18 +7218,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p0) :: (load (s8) from unknown-address + 10)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p0) :: (load (s8) from unknown-address + 11)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
@@ -7828,18 +7237,14 @@ body: |
; VI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p0) :: (load (s8) from unknown-address + 14)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; VI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p0) :: (load (s8) from unknown-address + 15)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -7858,20 +7263,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7884,18 +7285,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s8) from unknown-address + 6)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s8) from unknown-address + 7)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -7907,18 +7304,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p0) :: (load (s8) from unknown-address + 10)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p0) :: (load (s8) from unknown-address + 11)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
@@ -7930,18 +7323,14 @@ body: |
; GFX9: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p0) :: (load (s8) from unknown-address + 14)
; GFX9: [[PTR_ADD14:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; GFX9: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p0) :: (load (s8) from unknown-address + 15)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX9: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX9: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX9: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX9: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX9: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX9: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -8017,20 +7406,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -8044,18 +7429,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s8) from unknown-address + 6)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s8) from unknown-address + 7)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR5]](s32)
@@ -8074,20 +7455,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -8101,18 +7478,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s8) from unknown-address + 6)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s8) from unknown-address + 7)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR5]](s32)
@@ -8131,20 +7504,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -8158,18 +7527,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p0) :: (load (s8) from unknown-address + 6)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p0) :: (load (s8) from unknown-address + 7)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR5]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
index 3978992758d96..f356f74bccf8c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
@@ -33,43 +33,37 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; SI: $vgpr0 = COPY [[AND]](s32)
; CI-HSA-LABEL: name: test_load_global_s1_align1
; CI-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
; CI-HSA: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI-HSA: $vgpr0 = COPY [[AND]](s32)
; CI-MESA-LABEL: name: test_load_global_s1_align1
; CI-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
; CI-MESA: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI-MESA: $vgpr0 = COPY [[AND]](s32)
; VI-LABEL: name: test_load_global_s1_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; VI: $vgpr0 = COPY [[AND]](s32)
; GFX9-HSA-LABEL: name: test_load_global_s1_align1
; GFX9-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
; GFX9-HSA: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX9-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9-HSA: $vgpr0 = COPY [[AND]](s32)
; GFX9-MESA-LABEL: name: test_load_global_s1_align1
; GFX9-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
; GFX9-MESA: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9-MESA: $vgpr0 = COPY [[AND]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s1) = G_LOAD %0 :: (load (s1), align 1, addrspace 1)
@@ -87,43 +81,37 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; SI: $vgpr0 = COPY [[AND]](s32)
; CI-HSA-LABEL: name: test_load_global_s2_align1
; CI-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
; CI-HSA: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI-HSA: $vgpr0 = COPY [[AND]](s32)
; CI-MESA-LABEL: name: test_load_global_s2_align1
; CI-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
; CI-MESA: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI-MESA: $vgpr0 = COPY [[AND]](s32)
; VI-LABEL: name: test_load_global_s2_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; VI: $vgpr0 = COPY [[AND]](s32)
; GFX9-HSA-LABEL: name: test_load_global_s2_align1
; GFX9-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
; GFX9-HSA: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX9-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9-HSA: $vgpr0 = COPY [[AND]](s32)
; GFX9-MESA-LABEL: name: test_load_global_s2_align1
; GFX9-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
; GFX9-MESA: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9-MESA: $vgpr0 = COPY [[AND]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s2) = G_LOAD %0 :: (load (s2), align 1, addrspace 1)
@@ -145,33 +133,27 @@ body: |
; SI-LABEL: name: test_load_global_s8_align4
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[LOAD]](s32)
; CI-HSA-LABEL: name: test_load_global_s8_align4
; CI-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-HSA: $vgpr0 = COPY [[LOAD]](s32)
; CI-MESA-LABEL: name: test_load_global_s8_align4
; CI-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-MESA: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_global_s8_align4
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-HSA-LABEL: name: test_load_global_s8_align4
; GFX9-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-HSA: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-MESA-LABEL: name: test_load_global_s8_align4
; GFX9-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-MESA: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s8) = G_LOAD %0 :: (load (s8), align 4, addrspace 1)
%2:_(s32) = G_ANYEXT %1
@@ -187,33 +169,27 @@ body: |
; SI-LABEL: name: test_load_global_s8_align1
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[LOAD]](s32)
; CI-HSA-LABEL: name: test_load_global_s8_align1
; CI-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-HSA: $vgpr0 = COPY [[LOAD]](s32)
; CI-MESA-LABEL: name: test_load_global_s8_align1
; CI-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-MESA: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_global_s8_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-HSA-LABEL: name: test_load_global_s8_align1
; GFX9-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-HSA: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-MESA-LABEL: name: test_load_global_s8_align1
; GFX9-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-MESA: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s8) = G_LOAD %0 :: (load (s8), align 1, addrspace 1)
%2:_(s32) = G_ANYEXT %1
@@ -229,33 +205,27 @@ body: |
; SI-LABEL: name: test_load_global_s16_align4
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[LOAD]](s32)
; CI-HSA-LABEL: name: test_load_global_s16_align4
; CI-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-HSA: $vgpr0 = COPY [[LOAD]](s32)
; CI-MESA-LABEL: name: test_load_global_s16_align4
; CI-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-MESA: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_global_s16_align4
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-HSA-LABEL: name: test_load_global_s16_align4
; GFX9-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-HSA: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-MESA-LABEL: name: test_load_global_s16_align4
; GFX9-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-MESA: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s16) = G_LOAD %0 :: (load (s16), align 4, addrspace 1)
%2:_(s32) = G_ANYEXT %1
@@ -271,33 +241,27 @@ body: |
; SI-LABEL: name: test_load_global_s16_align2
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[LOAD]](s32)
; CI-HSA-LABEL: name: test_load_global_s16_align2
; CI-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-HSA: $vgpr0 = COPY [[LOAD]](s32)
; CI-MESA-LABEL: name: test_load_global_s16_align2
; CI-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-MESA: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_global_s16_align2
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-HSA-LABEL: name: test_load_global_s16_align2
; GFX9-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-HSA: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-MESA-LABEL: name: test_load_global_s16_align2
; GFX9-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-MESA: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s16) = G_LOAD %0 :: (load (s16), align 2, addrspace 1)
%2:_(s32) = G_ANYEXT %1
@@ -343,8 +307,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -353,8 +316,7 @@ body: |
; CI-HSA-LABEL: name: test_load_global_s16_align1
; CI-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 1, addrspace 1)
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-HSA: $vgpr0 = COPY [[LOAD]](s32)
; CI-MESA-LABEL: name: test_load_global_s16_align1
; CI-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
@@ -366,8 +328,7 @@ body: |
; CI-MESA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -392,8 +353,7 @@ body: |
; GFX9-HSA-LABEL: name: test_load_global_s16_align1
; GFX9-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), align 1, addrspace 1)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-HSA: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-MESA-LABEL: name: test_load_global_s16_align1
; GFX9-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
@@ -464,10 +424,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -483,10 +441,8 @@ body: |
; CI-MESA: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-MESA: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; CI-MESA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -498,10 +454,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -517,10 +471,8 @@ body: |
; GFX9-MESA: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; GFX9-MESA: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; GFX9-MESA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -549,20 +501,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -584,20 +532,16 @@ body: |
; CI-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -615,20 +559,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -650,20 +590,16 @@ body: |
; GFX9-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; GFX9-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -682,33 +618,27 @@ body: |
; SI-LABEL: name: test_load_global_s24_align8
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), align 8, addrspace 1)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[LOAD]](s32)
; CI-HSA-LABEL: name: test_load_global_s24_align8
; CI-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), align 8, addrspace 1)
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-HSA: $vgpr0 = COPY [[LOAD]](s32)
; CI-MESA-LABEL: name: test_load_global_s24_align8
; CI-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), align 8, addrspace 1)
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-MESA: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_global_s24_align8
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), align 8, addrspace 1)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-HSA-LABEL: name: test_load_global_s24_align8
; GFX9-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), align 8, addrspace 1)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-HSA: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-MESA-LABEL: name: test_load_global_s24_align8
; GFX9-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), align 8, addrspace 1)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-MESA: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s24) = G_LOAD %0 :: (load (s24), align 8, addrspace 1)
%2:_(s32) = G_ANYEXT %1
@@ -724,33 +654,27 @@ body: |
; SI-LABEL: name: test_load_global_s24_align4
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[LOAD]](s32)
; CI-HSA-LABEL: name: test_load_global_s24_align4
; CI-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-HSA: $vgpr0 = COPY [[LOAD]](s32)
; CI-MESA-LABEL: name: test_load_global_s24_align4
; CI-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-MESA: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_global_s24_align4
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-HSA-LABEL: name: test_load_global_s24_align4
; GFX9-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-HSA: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-MESA-LABEL: name: test_load_global_s24_align4
; GFX9-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-MESA: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s24) = G_LOAD %0 :: (load (s24), align 4, addrspace 1)
%2:_(s32) = G_ANYEXT %1
@@ -781,25 +705,22 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD1]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C5]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; SI: $vgpr0 = COPY [[COPY5]](s32)
+ ; SI: $vgpr0 = COPY [[OR2]](s32)
; CI-HSA-LABEL: name: test_load_global_s24_align2
; CI-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), addrspace 1)
@@ -809,8 +730,7 @@ body: |
; CI-HSA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CI-HSA: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-HSA: $vgpr0 = COPY [[OR]](s32)
; CI-MESA-LABEL: name: test_load_global_s24_align2
; CI-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
@@ -829,25 +749,22 @@ body: |
; CI-MESA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CI-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-MESA: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD1]](s32)
; CI-MESA: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
- ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C5]]
+ ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI-MESA: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-MESA: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CI-MESA: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI-MESA: $vgpr0 = COPY [[COPY5]](s32)
+ ; CI-MESA: $vgpr0 = COPY [[OR2]](s32)
; VI-LABEL: name: test_load_global_s24_align2
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
@@ -879,8 +796,7 @@ body: |
; VI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[OR2]](s32)
; GFX9-HSA-LABEL: name: test_load_global_s24_align2
; GFX9-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), addrspace 1)
@@ -890,8 +806,7 @@ body: |
; GFX9-HSA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX9-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; GFX9-HSA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-HSA: $vgpr0 = COPY [[OR]](s32)
; GFX9-MESA-LABEL: name: test_load_global_s24_align2
; GFX9-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
@@ -923,8 +838,7 @@ body: |
; GFX9-MESA: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9-MESA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-MESA: $vgpr0 = COPY [[OR2]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s24) = G_LOAD %0 :: (load (s24), align 2, addrspace 1)
%2:_(s32) = G_ANYEXT %1
@@ -953,15 +867,13 @@ body: |
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -970,8 +882,7 @@ body: |
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[OR2]](s32)
; CI-HSA-LABEL: name: test_load_global_s24_align1
; CI-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), align 1, addrspace 1)
@@ -981,8 +892,7 @@ body: |
; CI-HSA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CI-HSA: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-HSA: $vgpr0 = COPY [[OR]](s32)
; CI-MESA-LABEL: name: test_load_global_s24_align1
; CI-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
@@ -999,15 +909,13 @@ body: |
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-MESA: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-MESA: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CI-MESA: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -1016,8 +924,7 @@ body: |
; CI-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI-MESA: $vgpr0 = COPY [[COPY4]](s32)
+ ; CI-MESA: $vgpr0 = COPY [[OR2]](s32)
; VI-LABEL: name: test_load_global_s24_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
@@ -1047,8 +954,7 @@ body: |
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[OR2]](s32)
; GFX9-HSA-LABEL: name: test_load_global_s24_align1
; GFX9-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), align 1, addrspace 1)
@@ -1058,8 +964,7 @@ body: |
; GFX9-HSA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX9-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; GFX9-HSA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-HSA: $vgpr0 = COPY [[OR]](s32)
; GFX9-MESA-LABEL: name: test_load_global_s24_align1
; GFX9-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
@@ -1089,8 +994,7 @@ body: |
; GFX9-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9-MESA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-MESA: $vgpr0 = COPY [[OR2]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s24) = G_LOAD %0 :: (load (s24), align 1, addrspace 1)
%2:_(s32) = G_ANYEXT %1
@@ -1114,43 +1018,37 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)
; SI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
- ; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; SI: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
; SI: $vgpr0_vgpr1 = COPY [[AND]](s64)
; CI-HSA-LABEL: name: test_load_global_s48_align8
; CI-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)
; CI-HSA: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; CI-HSA: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
+ ; CI-HSA: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
; CI-HSA: $vgpr0_vgpr1 = COPY [[AND]](s64)
; CI-MESA-LABEL: name: test_load_global_s48_align8
; CI-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)
; CI-MESA: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
; CI-MESA: $vgpr0_vgpr1 = COPY [[AND]](s64)
; VI-LABEL: name: test_load_global_s48_align8
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)
; VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
- ; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; VI: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
; VI: $vgpr0_vgpr1 = COPY [[AND]](s64)
; GFX9-HSA-LABEL: name: test_load_global_s48_align8
; GFX9-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)
; GFX9-HSA: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; GFX9-HSA: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
+ ; GFX9-HSA: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
; GFX9-HSA: $vgpr0_vgpr1 = COPY [[AND]](s64)
; GFX9-MESA-LABEL: name: test_load_global_s48_align8
; GFX9-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-MESA: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)
; GFX9-MESA: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], [[C]]
; GFX9-MESA: $vgpr0_vgpr1 = COPY [[AND]](s64)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s48) = G_LOAD %0 :: (load (s48), align 8, addrspace 1)
@@ -1247,17 +1145,13 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -1279,17 +1173,13 @@ body: |
; CI-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -1307,17 +1197,13 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -1339,17 +1225,13 @@ body: |
; GFX9-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
; GFX9-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; GFX9-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9-MESA: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -1395,31 +1277,27 @@ body: |
; SI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; SI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; SI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; SI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; SI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -1468,31 +1346,27 @@ body: |
; CI-MESA: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI-MESA: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-MESA: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-MESA: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI-MESA: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-MESA: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI-MESA: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI-MESA: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI-MESA: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI-MESA: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI-MESA: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -1785,10 +1659,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -1797,10 +1669,8 @@ body: |
; SI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s16) from unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -1808,10 +1678,8 @@ body: |
; SI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p1) :: (load (s16) from unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; SI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p1) :: (load (s16) from unknown-address + 10, addrspace 1)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -1829,10 +1697,8 @@ body: |
; CI-MESA: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-MESA: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; CI-MESA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -1841,10 +1707,8 @@ body: |
; CI-MESA: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s16) from unknown-address + 4, addrspace 1)
; CI-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -1852,10 +1716,8 @@ body: |
; CI-MESA: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p1) :: (load (s16) from unknown-address + 8, addrspace 1)
; CI-MESA: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; CI-MESA: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p1) :: (load (s16) from unknown-address + 10, addrspace 1)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -1868,10 +1730,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -1880,10 +1740,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s16) from unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -1891,10 +1749,8 @@ body: |
; VI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p1) :: (load (s16) from unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; VI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p1) :: (load (s16) from unknown-address + 10, addrspace 1)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -1912,10 +1768,8 @@ body: |
; GFX9-MESA: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; GFX9-MESA: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; GFX9-MESA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -1924,10 +1778,8 @@ body: |
; GFX9-MESA: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s16) from unknown-address + 4, addrspace 1)
; GFX9-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; GFX9-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9-MESA: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -1935,10 +1787,8 @@ body: |
; GFX9-MESA: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p1) :: (load (s16) from unknown-address + 8, addrspace 1)
; GFX9-MESA: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; GFX9-MESA: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p1) :: (load (s16) from unknown-address + 10, addrspace 1)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX9-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -1968,20 +1818,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1994,18 +1840,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -2017,18 +1859,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s8) from unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -2052,20 +1890,16 @@ body: |
; CI-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2078,18 +1912,14 @@ body: |
; CI-MESA: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; CI-MESA: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI-MESA: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -2101,18 +1931,14 @@ body: |
; CI-MESA: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s8) from unknown-address + 10, addrspace 1)
; CI-MESA: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; CI-MESA: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; CI-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI-MESA: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI-MESA: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI-MESA: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -2131,20 +1957,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2157,18 +1979,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -2180,18 +1998,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s8) from unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -2215,20 +2029,16 @@ body: |
; GFX9-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; GFX9-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2241,18 +2051,14 @@ body: |
; GFX9-MESA: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; GFX9-MESA: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9-MESA: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -2264,18 +2070,14 @@ body: |
; GFX9-MESA: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s8) from unknown-address + 10, addrspace 1)
; GFX9-MESA: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; GFX9-MESA: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; GFX9-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9-MESA: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9-MESA: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9-MESA: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -2598,20 +2400,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2624,18 +2422,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -2647,18 +2441,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s8) from unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
@@ -2670,18 +2460,14 @@ body: |
; SI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p1) :: (load (s8) from unknown-address + 14, addrspace 1)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; SI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p1) :: (load (s8) from unknown-address + 15, addrspace 1)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; SI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; SI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -2705,20 +2491,16 @@ body: |
; CI-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2731,18 +2513,14 @@ body: |
; CI-MESA: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; CI-MESA: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI-MESA: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -2754,18 +2532,14 @@ body: |
; CI-MESA: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s8) from unknown-address + 10, addrspace 1)
; CI-MESA: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; CI-MESA: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; CI-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI-MESA: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI-MESA: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI-MESA: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI-MESA: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
@@ -2777,18 +2551,14 @@ body: |
; CI-MESA: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p1) :: (load (s8) from unknown-address + 14, addrspace 1)
; CI-MESA: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; CI-MESA: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p1) :: (load (s8) from unknown-address + 15, addrspace 1)
- ; CI-MESA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI-MESA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI-MESA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI-MESA: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI-MESA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI-MESA: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI-MESA: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI-MESA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI-MESA: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI-MESA: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -2807,20 +2577,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2833,18 +2599,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -2856,18 +2618,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s8) from unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
@@ -2879,18 +2637,14 @@ body: |
; VI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p1) :: (load (s8) from unknown-address + 14, addrspace 1)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; VI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p1) :: (load (s8) from unknown-address + 15, addrspace 1)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -2914,20 +2668,16 @@ body: |
; GFX9-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; GFX9-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2940,18 +2690,14 @@ body: |
; GFX9-MESA: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; GFX9-MESA: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9-MESA: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -2963,18 +2709,14 @@ body: |
; GFX9-MESA: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s8) from unknown-address + 10, addrspace 1)
; GFX9-MESA: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; GFX9-MESA: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; GFX9-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9-MESA: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9-MESA: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9-MESA: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9-MESA: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
@@ -2986,18 +2728,14 @@ body: |
; GFX9-MESA: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p1) :: (load (s8) from unknown-address + 14, addrspace 1)
; GFX9-MESA: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; GFX9-MESA: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p1) :: (load (s8) from unknown-address + 15, addrspace 1)
- ; GFX9-MESA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX9-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9-MESA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX9-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX9-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX9-MESA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX9-MESA: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9-MESA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX9-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX9-MESA: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX9-MESA: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9-MESA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX9-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX9-MESA: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX9-MESA: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -3155,31 +2893,27 @@ body: |
; SI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; SI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; SI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; SI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; SI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -3228,31 +2962,27 @@ body: |
; CI-MESA: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI-MESA: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-MESA: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-MESA: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI-MESA: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-MESA: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI-MESA: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI-MESA: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI-MESA: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI-MESA: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI-MESA: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -3526,17 +3256,13 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -3558,17 +3284,13 @@ body: |
; CI-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -3586,17 +3308,13 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -3618,17 +3336,13 @@ body: |
; GFX9-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
; GFX9-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; GFX9-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9-MESA: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -3674,31 +3388,27 @@ body: |
; SI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; SI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; SI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; SI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; SI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -3747,31 +3457,27 @@ body: |
; CI-MESA: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI-MESA: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-MESA: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-MESA: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI-MESA: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-MESA: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI-MESA: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI-MESA: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI-MESA: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI-MESA: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI-MESA: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -3965,10 +3671,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -3985,10 +3689,8 @@ body: |
; CI-MESA: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-MESA: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; CI-MESA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -4001,10 +3703,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -4021,10 +3721,8 @@ body: |
; GFX9-MESA: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; GFX9-MESA: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; GFX9-MESA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -4054,20 +3752,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -4090,20 +3784,16 @@ body: |
; CI-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -4122,20 +3812,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -4158,20 +3844,16 @@ body: |
; GFX9-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; GFX9-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -4202,8 +3884,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -4223,8 +3904,7 @@ body: |
; CI-HSA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI-HSA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-HSA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -4244,8 +3924,7 @@ body: |
; CI-MESA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -4335,8 +4014,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -4356,8 +4034,7 @@ body: |
; CI-HSA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI-HSA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-HSA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -4377,8 +4054,7 @@ body: |
; CI-MESA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -4465,8 +4141,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -4486,8 +4161,7 @@ body: |
; CI-HSA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI-HSA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-HSA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -4504,8 +4178,7 @@ body: |
; CI-MESA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -4590,25 +4263,22 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; SI: $vgpr0 = COPY [[COPY5]](s32)
+ ; SI: $vgpr0 = COPY [[OR2]](s32)
; CI-HSA-LABEL: name: test_load_global_v3s8_align4
; CI-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
@@ -4624,25 +4294,22 @@ body: |
; CI-HSA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI-HSA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-HSA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-HSA: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; CI-HSA: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
- ; CI-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
+ ; CI-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI-HSA: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-HSA: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-HSA: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CI-HSA: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CI-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; CI-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI-HSA: $vgpr0 = COPY [[COPY5]](s32)
+ ; CI-HSA: $vgpr0 = COPY [[OR2]](s32)
; CI-MESA-LABEL: name: test_load_global_v3s8_align4
; CI-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
@@ -4658,25 +4325,22 @@ body: |
; CI-MESA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-MESA: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; CI-MESA: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
- ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
+ ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI-MESA: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-MESA: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CI-MESA: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI-MESA: $vgpr0 = COPY [[COPY5]](s32)
+ ; CI-MESA: $vgpr0 = COPY [[OR2]](s32)
; VI-LABEL: name: test_load_global_v3s8_align4
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
@@ -4705,8 +4369,7 @@ body: |
; VI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[OR2]](s32)
; GFX9-HSA-LABEL: name: test_load_global_v3s8_align4
; GFX9-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
@@ -4735,8 +4398,7 @@ body: |
; GFX9-HSA: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; GFX9-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX9-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9-HSA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-HSA: $vgpr0 = COPY [[OR2]](s32)
; GFX9-MESA-LABEL: name: test_load_global_v3s8_align4
; GFX9-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
@@ -4765,8 +4427,7 @@ body: |
; GFX9-MESA: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9-MESA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-MESA: $vgpr0 = COPY [[OR2]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(<3 x s8>) = G_LOAD %0 :: (load (<3 x s8>), align 4, addrspace 1)
%2:_(s24) = G_BITCAST %1
@@ -4797,15 +4458,13 @@ body: |
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -4814,8 +4473,7 @@ body: |
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[OR2]](s32)
; CI-HSA-LABEL: name: test_load_global_v3s8_align1
; CI-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), align 1, addrspace 1)
@@ -4836,25 +4494,22 @@ body: |
; CI-HSA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CI-HSA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
; CI-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-HSA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-HSA: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-HSA: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; CI-HSA: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
- ; CI-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C5]]
+ ; CI-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI-HSA: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI-HSA: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-HSA: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CI-HSA: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; CI-HSA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; CI-HSA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL3]]
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
- ; CI-HSA: $vgpr0 = COPY [[COPY5]](s32)
+ ; CI-HSA: $vgpr0 = COPY [[OR3]](s32)
; CI-MESA-LABEL: name: test_load_global_v3s8_align1
; CI-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
@@ -4871,15 +4526,13 @@ body: |
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-MESA: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-MESA: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CI-MESA: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -4888,8 +4541,7 @@ body: |
; CI-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI-MESA: $vgpr0 = COPY [[COPY4]](s32)
+ ; CI-MESA: $vgpr0 = COPY [[OR2]](s32)
; VI-LABEL: name: test_load_global_v3s8_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
@@ -4919,8 +4571,7 @@ body: |
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[OR2]](s32)
; GFX9-HSA-LABEL: name: test_load_global_v3s8_align1
; GFX9-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), align 1, addrspace 1)
@@ -4954,8 +4605,7 @@ body: |
; GFX9-HSA: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; GFX9-HSA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX9-HSA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL3]]
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
- ; GFX9-HSA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-HSA: $vgpr0 = COPY [[OR3]](s32)
; GFX9-MESA-LABEL: name: test_load_global_v3s8_align1
; GFX9-MESA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-MESA: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
@@ -4985,8 +4635,7 @@ body: |
; GFX9-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9-MESA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-MESA: $vgpr0 = COPY [[OR2]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(<3 x s8>) = G_LOAD %0 :: (load (<3 x s8>), align 1, addrspace 1)
%2:_(s24) = G_BITCAST %1
@@ -5009,11 +4658,7 @@ body: |
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; SI: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; SI: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
; CI-HSA-LABEL: name: test_load_global_v4s8_align4
@@ -5025,11 +4670,7 @@ body: |
; CI-HSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; CI-HSA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-HSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-HSA: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; CI-HSA: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; CI-HSA: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; CI-HSA: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
; CI-MESA-LABEL: name: test_load_global_v4s8_align4
@@ -5041,11 +4682,7 @@ body: |
; CI-MESA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; CI-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-MESA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; CI-MESA: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; CI-MESA: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
; VI-LABEL: name: test_load_global_v4s8_align4
@@ -5057,11 +4694,7 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; VI: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; VI: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
; GFX9-HSA-LABEL: name: test_load_global_v4s8_align4
@@ -5073,12 +4706,8 @@ body: |
; GFX9-HSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX9-HSA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9-HSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LSHR]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR1]](s32), [[LSHR2]](s32)
; GFX9-HSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-HSA: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<4 x s16>)
; GFX9-HSA: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
@@ -5091,12 +4720,8 @@ body: |
; GFX9-MESA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX9-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9-MESA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LSHR]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR1]](s32), [[LSHR2]](s32)
; GFX9-MESA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-MESA: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<4 x s16>)
; GFX9-MESA: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
@@ -5145,11 +4770,7 @@ body: |
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C1]](s32)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C2]](s32)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C3]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LOAD1]](s32), [[LSHR3]](s32)
; SI: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; SI: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
; CI-HSA-LABEL: name: test_load_global_v4s8_align2
@@ -5161,11 +4782,7 @@ body: |
; CI-HSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; CI-HSA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-HSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-HSA: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; CI-HSA: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; CI-HSA: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; CI-HSA: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
; CI-MESA-LABEL: name: test_load_global_v4s8_align2
@@ -5183,11 +4800,7 @@ body: |
; CI-MESA: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C1]](s32)
; CI-MESA: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C2]](s32)
; CI-MESA: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C3]](s32)
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LOAD1]](s32), [[LSHR3]](s32)
; CI-MESA: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; CI-MESA: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
; VI-LABEL: name: test_load_global_v4s8_align2
@@ -5205,11 +4818,7 @@ body: |
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C1]](s32)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C2]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C3]](s32)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LOAD1]](s32), [[LSHR3]](s32)
; VI: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; VI: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
; GFX9-HSA-LABEL: name: test_load_global_v4s8_align2
@@ -5221,12 +4830,8 @@ body: |
; GFX9-HSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX9-HSA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9-HSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LSHR]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR1]](s32), [[LSHR2]](s32)
; GFX9-HSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-HSA: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<4 x s16>)
; GFX9-HSA: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
@@ -5245,12 +4850,8 @@ body: |
; GFX9-MESA: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C1]](s32)
; GFX9-MESA: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C2]](s32)
; GFX9-MESA: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C3]](s32)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LSHR]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD1]](s32), [[LSHR3]](s32)
; GFX9-MESA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-MESA: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<4 x s16>)
; GFX9-MESA: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
@@ -5277,11 +4878,7 @@ body: |
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; SI: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; SI: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
; CI-HSA-LABEL: name: test_load_global_v4s8_align1
@@ -5293,11 +4890,7 @@ body: |
; CI-HSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; CI-HSA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-HSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-HSA: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; CI-HSA: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32)
; CI-HSA: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; CI-HSA: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
; CI-MESA-LABEL: name: test_load_global_v4s8_align1
@@ -5312,11 +4905,7 @@ body: |
; CI-MESA: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; CI-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CI-MESA: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; CI-MESA: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
; VI-LABEL: name: test_load_global_v4s8_align1
@@ -5331,11 +4920,7 @@ body: |
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32)
+ ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; VI: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[BUILD_VECTOR]](<4 x s32>)
; VI: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
; GFX9-HSA-LABEL: name: test_load_global_v4s8_align1
@@ -5347,12 +4932,8 @@ body: |
; GFX9-HSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX9-HSA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9-HSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LSHR]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR1]](s32), [[LSHR2]](s32)
; GFX9-HSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-HSA: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<4 x s16>)
; GFX9-HSA: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
@@ -5368,12 +4949,8 @@ body: |
; GFX9-MESA: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; GFX9-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
; GFX9-MESA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-MESA: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<4 x s16>)
; GFX9-MESA: $vgpr0 = COPY [[TRUNC]](<4 x s8>)
@@ -5402,32 +4979,24 @@ body: |
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -5446,32 +5015,24 @@ body: |
; CI-HSA: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; CI-HSA: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; CI-HSA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CI-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CI-HSA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CI-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; CI-HSA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI-HSA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-HSA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; CI-HSA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; CI-HSA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-HSA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CI-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; CI-HSA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI-HSA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI-HSA: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -5490,32 +5051,24 @@ body: |
; CI-MESA: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; CI-MESA: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; CI-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; CI-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; CI-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -5534,32 +5087,24 @@ body: |
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -5578,32 +5123,24 @@ body: |
; GFX9-HSA: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; GFX9-HSA: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; GFX9-HSA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX9-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; GFX9-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX9-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX9-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX9-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX9-HSA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX9-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; GFX9-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX9-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; GFX9-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; GFX9-HSA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX9-HSA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9-HSA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; GFX9-HSA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; GFX9-HSA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9-HSA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; GFX9-HSA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX9-HSA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9-HSA: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -5622,32 +5159,24 @@ body: |
; GFX9-MESA: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; GFX9-MESA: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; GFX9-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX9-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX9-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; GFX9-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX9-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; GFX9-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; GFX9-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; GFX9-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX9-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -5684,60 +5213,44 @@ body: |
; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C]](s32)
; SI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C3]]
; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C1]](s32)
; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C3]]
; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C2]](s32)
; SI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -5762,60 +5275,44 @@ body: |
; CI-HSA: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; CI-HSA: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
; CI-HSA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CI-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CI-HSA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CI-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; CI-HSA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI-HSA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-HSA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; CI-HSA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; CI-HSA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-HSA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CI-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; CI-HSA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI-HSA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; CI-HSA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CI-HSA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI-HSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CI-HSA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI-HSA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C3]]
+ ; CI-HSA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
; CI-HSA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; CI-HSA: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI-HSA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CI-HSA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI-HSA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C3]]
; CI-HSA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s32)
; CI-HSA: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI-HSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; CI-HSA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI-HSA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C3]]
; CI-HSA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; CI-HSA: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; CI-HSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CI-HSA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI-HSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; CI-HSA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI-HSA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
+ ; CI-HSA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
; CI-HSA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C]](s32)
; CI-HSA: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI-HSA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; CI-HSA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI-HSA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C3]]
; CI-HSA: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C1]](s32)
; CI-HSA: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI-HSA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; CI-HSA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI-HSA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C3]]
; CI-HSA: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C2]](s32)
; CI-HSA: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI-HSA: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -5840,60 +5337,44 @@ body: |
; CI-MESA: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; CI-MESA: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; CI-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; CI-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; CI-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; CI-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CI-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C3]]
+ ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
; CI-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; CI-MESA: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CI-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C3]]
; CI-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s32)
; CI-MESA: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C3]]
; CI-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; CI-MESA: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; CI-MESA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CI-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI-MESA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; CI-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
+ ; CI-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
; CI-MESA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C]](s32)
; CI-MESA: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI-MESA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; CI-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C3]]
; CI-MESA: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C1]](s32)
; CI-MESA: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI-MESA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; CI-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C3]]
; CI-MESA: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C2]](s32)
; CI-MESA: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -5918,60 +5399,44 @@ body: |
; VI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; VI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C1]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C2]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -5996,60 +5461,44 @@ body: |
; GFX9-HSA: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; GFX9-HSA: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
; GFX9-HSA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX9-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; GFX9-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX9-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX9-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX9-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX9-HSA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX9-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; GFX9-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX9-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; GFX9-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; GFX9-HSA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX9-HSA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9-HSA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; GFX9-HSA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; GFX9-HSA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9-HSA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; GFX9-HSA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX9-HSA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; GFX9-HSA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; GFX9-HSA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9-HSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9-HSA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9-HSA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C3]]
+ ; GFX9-HSA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
; GFX9-HSA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; GFX9-HSA: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9-HSA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX9-HSA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9-HSA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C3]]
; GFX9-HSA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s32)
; GFX9-HSA: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9-HSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; GFX9-HSA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9-HSA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C3]]
; GFX9-HSA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; GFX9-HSA: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; GFX9-HSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; GFX9-HSA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9-HSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; GFX9-HSA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9-HSA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
+ ; GFX9-HSA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
; GFX9-HSA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C]](s32)
; GFX9-HSA: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9-HSA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; GFX9-HSA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9-HSA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C3]]
; GFX9-HSA: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C1]](s32)
; GFX9-HSA: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9-HSA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; GFX9-HSA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9-HSA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C3]]
; GFX9-HSA: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C2]](s32)
; GFX9-HSA: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9-HSA: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -6074,60 +5523,44 @@ body: |
; GFX9-MESA: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; GFX9-MESA: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
; GFX9-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX9-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX9-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; GFX9-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX9-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; GFX9-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; GFX9-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; GFX9-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX9-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; GFX9-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; GFX9-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C3]]
+ ; GFX9-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
; GFX9-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; GFX9-MESA: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX9-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C3]]
; GFX9-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s32)
; GFX9-MESA: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; GFX9-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C3]]
; GFX9-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; GFX9-MESA: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; GFX9-MESA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; GFX9-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9-MESA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; GFX9-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
+ ; GFX9-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
; GFX9-MESA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C]](s32)
; GFX9-MESA: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9-MESA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; GFX9-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C3]]
; GFX9-MESA: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C1]](s32)
; GFX9-MESA: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9-MESA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; GFX9-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C3]]
; GFX9-MESA: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C2]](s32)
; GFX9-MESA: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -6176,116 +5609,84 @@ body: |
; SI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C1]](s32)
; SI: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C2]](s32)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C]](s32)
; SI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C3]]
; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C1]](s32)
; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C3]]
; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C2]](s32)
; SI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; SI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; SI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; SI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[C3]]
+ ; SI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C3]]
; SI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C]](s32)
; SI: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; SI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; SI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C3]]
; SI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C1]](s32)
; SI: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; SI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; SI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C3]]
; SI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C2]](s32)
; SI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
- ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; SI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; SI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; SI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; SI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C3]]
+ ; SI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C3]]
; SI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C]](s32)
; SI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; SI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; SI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; SI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR16]], [[C3]]
; SI: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C1]](s32)
; SI: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; SI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; SI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; SI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR17]], [[C3]]
; SI: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C2]](s32)
; SI: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
- ; SI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; SI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C3]]
- ; SI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; SI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C3]]
+ ; SI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[UV6]], [[C3]]
+ ; SI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LSHR18]], [[C3]]
; SI: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[C]](s32)
; SI: [[OR18:%[0-9]+]]:_(s32) = G_OR [[AND24]], [[SHL18]]
- ; SI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; SI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C3]]
+ ; SI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[LSHR19]], [[C3]]
; SI: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C1]](s32)
; SI: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
- ; SI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; SI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C3]]
+ ; SI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LSHR20]], [[C3]]
; SI: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[C2]](s32)
; SI: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
- ; SI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; SI: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C3]]
- ; SI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; SI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C3]]
+ ; SI: [[AND28:%[0-9]+]]:_(s32) = G_AND [[UV7]], [[C3]]
+ ; SI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LSHR21]], [[C3]]
; SI: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[C]](s32)
; SI: [[OR21:%[0-9]+]]:_(s32) = G_OR [[AND28]], [[SHL21]]
- ; SI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; SI: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C3]]
+ ; SI: [[AND30:%[0-9]+]]:_(s32) = G_AND [[LSHR22]], [[C3]]
; SI: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[C1]](s32)
; SI: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
- ; SI: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; SI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C3]]
+ ; SI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LSHR23]], [[C3]]
; SI: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C2]](s32)
; SI: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32), [[OR14]](s32), [[OR17]](s32), [[OR20]](s32), [[OR23]](s32)
@@ -6322,116 +5723,84 @@ body: |
; CI-HSA: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C1]](s32)
; CI-HSA: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C2]](s32)
; CI-HSA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CI-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CI-HSA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CI-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; CI-HSA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI-HSA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-HSA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; CI-HSA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; CI-HSA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-HSA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CI-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; CI-HSA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI-HSA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; CI-HSA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CI-HSA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI-HSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CI-HSA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI-HSA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C3]]
+ ; CI-HSA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
; CI-HSA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; CI-HSA: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI-HSA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CI-HSA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI-HSA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C3]]
; CI-HSA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s32)
; CI-HSA: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI-HSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; CI-HSA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI-HSA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C3]]
; CI-HSA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; CI-HSA: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; CI-HSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CI-HSA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI-HSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; CI-HSA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI-HSA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
+ ; CI-HSA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
; CI-HSA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C]](s32)
; CI-HSA: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI-HSA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; CI-HSA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI-HSA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C3]]
; CI-HSA: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C1]](s32)
; CI-HSA: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI-HSA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; CI-HSA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI-HSA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C3]]
; CI-HSA: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C2]](s32)
; CI-HSA: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
- ; CI-HSA: [[COPY17:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; CI-HSA: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; CI-HSA: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; CI-HSA: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; CI-HSA: [[AND16:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[C3]]
+ ; CI-HSA: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C3]]
; CI-HSA: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C]](s32)
; CI-HSA: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; CI-HSA: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; CI-HSA: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; CI-HSA: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C3]]
; CI-HSA: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C1]](s32)
; CI-HSA: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; CI-HSA: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; CI-HSA: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; CI-HSA: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C3]]
; CI-HSA: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C2]](s32)
; CI-HSA: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
- ; CI-HSA: [[COPY21:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; CI-HSA: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; CI-HSA: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; CI-HSA: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; CI-HSA: [[AND20:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C3]]
+ ; CI-HSA: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C3]]
; CI-HSA: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C]](s32)
; CI-HSA: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; CI-HSA: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; CI-HSA: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; CI-HSA: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR16]], [[C3]]
; CI-HSA: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C1]](s32)
; CI-HSA: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; CI-HSA: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; CI-HSA: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; CI-HSA: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR17]], [[C3]]
; CI-HSA: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C2]](s32)
; CI-HSA: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
- ; CI-HSA: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; CI-HSA: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C3]]
- ; CI-HSA: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; CI-HSA: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C3]]
+ ; CI-HSA: [[AND24:%[0-9]+]]:_(s32) = G_AND [[UV6]], [[C3]]
+ ; CI-HSA: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LSHR18]], [[C3]]
; CI-HSA: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[C]](s32)
; CI-HSA: [[OR18:%[0-9]+]]:_(s32) = G_OR [[AND24]], [[SHL18]]
- ; CI-HSA: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; CI-HSA: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C3]]
+ ; CI-HSA: [[AND26:%[0-9]+]]:_(s32) = G_AND [[LSHR19]], [[C3]]
; CI-HSA: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C1]](s32)
; CI-HSA: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
- ; CI-HSA: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; CI-HSA: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C3]]
+ ; CI-HSA: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LSHR20]], [[C3]]
; CI-HSA: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[C2]](s32)
; CI-HSA: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
- ; CI-HSA: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; CI-HSA: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C3]]
- ; CI-HSA: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; CI-HSA: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C3]]
+ ; CI-HSA: [[AND28:%[0-9]+]]:_(s32) = G_AND [[UV7]], [[C3]]
+ ; CI-HSA: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LSHR21]], [[C3]]
; CI-HSA: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[C]](s32)
; CI-HSA: [[OR21:%[0-9]+]]:_(s32) = G_OR [[AND28]], [[SHL21]]
- ; CI-HSA: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; CI-HSA: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C3]]
+ ; CI-HSA: [[AND30:%[0-9]+]]:_(s32) = G_AND [[LSHR22]], [[C3]]
; CI-HSA: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[C1]](s32)
; CI-HSA: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
- ; CI-HSA: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; CI-HSA: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C3]]
+ ; CI-HSA: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LSHR23]], [[C3]]
; CI-HSA: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C2]](s32)
; CI-HSA: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
; CI-HSA: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32), [[OR14]](s32), [[OR17]](s32), [[OR20]](s32), [[OR23]](s32)
@@ -6468,116 +5837,84 @@ body: |
; CI-MESA: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C1]](s32)
; CI-MESA: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C2]](s32)
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; CI-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; CI-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; CI-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; CI-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CI-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C3]]
+ ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
; CI-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; CI-MESA: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CI-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C3]]
; CI-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s32)
; CI-MESA: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C3]]
; CI-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; CI-MESA: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; CI-MESA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CI-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI-MESA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; CI-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
+ ; CI-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
; CI-MESA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C]](s32)
; CI-MESA: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI-MESA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; CI-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C3]]
; CI-MESA: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C1]](s32)
; CI-MESA: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI-MESA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; CI-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C3]]
; CI-MESA: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C2]](s32)
; CI-MESA: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
- ; CI-MESA: [[COPY17:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; CI-MESA: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; CI-MESA: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; CI-MESA: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; CI-MESA: [[AND16:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[C3]]
+ ; CI-MESA: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C3]]
; CI-MESA: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C]](s32)
; CI-MESA: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; CI-MESA: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; CI-MESA: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; CI-MESA: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C3]]
; CI-MESA: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C1]](s32)
; CI-MESA: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; CI-MESA: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; CI-MESA: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; CI-MESA: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C3]]
; CI-MESA: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C2]](s32)
; CI-MESA: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
- ; CI-MESA: [[COPY21:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; CI-MESA: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; CI-MESA: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; CI-MESA: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; CI-MESA: [[AND20:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C3]]
+ ; CI-MESA: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C3]]
; CI-MESA: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C]](s32)
; CI-MESA: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; CI-MESA: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; CI-MESA: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; CI-MESA: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR16]], [[C3]]
; CI-MESA: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C1]](s32)
; CI-MESA: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; CI-MESA: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; CI-MESA: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; CI-MESA: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR17]], [[C3]]
; CI-MESA: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C2]](s32)
; CI-MESA: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
- ; CI-MESA: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; CI-MESA: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C3]]
- ; CI-MESA: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; CI-MESA: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C3]]
+ ; CI-MESA: [[AND24:%[0-9]+]]:_(s32) = G_AND [[UV6]], [[C3]]
+ ; CI-MESA: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LSHR18]], [[C3]]
; CI-MESA: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[C]](s32)
; CI-MESA: [[OR18:%[0-9]+]]:_(s32) = G_OR [[AND24]], [[SHL18]]
- ; CI-MESA: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; CI-MESA: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C3]]
+ ; CI-MESA: [[AND26:%[0-9]+]]:_(s32) = G_AND [[LSHR19]], [[C3]]
; CI-MESA: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C1]](s32)
; CI-MESA: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
- ; CI-MESA: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; CI-MESA: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C3]]
+ ; CI-MESA: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LSHR20]], [[C3]]
; CI-MESA: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[C2]](s32)
; CI-MESA: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
- ; CI-MESA: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; CI-MESA: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C3]]
- ; CI-MESA: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; CI-MESA: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C3]]
+ ; CI-MESA: [[AND28:%[0-9]+]]:_(s32) = G_AND [[UV7]], [[C3]]
+ ; CI-MESA: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LSHR21]], [[C3]]
; CI-MESA: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[C]](s32)
; CI-MESA: [[OR21:%[0-9]+]]:_(s32) = G_OR [[AND28]], [[SHL21]]
- ; CI-MESA: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; CI-MESA: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C3]]
+ ; CI-MESA: [[AND30:%[0-9]+]]:_(s32) = G_AND [[LSHR22]], [[C3]]
; CI-MESA: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[C1]](s32)
; CI-MESA: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
- ; CI-MESA: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; CI-MESA: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C3]]
+ ; CI-MESA: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LSHR23]], [[C3]]
; CI-MESA: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C2]](s32)
; CI-MESA: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32), [[OR14]](s32), [[OR17]](s32), [[OR20]](s32), [[OR23]](s32)
@@ -6614,116 +5951,84 @@ body: |
; VI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C1]](s32)
; VI: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C2]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C1]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C2]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; VI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; VI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; VI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; VI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[C3]]
+ ; VI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C3]]
; VI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C]](s32)
; VI: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; VI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; VI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; VI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C3]]
; VI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C1]](s32)
; VI: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; VI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; VI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; VI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C3]]
; VI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C2]](s32)
; VI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
- ; VI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; VI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; VI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; VI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; VI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C3]]
+ ; VI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C3]]
; VI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C]](s32)
; VI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; VI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; VI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; VI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR16]], [[C3]]
; VI: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C1]](s32)
; VI: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; VI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; VI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; VI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR17]], [[C3]]
; VI: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C2]](s32)
; VI: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
- ; VI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; VI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C3]]
- ; VI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; VI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C3]]
+ ; VI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[UV6]], [[C3]]
+ ; VI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LSHR18]], [[C3]]
; VI: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[C]](s32)
; VI: [[OR18:%[0-9]+]]:_(s32) = G_OR [[AND24]], [[SHL18]]
- ; VI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; VI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C3]]
+ ; VI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[LSHR19]], [[C3]]
; VI: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C1]](s32)
; VI: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
- ; VI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; VI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C3]]
+ ; VI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LSHR20]], [[C3]]
; VI: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[C2]](s32)
; VI: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
- ; VI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; VI: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C3]]
- ; VI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; VI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C3]]
+ ; VI: [[AND28:%[0-9]+]]:_(s32) = G_AND [[UV7]], [[C3]]
+ ; VI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LSHR21]], [[C3]]
; VI: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[C]](s32)
; VI: [[OR21:%[0-9]+]]:_(s32) = G_OR [[AND28]], [[SHL21]]
- ; VI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; VI: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C3]]
+ ; VI: [[AND30:%[0-9]+]]:_(s32) = G_AND [[LSHR22]], [[C3]]
; VI: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[C1]](s32)
; VI: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
- ; VI: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; VI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C3]]
+ ; VI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LSHR23]], [[C3]]
; VI: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C2]](s32)
; VI: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32), [[OR14]](s32), [[OR17]](s32), [[OR20]](s32), [[OR23]](s32)
@@ -6760,116 +6065,84 @@ body: |
; GFX9-HSA: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C1]](s32)
; GFX9-HSA: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C2]](s32)
; GFX9-HSA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX9-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; GFX9-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX9-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX9-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX9-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX9-HSA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX9-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; GFX9-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX9-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; GFX9-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; GFX9-HSA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX9-HSA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9-HSA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; GFX9-HSA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; GFX9-HSA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9-HSA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; GFX9-HSA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX9-HSA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; GFX9-HSA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; GFX9-HSA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9-HSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9-HSA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9-HSA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C3]]
+ ; GFX9-HSA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
; GFX9-HSA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; GFX9-HSA: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9-HSA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX9-HSA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9-HSA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C3]]
; GFX9-HSA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s32)
; GFX9-HSA: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9-HSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; GFX9-HSA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9-HSA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C3]]
; GFX9-HSA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; GFX9-HSA: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; GFX9-HSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; GFX9-HSA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9-HSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; GFX9-HSA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9-HSA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
+ ; GFX9-HSA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
; GFX9-HSA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C]](s32)
; GFX9-HSA: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9-HSA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; GFX9-HSA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9-HSA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C3]]
; GFX9-HSA: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C1]](s32)
; GFX9-HSA: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9-HSA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; GFX9-HSA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9-HSA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C3]]
; GFX9-HSA: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C2]](s32)
; GFX9-HSA: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
- ; GFX9-HSA: [[COPY17:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; GFX9-HSA: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; GFX9-HSA: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; GFX9-HSA: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; GFX9-HSA: [[AND16:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[C3]]
+ ; GFX9-HSA: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C3]]
; GFX9-HSA: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C]](s32)
; GFX9-HSA: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; GFX9-HSA: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; GFX9-HSA: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; GFX9-HSA: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C3]]
; GFX9-HSA: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C1]](s32)
; GFX9-HSA: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; GFX9-HSA: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; GFX9-HSA: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; GFX9-HSA: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C3]]
; GFX9-HSA: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C2]](s32)
; GFX9-HSA: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
- ; GFX9-HSA: [[COPY21:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; GFX9-HSA: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; GFX9-HSA: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; GFX9-HSA: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; GFX9-HSA: [[AND20:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C3]]
+ ; GFX9-HSA: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C3]]
; GFX9-HSA: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C]](s32)
; GFX9-HSA: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; GFX9-HSA: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; GFX9-HSA: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; GFX9-HSA: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR16]], [[C3]]
; GFX9-HSA: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C1]](s32)
; GFX9-HSA: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; GFX9-HSA: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; GFX9-HSA: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; GFX9-HSA: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR17]], [[C3]]
; GFX9-HSA: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C2]](s32)
; GFX9-HSA: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
- ; GFX9-HSA: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; GFX9-HSA: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C3]]
- ; GFX9-HSA: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; GFX9-HSA: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C3]]
+ ; GFX9-HSA: [[AND24:%[0-9]+]]:_(s32) = G_AND [[UV6]], [[C3]]
+ ; GFX9-HSA: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LSHR18]], [[C3]]
; GFX9-HSA: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[C]](s32)
; GFX9-HSA: [[OR18:%[0-9]+]]:_(s32) = G_OR [[AND24]], [[SHL18]]
- ; GFX9-HSA: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; GFX9-HSA: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C3]]
+ ; GFX9-HSA: [[AND26:%[0-9]+]]:_(s32) = G_AND [[LSHR19]], [[C3]]
; GFX9-HSA: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C1]](s32)
; GFX9-HSA: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
- ; GFX9-HSA: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; GFX9-HSA: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C3]]
+ ; GFX9-HSA: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LSHR20]], [[C3]]
; GFX9-HSA: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[C2]](s32)
; GFX9-HSA: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
- ; GFX9-HSA: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; GFX9-HSA: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C3]]
- ; GFX9-HSA: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; GFX9-HSA: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C3]]
+ ; GFX9-HSA: [[AND28:%[0-9]+]]:_(s32) = G_AND [[UV7]], [[C3]]
+ ; GFX9-HSA: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LSHR21]], [[C3]]
; GFX9-HSA: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[C]](s32)
; GFX9-HSA: [[OR21:%[0-9]+]]:_(s32) = G_OR [[AND28]], [[SHL21]]
- ; GFX9-HSA: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; GFX9-HSA: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C3]]
+ ; GFX9-HSA: [[AND30:%[0-9]+]]:_(s32) = G_AND [[LSHR22]], [[C3]]
; GFX9-HSA: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[C1]](s32)
; GFX9-HSA: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
- ; GFX9-HSA: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; GFX9-HSA: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C3]]
+ ; GFX9-HSA: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LSHR23]], [[C3]]
; GFX9-HSA: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C2]](s32)
; GFX9-HSA: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
; GFX9-HSA: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32), [[OR14]](s32), [[OR17]](s32), [[OR20]](s32), [[OR23]](s32)
@@ -6906,116 +6179,84 @@ body: |
; GFX9-MESA: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C1]](s32)
; GFX9-MESA: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C2]](s32)
; GFX9-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX9-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX9-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; GFX9-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX9-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; GFX9-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; GFX9-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; GFX9-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX9-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; GFX9-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; GFX9-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C3]]
+ ; GFX9-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
; GFX9-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; GFX9-MESA: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX9-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C3]]
; GFX9-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s32)
; GFX9-MESA: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; GFX9-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C3]]
; GFX9-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; GFX9-MESA: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; GFX9-MESA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; GFX9-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9-MESA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; GFX9-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
+ ; GFX9-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
; GFX9-MESA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C]](s32)
; GFX9-MESA: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9-MESA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; GFX9-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C3]]
; GFX9-MESA: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C1]](s32)
; GFX9-MESA: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9-MESA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; GFX9-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C3]]
; GFX9-MESA: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C2]](s32)
; GFX9-MESA: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
- ; GFX9-MESA: [[COPY17:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; GFX9-MESA: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; GFX9-MESA: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; GFX9-MESA: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; GFX9-MESA: [[AND16:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[C3]]
+ ; GFX9-MESA: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LSHR12]], [[C3]]
; GFX9-MESA: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C]](s32)
; GFX9-MESA: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; GFX9-MESA: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; GFX9-MESA: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; GFX9-MESA: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C3]]
; GFX9-MESA: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C1]](s32)
; GFX9-MESA: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; GFX9-MESA: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; GFX9-MESA: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; GFX9-MESA: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR14]], [[C3]]
; GFX9-MESA: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C2]](s32)
; GFX9-MESA: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
- ; GFX9-MESA: [[COPY21:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; GFX9-MESA: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; GFX9-MESA: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; GFX9-MESA: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; GFX9-MESA: [[AND20:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C3]]
+ ; GFX9-MESA: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C3]]
; GFX9-MESA: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C]](s32)
; GFX9-MESA: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; GFX9-MESA: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; GFX9-MESA: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; GFX9-MESA: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR16]], [[C3]]
; GFX9-MESA: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C1]](s32)
; GFX9-MESA: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; GFX9-MESA: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; GFX9-MESA: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; GFX9-MESA: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LSHR17]], [[C3]]
; GFX9-MESA: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C2]](s32)
; GFX9-MESA: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
- ; GFX9-MESA: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; GFX9-MESA: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C3]]
- ; GFX9-MESA: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; GFX9-MESA: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C3]]
+ ; GFX9-MESA: [[AND24:%[0-9]+]]:_(s32) = G_AND [[UV6]], [[C3]]
+ ; GFX9-MESA: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LSHR18]], [[C3]]
; GFX9-MESA: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[C]](s32)
; GFX9-MESA: [[OR18:%[0-9]+]]:_(s32) = G_OR [[AND24]], [[SHL18]]
- ; GFX9-MESA: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; GFX9-MESA: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C3]]
+ ; GFX9-MESA: [[AND26:%[0-9]+]]:_(s32) = G_AND [[LSHR19]], [[C3]]
; GFX9-MESA: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C1]](s32)
; GFX9-MESA: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
- ; GFX9-MESA: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; GFX9-MESA: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C3]]
+ ; GFX9-MESA: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LSHR20]], [[C3]]
; GFX9-MESA: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[C2]](s32)
; GFX9-MESA: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
- ; GFX9-MESA: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; GFX9-MESA: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C3]]
- ; GFX9-MESA: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; GFX9-MESA: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C3]]
+ ; GFX9-MESA: [[AND28:%[0-9]+]]:_(s32) = G_AND [[UV7]], [[C3]]
+ ; GFX9-MESA: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LSHR21]], [[C3]]
; GFX9-MESA: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[C]](s32)
; GFX9-MESA: [[OR21:%[0-9]+]]:_(s32) = G_OR [[AND28]], [[SHL21]]
- ; GFX9-MESA: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; GFX9-MESA: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C3]]
+ ; GFX9-MESA: [[AND30:%[0-9]+]]:_(s32) = G_AND [[LSHR22]], [[C3]]
; GFX9-MESA: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[C1]](s32)
; GFX9-MESA: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
- ; GFX9-MESA: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; GFX9-MESA: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C3]]
+ ; GFX9-MESA: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LSHR23]], [[C3]]
; GFX9-MESA: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C2]](s32)
; GFX9-MESA: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
; GFX9-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32), [[OR14]](s32), [[OR17]](s32), [[OR20]](s32), [[OR23]](s32)
@@ -7075,10 +6316,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -7095,10 +6334,8 @@ body: |
; CI-MESA: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-MESA: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; CI-MESA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -7111,10 +6348,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -7130,9 +6365,7 @@ body: |
; GFX9-MESA: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; GFX9-MESA: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; GFX9-MESA: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
; GFX9-MESA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(<2 x s16>) = G_LOAD %0 :: (load (<2 x s16>), align 2, addrspace 1)
@@ -7193,8 +6426,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -7205,10 +6437,9 @@ body: |
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -7233,8 +6464,7 @@ body: |
; CI-MESA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -7245,10 +6475,9 @@ body: |
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; CI-MESA: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-MESA: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; CI-MESA: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-MESA: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -7351,24 +6580,18 @@ body: |
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -7391,24 +6614,18 @@ body: |
; CI-HSA: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; CI-HSA: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CI-HSA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-HSA: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; CI-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CI-HSA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-HSA: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; CI-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-HSA: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -7431,24 +6648,18 @@ body: |
; CI-MESA: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; CI-MESA: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CI-MESA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-MESA: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-MESA: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -7471,24 +6682,18 @@ body: |
; VI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -7510,15 +6715,9 @@ body: |
; GFX9-HSA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9-HSA: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX9-HSA: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[BITCAST2]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[BITCAST3]](s32)
; GFX9-HSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9-HSA: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; GFX9-MESA-LABEL: name: test_load_global_v3s16_align8
@@ -7537,15 +6736,9 @@ body: |
; GFX9-MESA: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9-MESA: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX9-MESA: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[BITCAST2]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[BITCAST3]](s32)
; GFX9-MESA: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9-MESA: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(p1) = COPY $vgpr0_vgpr1
@@ -7587,24 +6780,18 @@ body: |
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -7630,24 +6817,18 @@ body: |
; CI-HSA: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CI-HSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; CI-HSA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-HSA: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; CI-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-HSA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-HSA: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; CI-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-HSA: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -7673,24 +6854,18 @@ body: |
; CI-MESA: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CI-MESA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-MESA: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-MESA: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -7716,24 +6891,18 @@ body: |
; VI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -7758,15 +6927,9 @@ body: |
; GFX9-HSA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C2]](s32)
; GFX9-HSA: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9-HSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[BITCAST]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9-HSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9-HSA: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; GFX9-MESA-LABEL: name: test_load_global_v3s16_align4
@@ -7788,15 +6951,9 @@ body: |
; GFX9-MESA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C2]](s32)
; GFX9-MESA: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9-MESA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[BITCAST]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9-MESA: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9-MESA: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(p1) = COPY $vgpr0_vgpr1
@@ -7832,24 +6989,18 @@ body: |
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -7875,24 +7026,18 @@ body: |
; CI-HSA: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CI-HSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; CI-HSA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-HSA: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; CI-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-HSA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-HSA: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; CI-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-HSA: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -7918,24 +7063,18 @@ body: |
; CI-MESA: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CI-MESA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-MESA: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-MESA: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -7961,24 +7100,18 @@ body: |
; VI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -8003,15 +7136,9 @@ body: |
; GFX9-HSA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C2]](s32)
; GFX9-HSA: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9-HSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[BITCAST]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9-HSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9-HSA: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; GFX9-MESA-LABEL: name: test_load_global_v3s16_align2
@@ -8033,15 +7160,9 @@ body: |
; GFX9-MESA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C2]](s32)
; GFX9-MESA: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9-MESA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[BITCAST]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9-MESA: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9-MESA: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(p1) = COPY $vgpr0_vgpr1
@@ -8068,8 +7189,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -8080,10 +7200,9 @@ body: |
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
@@ -8093,10 +7212,9 @@ body: |
; SI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p1) :: (load (s8) from unknown-address + 5, addrspace 1)
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; SI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; SI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
@@ -8116,15 +7234,12 @@ body: |
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C7]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C6]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; SI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C7]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C7]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL5]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
@@ -8150,24 +7265,18 @@ body: |
; CI-HSA: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CI-HSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; CI-HSA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-HSA: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; CI-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-HSA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-HSA: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; CI-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-HSA: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -8184,8 +7293,7 @@ body: |
; CI-MESA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -8196,10 +7304,9 @@ body: |
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; CI-MESA: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-MESA: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; CI-MESA: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-MESA: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
@@ -8209,10 +7316,9 @@ body: |
; CI-MESA: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p1) :: (load (s8) from unknown-address + 5, addrspace 1)
; CI-MESA: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI-MESA: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; CI-MESA: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI-MESA: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
@@ -8232,15 +7338,12 @@ body: |
; CI-MESA: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; CI-MESA: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; CI-MESA: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
+ ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C7]]
; CI-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C6]](s32)
; CI-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; CI-MESA: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C7]]
+ ; CI-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C7]]
; CI-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C6]](s32)
; CI-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL5]]
; CI-MESA: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
@@ -8299,15 +7402,12 @@ body: |
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C6]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C6]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C6]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C6]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C5]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL5]]
; VI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
@@ -8332,15 +7432,9 @@ body: |
; GFX9-HSA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C2]](s32)
; GFX9-HSA: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9-HSA: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[BITCAST]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9-HSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9-HSA: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; GFX9-MESA-LABEL: name: test_load_global_v3s16_align1
@@ -8393,11 +7487,8 @@ body: |
; GFX9-MESA: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[OR1]](s16)
; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX9-MESA: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[OR2]](s16)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[COPY1]](s32)
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[BITCAST]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9-MESA: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9-MESA: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(p1) = COPY $vgpr0_vgpr1
@@ -8496,18 +7587,14 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -8530,18 +7617,14 @@ body: |
; CI-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-MESA: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -8560,18 +7643,14 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -8593,12 +7672,8 @@ body: |
; GFX9-MESA: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; GFX9-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
; GFX9-MESA: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-MESA: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
%0:_(p1) = COPY $vgpr0_vgpr1
@@ -8623,8 +7698,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -8635,10 +7709,9 @@ body: |
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -8654,10 +7727,9 @@ body: |
; SI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p1) :: (load (s8) from unknown-address + 5, addrspace 1)
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; SI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; SI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
@@ -8666,10 +7738,9 @@ body: |
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; SI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY6]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
+ ; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY3]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; SI: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
@@ -8694,8 +7765,7 @@ body: |
; CI-MESA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -8706,10 +7776,9 @@ body: |
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; CI-MESA: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-MESA: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; CI-MESA: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-MESA: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -8725,10 +7794,9 @@ body: |
; CI-MESA: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p1) :: (load (s8) from unknown-address + 5, addrspace 1)
; CI-MESA: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI-MESA: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; CI-MESA: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI-MESA: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
@@ -8737,10 +7805,9 @@ body: |
; CI-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
; CI-MESA: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI-MESA: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C1]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; CI-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY6]](s32)
+ ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
+ ; CI-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY3]](s32)
; CI-MESA: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; CI-MESA: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
; CI-MESA: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
@@ -8897,24 +7964,18 @@ body: |
; SI: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -8940,24 +8001,18 @@ body: |
; CI-HSA: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; CI-HSA: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; CI-HSA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-HSA: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; CI-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CI-HSA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-HSA: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; CI-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-HSA: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -8983,24 +8038,18 @@ body: |
; CI-MESA: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; CI-MESA: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; CI-MESA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-MESA: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-MESA: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -9026,24 +8075,18 @@ body: |
; VI: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -9068,15 +8111,9 @@ body: |
; GFX9-HSA: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>), [[UV6:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF1]](<6 x s16>)
; GFX9-HSA: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; GFX9-HSA: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[LSHR]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST2]](s32), [[LSHR1]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST3]](s32), [[BITCAST4]](s32)
; GFX9-HSA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9-HSA: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-HSA: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
@@ -9098,15 +8135,9 @@ body: |
; GFX9-MESA: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>), [[UV6:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF1]](<6 x s16>)
; GFX9-MESA: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; GFX9-MESA: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[LSHR]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST2]](s32), [[LSHR1]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST3]](s32), [[BITCAST4]](s32)
; GFX9-MESA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9-MESA: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-MESA: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
@@ -9147,24 +8178,18 @@ body: |
; SI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -9195,24 +8220,18 @@ body: |
; CI-HSA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-HSA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C4]](s32)
; CI-HSA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C5]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C5]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-HSA: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C5]]
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
+ ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C5]]
+ ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C5]]
; CI-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-HSA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-HSA: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
- ; CI-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C5]]
+ ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C5]]
+ ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C5]]
; CI-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-HSA: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -9243,24 +8262,18 @@ body: |
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C4]](s32)
; CI-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C5]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C5]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-MESA: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C5]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C5]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C5]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C5]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C5]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C5]]
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-MESA: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -9291,24 +8304,18 @@ body: |
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C4]](s32)
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C5]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C5]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C5]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C5]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C5]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C5]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C5]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C5]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -9338,15 +8345,9 @@ body: |
; GFX9-HSA: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; GFX9-HSA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-HSA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C4]](s32)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD4]](s32), [[BITCAST]](s32)
; GFX9-HSA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9-HSA: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-HSA: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
@@ -9373,15 +8374,9 @@ body: |
; GFX9-MESA: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; GFX9-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C4]](s32)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD4]](s32), [[BITCAST]](s32)
; GFX9-MESA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9-MESA: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-MESA: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
@@ -9422,24 +8417,18 @@ body: |
; SI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -9470,24 +8459,18 @@ body: |
; CI-HSA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-HSA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C4]](s32)
; CI-HSA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C5]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C5]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-HSA: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C5]]
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
+ ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C5]]
+ ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C5]]
; CI-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-HSA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-HSA: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
- ; CI-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C5]]
+ ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C5]]
+ ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C5]]
; CI-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-HSA: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -9518,24 +8501,18 @@ body: |
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C4]](s32)
; CI-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C5]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C5]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-MESA: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C5]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C5]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C5]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C5]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C5]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C5]]
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-MESA: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -9566,24 +8543,18 @@ body: |
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C4]](s32)
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C5]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C5]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C5]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C5]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C5]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C5]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C5]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C5]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -9613,15 +8584,9 @@ body: |
; GFX9-HSA: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; GFX9-HSA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-HSA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C4]](s32)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD4]](s32), [[BITCAST]](s32)
; GFX9-HSA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9-HSA: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-HSA: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
@@ -9648,15 +8613,9 @@ body: |
; GFX9-MESA: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; GFX9-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C4]](s32)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD4]](s32), [[BITCAST]](s32)
; GFX9-MESA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9-MESA: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-MESA: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
@@ -9701,24 +8660,18 @@ body: |
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C4]](s32)
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C5]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C5]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C5]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C5]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C5]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C5]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C5]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C5]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -9749,24 +8702,18 @@ body: |
; CI-HSA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-HSA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C4]](s32)
; CI-HSA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C5]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C5]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-HSA: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C5]]
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
+ ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C5]]
+ ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C5]]
; CI-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-HSA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-HSA: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
- ; CI-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C5]]
+ ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C5]]
+ ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C5]]
; CI-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-HSA: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -9797,24 +8744,18 @@ body: |
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C4]](s32)
; CI-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C5]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C5]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-MESA: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C5]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C5]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C5]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C5]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C5]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C5]]
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-MESA: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -9845,24 +8786,18 @@ body: |
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C4]](s32)
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C5]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C5]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C5]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C5]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C5]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C5]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C5]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C5]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -9892,15 +8827,9 @@ body: |
; GFX9-HSA: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; GFX9-HSA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-HSA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C4]](s32)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD4]](s32), [[BITCAST]](s32)
; GFX9-HSA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9-HSA: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-HSA: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
@@ -9927,15 +8856,9 @@ body: |
; GFX9-MESA: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; GFX9-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C4]](s32)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD4]](s32), [[BITCAST]](s32)
; GFX9-MESA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9-MESA: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-MESA: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
@@ -9967,8 +8890,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -9979,10 +8901,9 @@ body: |
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
@@ -9992,10 +8913,9 @@ body: |
; SI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p1) :: (load (s8) from unknown-address + 5, addrspace 1)
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; SI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
@@ -10004,10 +8924,9 @@ body: |
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; SI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY6]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
+ ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY3]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; SI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -10017,10 +8936,9 @@ body: |
; SI: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p1) :: (load (s8) from unknown-address + 9, addrspace 1)
; SI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD8]](s32)
; SI: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C1]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY8]](s32)
+ ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
+ ; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY4]](s32)
; SI: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; SI: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
; SI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
@@ -10043,8 +8961,7 @@ body: |
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR6]](s32)
; SI: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR4]](s16)
; SI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C8]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C8]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C7]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[ZEXT4]], [[SHL7]]
; SI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR7]](s32)
@@ -10075,24 +8992,18 @@ body: |
; CI-HSA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-HSA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C4]](s32)
; CI-HSA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C5]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C5]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-HSA: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C5]]
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
+ ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C5]]
+ ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C5]]
; CI-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-HSA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-HSA: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
- ; CI-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C5]]
+ ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C5]]
+ ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C5]]
; CI-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-HSA: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -10110,8 +9021,7 @@ body: |
; CI-MESA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -10122,10 +9032,9 @@ body: |
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; CI-MESA: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-MESA: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; CI-MESA: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-MESA: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
@@ -10135,10 +9044,9 @@ body: |
; CI-MESA: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p1) :: (load (s8) from unknown-address + 5, addrspace 1)
; CI-MESA: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI-MESA: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; CI-MESA: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI-MESA: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
@@ -10147,10 +9055,9 @@ body: |
; CI-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
; CI-MESA: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI-MESA: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C1]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY6]](s32)
+ ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
+ ; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY3]](s32)
; CI-MESA: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
; CI-MESA: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -10160,10 +9067,9 @@ body: |
; CI-MESA: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p1) :: (load (s8) from unknown-address + 9, addrspace 1)
; CI-MESA: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD8]](s32)
; CI-MESA: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C1]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY8]](s32)
+ ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
+ ; CI-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY4]](s32)
; CI-MESA: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; CI-MESA: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
; CI-MESA: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
@@ -10186,8 +9092,7 @@ body: |
; CI-MESA: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR6]](s32)
; CI-MESA: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR4]](s16)
; CI-MESA: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C8]]
+ ; CI-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C8]]
; CI-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C7]](s32)
; CI-MESA: [[OR7:%[0-9]+]]:_(s32) = G_OR [[ZEXT4]], [[SHL7]]
; CI-MESA: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR7]](s32)
@@ -10271,8 +9176,7 @@ body: |
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR6]](s32)
; VI: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR4]](s16)
; VI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C7]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C7]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C6]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[ZEXT4]], [[SHL7]]
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR7]](s32)
@@ -10302,15 +9206,9 @@ body: |
; GFX9-HSA: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; GFX9-HSA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-HSA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C4]](s32)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD4]](s32), [[BITCAST]](s32)
; GFX9-HSA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9-HSA: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-HSA: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
@@ -10386,8 +9284,7 @@ body: |
; GFX9-MESA: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[OR3]](s16)
; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[ANYEXT3]](s32)
; GFX9-MESA: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[OR4]](s16)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT4]](s32), [[COPY1]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT4]](s32), [[BITCAST]](s32)
; GFX9-MESA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9-MESA: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-MESA: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
@@ -10549,10 +9446,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -10561,10 +9456,8 @@ body: |
; SI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s16) from unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -10572,10 +9465,8 @@ body: |
; SI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p1) :: (load (s16) from unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; SI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p1) :: (load (s16) from unknown-address + 10, addrspace 1)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -10593,10 +9484,8 @@ body: |
; CI-MESA: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-MESA: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; CI-MESA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -10605,10 +9494,8 @@ body: |
; CI-MESA: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s16) from unknown-address + 4, addrspace 1)
; CI-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -10616,10 +9503,8 @@ body: |
; CI-MESA: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p1) :: (load (s16) from unknown-address + 8, addrspace 1)
; CI-MESA: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; CI-MESA: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p1) :: (load (s16) from unknown-address + 10, addrspace 1)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -10632,10 +9517,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -10644,10 +9527,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s16) from unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -10655,10 +9536,8 @@ body: |
; VI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p1) :: (load (s16) from unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; VI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p1) :: (load (s16) from unknown-address + 10, addrspace 1)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -10676,10 +9555,8 @@ body: |
; GFX9-MESA: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; GFX9-MESA: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; GFX9-MESA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -10688,10 +9565,8 @@ body: |
; GFX9-MESA: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s16) from unknown-address + 4, addrspace 1)
; GFX9-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; GFX9-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9-MESA: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -10699,10 +9574,8 @@ body: |
; GFX9-MESA: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p1) :: (load (s16) from unknown-address + 8, addrspace 1)
; GFX9-MESA: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; GFX9-MESA: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p1) :: (load (s16) from unknown-address + 10, addrspace 1)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX9-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -10732,20 +9605,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -10758,18 +9627,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -10781,18 +9646,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s8) from unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -10816,20 +9677,16 @@ body: |
; CI-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -10842,18 +9699,14 @@ body: |
; CI-MESA: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; CI-MESA: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI-MESA: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -10865,18 +9718,14 @@ body: |
; CI-MESA: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s8) from unknown-address + 10, addrspace 1)
; CI-MESA: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; CI-MESA: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; CI-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI-MESA: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI-MESA: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI-MESA: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -10895,20 +9744,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -10921,18 +9766,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -10944,18 +9785,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s8) from unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -10979,20 +9816,16 @@ body: |
; GFX9-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; GFX9-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -11005,18 +9838,14 @@ body: |
; GFX9-MESA: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; GFX9-MESA: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9-MESA: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -11028,18 +9857,14 @@ body: |
; GFX9-MESA: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s8) from unknown-address + 10, addrspace 1)
; GFX9-MESA: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; GFX9-MESA: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; GFX9-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9-MESA: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9-MESA: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9-MESA: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -11076,31 +9901,23 @@ body: |
; SI: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; SI: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
@@ -11128,31 +9945,23 @@ body: |
; CI-HSA: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; CI-HSA: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
; CI-HSA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-HSA: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; CI-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CI-HSA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-HSA: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; CI-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-HSA: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; CI-HSA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; CI-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; CI-HSA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; CI-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; CI-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; CI-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; CI-HSA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
; CI-HSA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI-HSA: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
@@ -11180,31 +9989,23 @@ body: |
; CI-MESA: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; CI-MESA: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
; CI-MESA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-MESA: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-MESA: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI-MESA: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
@@ -11232,31 +10033,23 @@ body: |
; VI: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; VI: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
@@ -11283,18 +10076,10 @@ body: |
; GFX9-HSA: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>), [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF1]](<8 x s16>)
; GFX9-HSA: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; GFX9-HSA: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9-HSA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX9-HSA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[LSHR]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST2]](s32), [[LSHR1]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST3]](s32), [[LSHR2]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST4]](s32), [[BITCAST5]](s32)
; GFX9-HSA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9-HSA: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-HSA: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
@@ -11318,18 +10103,10 @@ body: |
; GFX9-MESA: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>), [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF1]](<8 x s16>)
; GFX9-MESA: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; GFX9-MESA: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX9-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[LSHR]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST2]](s32), [[LSHR1]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST3]](s32), [[LSHR2]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST4]](s32), [[BITCAST5]](s32)
; GFX9-MESA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9-MESA: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-MESA: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
@@ -11382,31 +10159,23 @@ body: |
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C6]](s32)
; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C7]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C7]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C7]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C7]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C6]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C7]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C7]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C7]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C7]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C7]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C7]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C7]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C7]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C7]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
@@ -11444,31 +10213,23 @@ body: |
; CI-HSA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-HSA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C6]](s32)
; CI-HSA: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C7]]
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C7]]
+ ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C7]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C7]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C6]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-HSA: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C7]]
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C7]]
+ ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C7]]
+ ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C7]]
; CI-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-HSA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-HSA: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C7]]
- ; CI-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
+ ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C7]]
+ ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C7]]
; CI-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C6]](s32)
; CI-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-HSA: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; CI-HSA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; CI-HSA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
+ ; CI-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C7]]
+ ; CI-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C7]]
; CI-HSA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-HSA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI-HSA: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
@@ -11506,31 +10267,23 @@ body: |
; CI-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C6]](s32)
; CI-MESA: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C7]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C7]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C7]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C7]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C6]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-MESA: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C7]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C7]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C7]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C7]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C7]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C7]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C7]]
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C6]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-MESA: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
+ ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C7]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C7]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI-MESA: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
@@ -11568,31 +10321,23 @@ body: |
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C6]](s32)
; VI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C7]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C7]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C7]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C7]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C6]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C7]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C7]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C7]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C7]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C7]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C7]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C7]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C7]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C7]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; VI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
@@ -11629,18 +10374,10 @@ body: |
; GFX9-HSA: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; GFX9-HSA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-HSA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C6]](s32)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9-HSA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9-HSA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD4]](s32), [[LOAD5]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD6]](s32), [[BITCAST]](s32)
; GFX9-HSA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9-HSA: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-HSA: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
@@ -11674,18 +10411,10 @@ body: |
; GFX9-MESA: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; GFX9-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C6]](s32)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD4]](s32), [[LOAD5]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD6]](s32), [[BITCAST]](s32)
; GFX9-MESA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9-MESA: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-MESA: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
@@ -11738,31 +10467,23 @@ body: |
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C6]](s32)
; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C7]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C7]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C7]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C7]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C6]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C7]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C7]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C7]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C7]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C7]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C7]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C7]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C7]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C7]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
@@ -11800,31 +10521,23 @@ body: |
; CI-HSA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-HSA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C6]](s32)
; CI-HSA: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C7]]
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C7]]
+ ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C7]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C7]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C6]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-HSA: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C7]]
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C7]]
+ ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C7]]
+ ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C7]]
; CI-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-HSA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-HSA: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C7]]
- ; CI-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
+ ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C7]]
+ ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C7]]
; CI-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C6]](s32)
; CI-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-HSA: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; CI-HSA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; CI-HSA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
+ ; CI-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C7]]
+ ; CI-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C7]]
; CI-HSA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-HSA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI-HSA: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
@@ -11862,31 +10575,23 @@ body: |
; CI-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C6]](s32)
; CI-MESA: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C7]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C7]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C7]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C7]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C6]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-MESA: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C7]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C7]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C7]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C7]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C7]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C7]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C7]]
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C6]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-MESA: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
+ ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C7]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C7]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI-MESA: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
@@ -11924,31 +10629,23 @@ body: |
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C6]](s32)
; VI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C7]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C7]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C7]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C7]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C6]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C7]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C7]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C7]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C7]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C7]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C7]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C7]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C7]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C7]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; VI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
@@ -11985,18 +10682,10 @@ body: |
; GFX9-HSA: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; GFX9-HSA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-HSA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C6]](s32)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9-HSA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9-HSA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD4]](s32), [[LOAD5]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD6]](s32), [[BITCAST]](s32)
; GFX9-HSA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9-HSA: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-HSA: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
@@ -12030,18 +10719,10 @@ body: |
; GFX9-MESA: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; GFX9-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C6]](s32)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD4]](s32), [[LOAD5]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD6]](s32), [[BITCAST]](s32)
; GFX9-MESA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9-MESA: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-MESA: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
@@ -12108,77 +10789,58 @@ body: |
; SI: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C4]](s32)
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C5]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C5]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C5]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C5]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C5]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C5]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C5]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C5]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C5]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C5]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C4]](s32)
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; SI: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C5]]
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C5]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C4]](s32)
- ; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[COPY9]], [[SHL4]]
+ ; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL4]]
; SI: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C5]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C5]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL5]]
; SI: [[BITCAST13:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C5]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C5]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C5]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C5]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL6]]
; SI: [[BITCAST14:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR6]](s32)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C5]]
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C5]]
+ ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C5]]
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C5]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL7]]
; SI: [[BITCAST15:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR7]](s32)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C5]]
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C5]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C5]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C5]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C4]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[AND14]], [[SHL8]]
; SI: [[BITCAST16:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR8]](s32)
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; SI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C5]]
- ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C5]]
+ ; SI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C5]]
+ ; SI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C5]]
; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; SI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL9]]
; SI: [[BITCAST17:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR9]](s32)
- ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; SI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C5]]
+ ; SI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C5]]
; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[C6]], [[C4]](s32)
; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[AND18]], [[SHL10]]
; SI: [[BITCAST18:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR10]](s32)
@@ -12189,31 +10851,23 @@ body: |
; SI: [[UV8:%[0-9]+]]:_(<2 x s16>), [[UV9:%[0-9]+]]:_(<2 x s16>), [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF4]](<8 x s16>)
; SI: [[BITCAST19:%[0-9]+]]:_(s32) = G_BITCAST [[UV8]](<2 x s16>)
; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST19]], [[C4]](s32)
- ; SI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C5]]
- ; SI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C5]]
+ ; SI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C5]]
+ ; SI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C5]]
; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND20]], [[C4]](s32)
; SI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[AND19]], [[SHL11]]
; SI: [[BITCAST20:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR11]](s32)
- ; SI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C5]]
- ; SI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C5]]
+ ; SI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C5]]
+ ; SI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C5]]
; SI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C4]](s32)
; SI: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND21]], [[SHL12]]
; SI: [[BITCAST21:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR12]](s32)
- ; SI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C5]]
- ; SI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C5]]
+ ; SI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C5]]
+ ; SI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C5]]
; SI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C4]](s32)
; SI: [[OR13:%[0-9]+]]:_(s32) = G_OR [[AND23]], [[SHL13]]
; SI: [[BITCAST22:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR13]](s32)
- ; SI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C5]]
- ; SI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[BITCAST19]](s32)
- ; SI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C5]]
+ ; SI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C5]]
+ ; SI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[BITCAST19]], [[C5]]
; SI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C4]](s32)
; SI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[AND25]], [[SHL14]]
; SI: [[BITCAST23:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR14]](s32)
@@ -12251,31 +10905,23 @@ body: |
; CI-HSA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-HSA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C6]](s32)
; CI-HSA: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C7]]
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C7]]
+ ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C7]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C7]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C6]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-HSA: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C7]]
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C7]]
+ ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C7]]
+ ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C7]]
; CI-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-HSA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-HSA: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C7]]
- ; CI-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
+ ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C7]]
+ ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C7]]
; CI-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C6]](s32)
; CI-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-HSA: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; CI-HSA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; CI-HSA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
+ ; CI-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C7]]
+ ; CI-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C7]]
; CI-HSA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-HSA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI-HSA: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
@@ -12327,77 +10973,58 @@ body: |
; CI-MESA: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CI-MESA: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C4]](s32)
; CI-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C5]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C5]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-MESA: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C5]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C5]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C5]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C5]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C5]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C5]]
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-MESA: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C5]]
+ ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C5]]
; CI-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C4]](s32)
+ ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C4]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI-MESA: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
- ; CI-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; CI-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C5]]
+ ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C5]]
; CI-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C4]](s32)
- ; CI-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[COPY9]], [[SHL4]]
+ ; CI-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL4]]
; CI-MESA: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; CI-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C5]]
- ; CI-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C5]]
+ ; CI-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
+ ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
; CI-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL5]]
; CI-MESA: [[BITCAST13:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
- ; CI-MESA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CI-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C5]]
- ; CI-MESA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C5]]
+ ; CI-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C5]]
+ ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C5]]
; CI-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C4]](s32)
; CI-MESA: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL6]]
; CI-MESA: [[BITCAST14:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR6]](s32)
- ; CI-MESA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CI-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C5]]
- ; CI-MESA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; CI-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C5]]
+ ; CI-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C5]]
+ ; CI-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C5]]
; CI-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI-MESA: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL7]]
; CI-MESA: [[BITCAST15:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR7]](s32)
- ; CI-MESA: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C5]]
- ; CI-MESA: [[COPY18:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; CI-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C5]]
+ ; CI-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C5]]
+ ; CI-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C5]]
; CI-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C4]](s32)
; CI-MESA: [[OR8:%[0-9]+]]:_(s32) = G_OR [[AND14]], [[SHL8]]
; CI-MESA: [[BITCAST16:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR8]](s32)
- ; CI-MESA: [[COPY19:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; CI-MESA: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C5]]
- ; CI-MESA: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CI-MESA: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C5]]
+ ; CI-MESA: [[AND16:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C5]]
+ ; CI-MESA: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C5]]
; CI-MESA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; CI-MESA: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL9]]
; CI-MESA: [[BITCAST17:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR9]](s32)
- ; CI-MESA: [[COPY21:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; CI-MESA: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C5]]
+ ; CI-MESA: [[AND18:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C5]]
; CI-MESA: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[C6]], [[C4]](s32)
; CI-MESA: [[OR10:%[0-9]+]]:_(s32) = G_OR [[AND18]], [[SHL10]]
; CI-MESA: [[BITCAST18:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR10]](s32)
@@ -12408,31 +11035,23 @@ body: |
; CI-MESA: [[UV8:%[0-9]+]]:_(<2 x s16>), [[UV9:%[0-9]+]]:_(<2 x s16>), [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF4]](<8 x s16>)
; CI-MESA: [[BITCAST19:%[0-9]+]]:_(s32) = G_BITCAST [[UV8]](<2 x s16>)
; CI-MESA: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST19]], [[C4]](s32)
- ; CI-MESA: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C5]]
- ; CI-MESA: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C5]]
+ ; CI-MESA: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C5]]
+ ; CI-MESA: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C5]]
; CI-MESA: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND20]], [[C4]](s32)
; CI-MESA: [[OR11:%[0-9]+]]:_(s32) = G_OR [[AND19]], [[SHL11]]
; CI-MESA: [[BITCAST20:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR11]](s32)
- ; CI-MESA: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C5]]
- ; CI-MESA: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C5]]
+ ; CI-MESA: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C5]]
+ ; CI-MESA: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C5]]
; CI-MESA: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C4]](s32)
; CI-MESA: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND21]], [[SHL12]]
; CI-MESA: [[BITCAST21:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR12]](s32)
- ; CI-MESA: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-MESA: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C5]]
- ; CI-MESA: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C5]]
+ ; CI-MESA: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C5]]
+ ; CI-MESA: [[AND24:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C5]]
; CI-MESA: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C4]](s32)
; CI-MESA: [[OR13:%[0-9]+]]:_(s32) = G_OR [[AND23]], [[SHL13]]
; CI-MESA: [[BITCAST22:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR13]](s32)
- ; CI-MESA: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-MESA: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C5]]
- ; CI-MESA: [[COPY29:%[0-9]+]]:_(s32) = COPY [[BITCAST19]](s32)
- ; CI-MESA: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C5]]
+ ; CI-MESA: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C5]]
+ ; CI-MESA: [[AND26:%[0-9]+]]:_(s32) = G_AND [[BITCAST19]], [[C5]]
; CI-MESA: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C4]](s32)
; CI-MESA: [[OR14:%[0-9]+]]:_(s32) = G_OR [[AND25]], [[SHL14]]
; CI-MESA: [[BITCAST23:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR14]](s32)
@@ -12484,77 +11103,58 @@ body: |
; VI: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; VI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C4]](s32)
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C5]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C5]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C5]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C5]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C5]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C5]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C5]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C5]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C5]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C5]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C4]](s32)
+ ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; VI: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C5]]
+ ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C5]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C4]](s32)
- ; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[COPY9]], [[SHL4]]
+ ; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL4]]
; VI: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C5]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C5]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C5]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL5]]
; VI: [[BITCAST13:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C5]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C5]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C5]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C5]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL6]]
; VI: [[BITCAST14:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR6]](s32)
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C5]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C5]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C5]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C5]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL7]]
; VI: [[BITCAST15:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR7]](s32)
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C5]]
- ; VI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C5]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C5]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C5]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C4]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[AND14]], [[SHL8]]
; VI: [[BITCAST16:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR8]](s32)
- ; VI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; VI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C5]]
- ; VI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C5]]
+ ; VI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C5]]
+ ; VI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C5]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL9]]
; VI: [[BITCAST17:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR9]](s32)
- ; VI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; VI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C5]]
+ ; VI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C5]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[C6]], [[C4]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[AND18]], [[SHL10]]
; VI: [[BITCAST18:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR10]](s32)
@@ -12565,31 +11165,23 @@ body: |
; VI: [[UV8:%[0-9]+]]:_(<2 x s16>), [[UV9:%[0-9]+]]:_(<2 x s16>), [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF4]](<8 x s16>)
; VI: [[BITCAST19:%[0-9]+]]:_(s32) = G_BITCAST [[UV8]](<2 x s16>)
; VI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST19]], [[C4]](s32)
- ; VI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C5]]
- ; VI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C5]]
+ ; VI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C5]]
+ ; VI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C5]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND20]], [[C4]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[AND19]], [[SHL11]]
; VI: [[BITCAST20:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR11]](s32)
- ; VI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C5]]
- ; VI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C5]]
+ ; VI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C5]]
+ ; VI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C5]]
; VI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C4]](s32)
; VI: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND21]], [[SHL12]]
; VI: [[BITCAST21:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR12]](s32)
- ; VI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C5]]
- ; VI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C5]]
+ ; VI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C5]]
+ ; VI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C5]]
; VI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C4]](s32)
; VI: [[OR13:%[0-9]+]]:_(s32) = G_OR [[AND23]], [[SHL13]]
; VI: [[BITCAST22:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR13]](s32)
- ; VI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C5]]
- ; VI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[BITCAST19]](s32)
- ; VI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C5]]
+ ; VI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C5]]
+ ; VI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[BITCAST19]], [[C5]]
; VI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C4]](s32)
; VI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[AND25]], [[SHL14]]
; VI: [[BITCAST23:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR14]](s32)
@@ -12626,18 +11218,10 @@ body: |
; GFX9-HSA: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; GFX9-HSA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-HSA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C6]](s32)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9-HSA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9-HSA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD4]](s32), [[LOAD5]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD6]](s32), [[BITCAST]](s32)
; GFX9-HSA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9-HSA: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-HSA: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
@@ -12685,39 +11269,20 @@ body: |
; GFX9-MESA: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C4]](s32)
; GFX9-MESA: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; GFX9-MESA: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C4]](s32)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD4]](s32), [[LOAD5]](s32)
; GFX9-MESA: [[DEF3:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[DEF3]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
- ; GFX9-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[DEF3]](s32)
- ; GFX9-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
- ; GFX9-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
- ; GFX9-MESA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9-MESA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
- ; GFX9-MESA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9-MESA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
- ; GFX9-MESA: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9-MESA: [[COPY18:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)
- ; GFX9-MESA: [[COPY19:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; GFX9-MESA: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC9:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
- ; GFX9-MESA: [[COPY21:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC10:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[DEF3]](s32)
+ ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[DEF3]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD6]](s32), [[COPY1]](s32)
+ ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[DEF3]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[BITCAST]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST2]](s32), [[LSHR2]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST3]](s32), [[BITCAST4]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR4]](s32), [[BITCAST5]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC9:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST6]](s32), [[LSHR6]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC10:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST7]](s32), [[DEF3]](s32)
; GFX9-MESA: [[CONCAT_VECTORS:%[0-9]+]]:_(<42 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>), [[BUILD_VECTOR_TRUNC4]](<2 x s16>), [[BUILD_VECTOR_TRUNC5]](<2 x s16>), [[BUILD_VECTOR_TRUNC6]](<2 x s16>), [[BUILD_VECTOR_TRUNC7]](<2 x s16>), [[BUILD_VECTOR_TRUNC8]](<2 x s16>), [[BUILD_VECTOR_TRUNC9]](<2 x s16>), [[BUILD_VECTOR_TRUNC10]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>)
; GFX9-MESA: [[DEF4:%[0-9]+]]:_(<22 x s16>) = G_IMPLICIT_DEF
; GFX9-MESA: [[DEF5:%[0-9]+]]:_(<8 x s16>) = G_IMPLICIT_DEF
@@ -12725,18 +11290,10 @@ body: |
; GFX9-MESA: [[UV8:%[0-9]+]]:_(<2 x s16>), [[UV9:%[0-9]+]]:_(<2 x s16>), [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[DEF5]](<8 x s16>)
; GFX9-MESA: [[BITCAST8:%[0-9]+]]:_(s32) = G_BITCAST [[UV8]](<2 x s16>)
; GFX9-MESA: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST8]], [[C4]](s32)
- ; GFX9-MESA: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC11:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY22]](s32), [[COPY23]](s32)
- ; GFX9-MESA: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC12:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY24]](s32), [[COPY25]](s32)
- ; GFX9-MESA: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-MESA: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC13:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY26]](s32), [[COPY27]](s32)
- ; GFX9-MESA: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9-MESA: [[COPY29:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC14:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY28]](s32), [[COPY29]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC11:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC12:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC13:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD4]](s32), [[LOAD5]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC14:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD6]](s32), [[BITCAST8]](s32)
; GFX9-MESA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC11]](<2 x s16>)
; GFX9-MESA: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC12]](<2 x s16>)
; GFX9-MESA: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC13]](<2 x s16>)
@@ -12770,8 +11327,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -12782,10 +11338,9 @@ body: |
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
@@ -12795,10 +11350,9 @@ body: |
; SI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p1) :: (load (s8) from unknown-address + 5, addrspace 1)
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; SI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
@@ -12807,10 +11361,9 @@ body: |
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; SI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY6]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
+ ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY3]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; SI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -12820,10 +11373,9 @@ body: |
; SI: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p1) :: (load (s8) from unknown-address + 9, addrspace 1)
; SI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD8]](s32)
; SI: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C1]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY8]](s32)
+ ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
+ ; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY4]](s32)
; SI: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; SI: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
; SI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
@@ -12832,10 +11384,9 @@ body: |
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
; SI: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD10]](s32)
; SI: [[AND10:%[0-9]+]]:_(s16) = G_AND [[TRUNC10]], [[C1]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
- ; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY10]](s32)
+ ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
+ ; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY5]](s32)
; SI: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
; SI: [[OR5:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC11]]
; SI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
@@ -12844,10 +11395,9 @@ body: |
; SI: [[LOAD13:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD12]](p1) :: (load (s8) from unknown-address + 13, addrspace 1)
; SI: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD12]](s32)
; SI: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC12]], [[C1]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY12]](s32)
+ ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
+ ; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY6]](s32)
; SI: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; SI: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[TRUNC13]]
; SI: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
@@ -12891,54 +11441,42 @@ body: |
; SI: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR9]](s32)
; SI: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
; SI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[COPY14]], [[C7]](s32)
+ ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C7]](s32)
; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[ZEXT6]], [[SHL10]]
; SI: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR10]](s32)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; SI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C9]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C9]]
; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C7]](s32)
- ; SI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL11]]
+ ; SI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[COPY8]], [[SHL11]]
; SI: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR11]](s32)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C9]]
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C9]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C9]]
+ ; SI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C9]]
; SI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND16]], [[C7]](s32)
; SI: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND15]], [[SHL12]]
; SI: [[BITCAST13:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR12]](s32)
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C9]]
- ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C9]]
+ ; SI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C9]]
+ ; SI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C9]]
; SI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C7]](s32)
; SI: [[OR13:%[0-9]+]]:_(s32) = G_OR [[AND17]], [[SHL13]]
; SI: [[BITCAST14:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR13]](s32)
- ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C9]]
- ; SI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; SI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C9]]
+ ; SI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C9]]
+ ; SI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C9]]
; SI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND20]], [[C7]](s32)
; SI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[AND19]], [[SHL14]]
; SI: [[BITCAST15:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR14]](s32)
- ; SI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C9]]
- ; SI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; SI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C9]]
+ ; SI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C9]]
+ ; SI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C9]]
; SI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C7]](s32)
; SI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND21]], [[SHL15]]
; SI: [[BITCAST16:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR15]](s32)
- ; SI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; SI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C9]]
- ; SI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C9]]
+ ; SI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C9]]
+ ; SI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C9]]
; SI: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C7]](s32)
; SI: [[OR16:%[0-9]+]]:_(s32) = G_OR [[AND23]], [[SHL16]]
; SI: [[BITCAST17:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR16]](s32)
- ; SI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; SI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C9]]
+ ; SI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C9]]
; SI: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[C8]], [[C7]](s32)
; SI: [[OR17:%[0-9]+]]:_(s32) = G_OR [[AND25]], [[SHL17]]
; SI: [[BITCAST18:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR17]](s32)
@@ -12965,8 +11503,7 @@ body: |
; SI: [[OR20:%[0-9]+]]:_(s32) = G_OR [[ZEXT11]], [[SHL20]]
; SI: [[BITCAST22:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR20]](s32)
; SI: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
- ; SI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[BITCAST19]](s32)
- ; SI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C9]]
+ ; SI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[BITCAST19]], [[C9]]
; SI: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C7]](s32)
; SI: [[OR21:%[0-9]+]]:_(s32) = G_OR [[ZEXT13]], [[SHL21]]
; SI: [[BITCAST23:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR21]](s32)
@@ -13004,31 +11541,23 @@ body: |
; CI-HSA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-HSA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C6]](s32)
; CI-HSA: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C7]]
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C7]]
+ ; CI-HSA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C7]]
+ ; CI-HSA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C7]]
; CI-HSA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C6]](s32)
; CI-HSA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-HSA: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C7]]
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C7]]
+ ; CI-HSA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C7]]
+ ; CI-HSA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C7]]
; CI-HSA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-HSA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-HSA: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C7]]
- ; CI-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
+ ; CI-HSA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C7]]
+ ; CI-HSA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C7]]
; CI-HSA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C6]](s32)
; CI-HSA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-HSA: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; CI-HSA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; CI-HSA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
+ ; CI-HSA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C7]]
+ ; CI-HSA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C7]]
; CI-HSA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-HSA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI-HSA: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
@@ -13047,8 +11576,7 @@ body: |
; CI-MESA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -13059,10 +11587,9 @@ body: |
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; CI-MESA: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-MESA: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; CI-MESA: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-MESA: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
@@ -13072,10 +11599,9 @@ body: |
; CI-MESA: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p1) :: (load (s8) from unknown-address + 5, addrspace 1)
; CI-MESA: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI-MESA: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; CI-MESA: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI-MESA: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
@@ -13084,10 +11610,9 @@ body: |
; CI-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
; CI-MESA: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI-MESA: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C1]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY6]](s32)
+ ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
+ ; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY3]](s32)
; CI-MESA: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
; CI-MESA: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -13097,10 +11622,9 @@ body: |
; CI-MESA: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p1) :: (load (s8) from unknown-address + 9, addrspace 1)
; CI-MESA: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD8]](s32)
; CI-MESA: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C1]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY8]](s32)
+ ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
+ ; CI-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY4]](s32)
; CI-MESA: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; CI-MESA: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
; CI-MESA: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
@@ -13109,10 +11633,9 @@ body: |
; CI-MESA: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
; CI-MESA: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD10]](s32)
; CI-MESA: [[AND10:%[0-9]+]]:_(s16) = G_AND [[TRUNC10]], [[C1]]
- ; CI-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
- ; CI-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY10]](s32)
+ ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
+ ; CI-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY5]](s32)
; CI-MESA: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
; CI-MESA: [[OR5:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC11]]
; CI-MESA: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
@@ -13121,10 +11644,9 @@ body: |
; CI-MESA: [[LOAD13:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD12]](p1) :: (load (s8) from unknown-address + 13, addrspace 1)
; CI-MESA: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD12]](s32)
; CI-MESA: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC12]], [[C1]]
- ; CI-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-MESA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY12]](s32)
+ ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
+ ; CI-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY6]](s32)
; CI-MESA: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; CI-MESA: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[TRUNC13]]
; CI-MESA: [[DEF:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
@@ -13168,54 +11690,42 @@ body: |
; CI-MESA: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR9]](s32)
; CI-MESA: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
; CI-MESA: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CI-MESA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[COPY14]], [[C7]](s32)
+ ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C7]](s32)
; CI-MESA: [[OR10:%[0-9]+]]:_(s32) = G_OR [[ZEXT6]], [[SHL10]]
; CI-MESA: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR10]](s32)
- ; CI-MESA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI-MESA: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C9]]
+ ; CI-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C9]]
; CI-MESA: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C7]](s32)
- ; CI-MESA: [[OR11:%[0-9]+]]:_(s32) = G_OR [[COPY15]], [[SHL11]]
+ ; CI-MESA: [[OR11:%[0-9]+]]:_(s32) = G_OR [[COPY8]], [[SHL11]]
; CI-MESA: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR11]](s32)
- ; CI-MESA: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C9]]
- ; CI-MESA: [[COPY18:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI-MESA: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C9]]
+ ; CI-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C9]]
+ ; CI-MESA: [[AND16:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C9]]
; CI-MESA: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND16]], [[C7]](s32)
; CI-MESA: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND15]], [[SHL12]]
; CI-MESA: [[BITCAST13:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR12]](s32)
- ; CI-MESA: [[COPY19:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CI-MESA: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C9]]
- ; CI-MESA: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-MESA: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C9]]
+ ; CI-MESA: [[AND17:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C9]]
+ ; CI-MESA: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C9]]
; CI-MESA: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C7]](s32)
; CI-MESA: [[OR13:%[0-9]+]]:_(s32) = G_OR [[AND17]], [[SHL13]]
; CI-MESA: [[BITCAST14:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR13]](s32)
- ; CI-MESA: [[COPY21:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CI-MESA: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C9]]
- ; CI-MESA: [[COPY22:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; CI-MESA: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C9]]
+ ; CI-MESA: [[AND19:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C9]]
+ ; CI-MESA: [[AND20:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C9]]
; CI-MESA: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND20]], [[C7]](s32)
; CI-MESA: [[OR14:%[0-9]+]]:_(s32) = G_OR [[AND19]], [[SHL14]]
; CI-MESA: [[BITCAST15:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR14]](s32)
- ; CI-MESA: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI-MESA: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C9]]
- ; CI-MESA: [[COPY24:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; CI-MESA: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C9]]
+ ; CI-MESA: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C9]]
+ ; CI-MESA: [[AND22:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C9]]
; CI-MESA: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C7]](s32)
; CI-MESA: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND21]], [[SHL15]]
; CI-MESA: [[BITCAST16:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR15]](s32)
- ; CI-MESA: [[COPY25:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; CI-MESA: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C9]]
- ; CI-MESA: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CI-MESA: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C9]]
+ ; CI-MESA: [[AND23:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C9]]
+ ; CI-MESA: [[AND24:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C9]]
; CI-MESA: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C7]](s32)
; CI-MESA: [[OR16:%[0-9]+]]:_(s32) = G_OR [[AND23]], [[SHL16]]
; CI-MESA: [[BITCAST17:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR16]](s32)
- ; CI-MESA: [[COPY27:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; CI-MESA: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C9]]
+ ; CI-MESA: [[AND25:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C9]]
; CI-MESA: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[C8]], [[C7]](s32)
; CI-MESA: [[OR17:%[0-9]+]]:_(s32) = G_OR [[AND25]], [[SHL17]]
; CI-MESA: [[BITCAST18:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR17]](s32)
@@ -13242,8 +11752,7 @@ body: |
; CI-MESA: [[OR20:%[0-9]+]]:_(s32) = G_OR [[ZEXT11]], [[SHL20]]
; CI-MESA: [[BITCAST22:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR20]](s32)
; CI-MESA: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
- ; CI-MESA: [[COPY28:%[0-9]+]]:_(s32) = COPY [[BITCAST19]](s32)
- ; CI-MESA: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C9]]
+ ; CI-MESA: [[AND26:%[0-9]+]]:_(s32) = G_AND [[BITCAST19]], [[C9]]
; CI-MESA: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C7]](s32)
; CI-MESA: [[OR21:%[0-9]+]]:_(s32) = G_OR [[ZEXT13]], [[SHL21]]
; CI-MESA: [[BITCAST23:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR21]](s32)
@@ -13375,48 +11884,36 @@ body: |
; VI: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR10]](s32)
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
; VI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C8]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C8]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C6]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL11]]
; VI: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR11]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C8]]
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C8]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C8]]
+ ; VI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C8]]
; VI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND16]], [[C6]](s32)
; VI: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND15]], [[SHL12]]
; VI: [[BITCAST13:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR12]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; VI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C8]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C8]]
+ ; VI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C8]]
+ ; VI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C8]]
; VI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C6]](s32)
; VI: [[OR13:%[0-9]+]]:_(s32) = G_OR [[AND17]], [[SHL13]]
; VI: [[BITCAST14:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR13]](s32)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; VI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C8]]
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; VI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C8]]
+ ; VI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C8]]
+ ; VI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C8]]
; VI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND20]], [[C6]](s32)
; VI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[AND19]], [[SHL14]]
; VI: [[BITCAST15:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR14]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C8]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; VI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C8]]
+ ; VI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C8]]
+ ; VI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C8]]
; VI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C6]](s32)
; VI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND21]], [[SHL15]]
; VI: [[BITCAST16:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR15]](s32)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; VI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C8]]
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C8]]
+ ; VI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C8]]
+ ; VI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C8]]
; VI: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C6]](s32)
; VI: [[OR16:%[0-9]+]]:_(s32) = G_OR [[AND23]], [[SHL16]]
; VI: [[BITCAST17:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR16]](s32)
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; VI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C8]]
+ ; VI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C8]]
; VI: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[C7]], [[C6]](s32)
; VI: [[OR17:%[0-9]+]]:_(s32) = G_OR [[AND25]], [[SHL17]]
; VI: [[BITCAST18:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR17]](s32)
@@ -13443,8 +11940,7 @@ body: |
; VI: [[OR20:%[0-9]+]]:_(s32) = G_OR [[ZEXT11]], [[SHL20]]
; VI: [[BITCAST22:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR20]](s32)
; VI: [[ZEXT13:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[BITCAST19]](s32)
- ; VI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C8]]
+ ; VI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[BITCAST19]], [[C8]]
; VI: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C6]](s32)
; VI: [[OR21:%[0-9]+]]:_(s32) = G_OR [[ZEXT13]], [[SHL21]]
; VI: [[BITCAST23:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR21]](s32)
@@ -13481,18 +11977,10 @@ body: |
; GFX9-HSA: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; GFX9-HSA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-HSA: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C6]](s32)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9-HSA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9-HSA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD4]](s32), [[LOAD5]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD6]](s32), [[BITCAST]](s32)
; GFX9-HSA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9-HSA: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9-HSA: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
@@ -13612,25 +12100,13 @@ body: |
; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[DEF3]](s32)
; GFX9-MESA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT6]](s32), [[COPY1]](s32)
; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[DEF3]](s32)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
- ; GFX9-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
- ; GFX9-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; GFX9-MESA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC9:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
- ; GFX9-MESA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC10:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[DEF3]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[BITCAST]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST2]](s32), [[LSHR2]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST3]](s32), [[BITCAST4]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR4]](s32), [[BITCAST5]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC9:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST6]](s32), [[LSHR6]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC10:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST7]](s32), [[DEF3]](s32)
; GFX9-MESA: [[CONCAT_VECTORS:%[0-9]+]]:_(<42 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>), [[BUILD_VECTOR_TRUNC4]](<2 x s16>), [[BUILD_VECTOR_TRUNC5]](<2 x s16>), [[BUILD_VECTOR_TRUNC6]](<2 x s16>), [[BUILD_VECTOR_TRUNC7]](<2 x s16>), [[BUILD_VECTOR_TRUNC8]](<2 x s16>), [[BUILD_VECTOR_TRUNC9]](<2 x s16>), [[BUILD_VECTOR_TRUNC10]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>), [[DEF]](<2 x s16>)
; GFX9-MESA: [[DEF4:%[0-9]+]]:_(<22 x s16>) = G_IMPLICIT_DEF
; GFX9-MESA: [[DEF5:%[0-9]+]]:_(<8 x s16>) = G_IMPLICIT_DEF
@@ -13648,8 +12124,7 @@ body: |
; GFX9-MESA: [[ANYEXT12:%[0-9]+]]:_(s32) = G_ANYEXT [[OR5]](s16)
; GFX9-MESA: [[BUILD_VECTOR_TRUNC13:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT11]](s32), [[ANYEXT12]](s32)
; GFX9-MESA: [[ANYEXT13:%[0-9]+]]:_(s32) = G_ANYEXT [[OR6]](s16)
- ; GFX9-MESA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC14:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT13]](s32), [[COPY15]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC14:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT13]](s32), [[BITCAST8]](s32)
; GFX9-MESA: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC11]](<2 x s16>)
; GFX9-MESA: $vgpr1 = COPY [[BUILD_VECTOR_TRUNC12]](<2 x s16>)
; GFX9-MESA: $vgpr2 = COPY [[BUILD_VECTOR_TRUNC13]](<2 x s16>)
@@ -13831,10 +12306,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -13843,10 +12316,8 @@ body: |
; SI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s16) from unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -13862,10 +12333,8 @@ body: |
; CI-MESA: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-MESA: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; CI-MESA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -13874,10 +12343,8 @@ body: |
; CI-MESA: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s16) from unknown-address + 4, addrspace 1)
; CI-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -13889,10 +12356,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -13901,10 +12366,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s16) from unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -13920,10 +12383,8 @@ body: |
; GFX9-MESA: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; GFX9-MESA: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; GFX9-MESA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -13932,10 +12393,8 @@ body: |
; GFX9-MESA: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s16) from unknown-address + 4, addrspace 1)
; GFX9-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; GFX9-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -13964,20 +12423,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -13990,18 +12445,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -14023,20 +12474,16 @@ body: |
; CI-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -14049,18 +12496,14 @@ body: |
; CI-MESA: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; CI-MESA: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -14078,20 +12521,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -14104,18 +12543,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -14137,20 +12572,16 @@ body: |
; GFX9-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; GFX9-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -14163,18 +12594,14 @@ body: |
; GFX9-MESA: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; GFX9-MESA: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -14609,17 +13036,13 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -14632,16 +13055,12 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s16) from unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s16) from unknown-address + 14, addrspace 1)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; SI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR3]](s32)
@@ -14664,17 +13083,13 @@ body: |
; CI-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -14687,16 +13102,12 @@ body: |
; CI-MESA: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s16) from unknown-address + 12, addrspace 1)
; CI-MESA: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s16) from unknown-address + 14, addrspace 1)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C4]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI-MESA: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR3]](s32)
@@ -14715,17 +13126,13 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -14738,16 +13145,12 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s16) from unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s16) from unknown-address + 14, addrspace 1)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; VI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR3]](s32)
@@ -14770,17 +13173,13 @@ body: |
; GFX9-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
; GFX9-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; GFX9-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9-MESA: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -14793,16 +13192,12 @@ body: |
; GFX9-MESA: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s16) from unknown-address + 12, addrspace 1)
; GFX9-MESA: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s16) from unknown-address + 14, addrspace 1)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
- ; GFX9-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; GFX9-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
+ ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C4]](s32)
; GFX9-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX9-MESA: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR3]](s32)
@@ -14849,31 +13244,27 @@ body: |
; SI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; SI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; SI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; SI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; SI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -14906,34 +13297,30 @@ body: |
; SI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p1) :: (load (s8) from unknown-address + 15, addrspace 1)
; SI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD8]](s32)
; SI: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C7]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C9]]
- ; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY8]](s32)
+ ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C9]]
+ ; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY4]](s32)
; SI: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; SI: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
; SI: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD10]](s32)
; SI: [[AND10:%[0-9]+]]:_(s16) = G_AND [[TRUNC10]], [[C7]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C9]]
- ; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY10]](s32)
+ ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C9]]
+ ; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY5]](s32)
; SI: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL7]](s32)
; SI: [[OR7:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC11]]
; SI: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD12]](s32)
; SI: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC12]], [[C7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C9]]
- ; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY12]](s32)
+ ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C9]]
+ ; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY6]](s32)
; SI: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
; SI: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[TRUNC13]]
; SI: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD14]](s32)
; SI: [[AND14:%[0-9]+]]:_(s16) = G_AND [[TRUNC14]], [[C7]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C9]]
- ; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY14]](s32)
+ ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C9]]
+ ; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY7]](s32)
; SI: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[SHL9]](s32)
; SI: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[TRUNC15]]
; SI: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
@@ -14981,31 +13368,27 @@ body: |
; CI-MESA: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI-MESA: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-MESA: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-MESA: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI-MESA: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-MESA: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI-MESA: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI-MESA: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI-MESA: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI-MESA: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI-MESA: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -15038,34 +13421,30 @@ body: |
; CI-MESA: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p1) :: (load (s8) from unknown-address + 15, addrspace 1)
; CI-MESA: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD8]](s32)
; CI-MESA: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C7]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C9]]
- ; CI-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY8]](s32)
+ ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C9]]
+ ; CI-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY4]](s32)
; CI-MESA: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; CI-MESA: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
; CI-MESA: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD10]](s32)
; CI-MESA: [[AND10:%[0-9]+]]:_(s16) = G_AND [[TRUNC10]], [[C7]]
- ; CI-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C9]]
- ; CI-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY10]](s32)
+ ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C9]]
+ ; CI-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY5]](s32)
; CI-MESA: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL7]](s32)
; CI-MESA: [[OR7:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC11]]
; CI-MESA: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD12]](s32)
; CI-MESA: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC12]], [[C7]]
- ; CI-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C9]]
- ; CI-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY12]](s32)
+ ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C9]]
+ ; CI-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY6]](s32)
; CI-MESA: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
; CI-MESA: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[TRUNC13]]
; CI-MESA: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD14]](s32)
; CI-MESA: [[AND14:%[0-9]+]]:_(s16) = G_AND [[TRUNC14]], [[C7]]
- ; CI-MESA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C9]]
- ; CI-MESA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY14]](s32)
+ ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C9]]
+ ; CI-MESA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY7]](s32)
; CI-MESA: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[SHL9]](s32)
; CI-MESA: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[TRUNC15]]
; CI-MESA: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
@@ -15523,31 +13902,27 @@ body: |
; SI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; SI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; SI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; SI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; SI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -15580,34 +13955,30 @@ body: |
; SI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p1) :: (load (s8) from unknown-address + 15, addrspace 1)
; SI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD8]](s32)
; SI: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C7]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C9]]
- ; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY8]](s32)
+ ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C9]]
+ ; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY4]](s32)
; SI: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; SI: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
; SI: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD10]](s32)
; SI: [[AND10:%[0-9]+]]:_(s16) = G_AND [[TRUNC10]], [[C7]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C9]]
- ; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY10]](s32)
+ ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C9]]
+ ; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY5]](s32)
; SI: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL7]](s32)
; SI: [[OR7:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC11]]
; SI: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD12]](s32)
; SI: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC12]], [[C7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C9]]
- ; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY12]](s32)
+ ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C9]]
+ ; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY6]](s32)
; SI: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
; SI: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[TRUNC13]]
; SI: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD14]](s32)
; SI: [[AND14:%[0-9]+]]:_(s16) = G_AND [[TRUNC14]], [[C7]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C9]]
- ; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY14]](s32)
+ ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C9]]
+ ; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY7]](s32)
; SI: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[SHL9]](s32)
; SI: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[TRUNC15]]
; SI: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
@@ -15638,34 +14009,30 @@ body: |
; SI: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p1) :: (load (s8) from unknown-address + 23, addrspace 1)
; SI: [[TRUNC16:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD16]](s32)
; SI: [[AND16:%[0-9]+]]:_(s16) = G_AND [[TRUNC16]], [[C7]]
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; SI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C9]]
- ; SI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[COPY16]](s32)
+ ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C9]]
+ ; SI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[COPY8]](s32)
; SI: [[TRUNC17:%[0-9]+]]:_(s16) = G_TRUNC [[SHL12]](s32)
; SI: [[OR12:%[0-9]+]]:_(s16) = G_OR [[AND16]], [[TRUNC17]]
; SI: [[TRUNC18:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD18]](s32)
; SI: [[AND18:%[0-9]+]]:_(s16) = G_AND [[TRUNC18]], [[C7]]
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; SI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C9]]
- ; SI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[COPY18]](s32)
+ ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C9]]
+ ; SI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[COPY9]](s32)
; SI: [[TRUNC19:%[0-9]+]]:_(s16) = G_TRUNC [[SHL13]](s32)
; SI: [[OR13:%[0-9]+]]:_(s16) = G_OR [[AND18]], [[TRUNC19]]
; SI: [[TRUNC20:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD20]](s32)
; SI: [[AND20:%[0-9]+]]:_(s16) = G_AND [[TRUNC20]], [[C7]]
- ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; SI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C9]]
- ; SI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[COPY20]](s32)
+ ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C9]]
+ ; SI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[COPY10]](s32)
; SI: [[TRUNC21:%[0-9]+]]:_(s16) = G_TRUNC [[SHL14]](s32)
; SI: [[OR14:%[0-9]+]]:_(s16) = G_OR [[AND20]], [[TRUNC21]]
; SI: [[TRUNC22:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD22]](s32)
; SI: [[AND22:%[0-9]+]]:_(s16) = G_AND [[TRUNC22]], [[C7]]
- ; SI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; SI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C9]]
- ; SI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[COPY22]](s32)
+ ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C9]]
+ ; SI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[COPY11]](s32)
; SI: [[TRUNC23:%[0-9]+]]:_(s16) = G_TRUNC [[SHL15]](s32)
; SI: [[OR15:%[0-9]+]]:_(s16) = G_OR [[AND22]], [[TRUNC23]]
; SI: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[OR12]](s16)
@@ -15722,31 +14089,27 @@ body: |
; CI-MESA: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI-MESA: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-MESA: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-MESA: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI-MESA: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-MESA: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI-MESA: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI-MESA: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI-MESA: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI-MESA: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI-MESA: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -15779,34 +14142,30 @@ body: |
; CI-MESA: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p1) :: (load (s8) from unknown-address + 15, addrspace 1)
; CI-MESA: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD8]](s32)
; CI-MESA: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C7]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C9]]
- ; CI-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY8]](s32)
+ ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C9]]
+ ; CI-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY4]](s32)
; CI-MESA: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; CI-MESA: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
; CI-MESA: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD10]](s32)
; CI-MESA: [[AND10:%[0-9]+]]:_(s16) = G_AND [[TRUNC10]], [[C7]]
- ; CI-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C9]]
- ; CI-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY10]](s32)
+ ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C9]]
+ ; CI-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY5]](s32)
; CI-MESA: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL7]](s32)
; CI-MESA: [[OR7:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC11]]
; CI-MESA: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD12]](s32)
; CI-MESA: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC12]], [[C7]]
- ; CI-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C9]]
- ; CI-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY12]](s32)
+ ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C9]]
+ ; CI-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY6]](s32)
; CI-MESA: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
; CI-MESA: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[TRUNC13]]
; CI-MESA: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD14]](s32)
; CI-MESA: [[AND14:%[0-9]+]]:_(s16) = G_AND [[TRUNC14]], [[C7]]
- ; CI-MESA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C9]]
- ; CI-MESA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY14]](s32)
+ ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C9]]
+ ; CI-MESA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY7]](s32)
; CI-MESA: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[SHL9]](s32)
; CI-MESA: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[TRUNC15]]
; CI-MESA: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
@@ -15837,34 +14196,30 @@ body: |
; CI-MESA: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p1) :: (load (s8) from unknown-address + 23, addrspace 1)
; CI-MESA: [[TRUNC16:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD16]](s32)
; CI-MESA: [[AND16:%[0-9]+]]:_(s16) = G_AND [[TRUNC16]], [[C7]]
- ; CI-MESA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; CI-MESA: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C9]]
- ; CI-MESA: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[COPY16]](s32)
+ ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C9]]
+ ; CI-MESA: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[COPY8]](s32)
; CI-MESA: [[TRUNC17:%[0-9]+]]:_(s16) = G_TRUNC [[SHL12]](s32)
; CI-MESA: [[OR12:%[0-9]+]]:_(s16) = G_OR [[AND16]], [[TRUNC17]]
; CI-MESA: [[TRUNC18:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD18]](s32)
; CI-MESA: [[AND18:%[0-9]+]]:_(s16) = G_AND [[TRUNC18]], [[C7]]
- ; CI-MESA: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; CI-MESA: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C9]]
- ; CI-MESA: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[COPY18]](s32)
+ ; CI-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C9]]
+ ; CI-MESA: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[COPY9]](s32)
; CI-MESA: [[TRUNC19:%[0-9]+]]:_(s16) = G_TRUNC [[SHL13]](s32)
; CI-MESA: [[OR13:%[0-9]+]]:_(s16) = G_OR [[AND18]], [[TRUNC19]]
; CI-MESA: [[TRUNC20:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD20]](s32)
; CI-MESA: [[AND20:%[0-9]+]]:_(s16) = G_AND [[TRUNC20]], [[C7]]
- ; CI-MESA: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; CI-MESA: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C9]]
- ; CI-MESA: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[COPY20]](s32)
+ ; CI-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C9]]
+ ; CI-MESA: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[COPY10]](s32)
; CI-MESA: [[TRUNC21:%[0-9]+]]:_(s16) = G_TRUNC [[SHL14]](s32)
; CI-MESA: [[OR14:%[0-9]+]]:_(s16) = G_OR [[AND20]], [[TRUNC21]]
; CI-MESA: [[TRUNC22:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD22]](s32)
; CI-MESA: [[AND22:%[0-9]+]]:_(s16) = G_AND [[TRUNC22]], [[C7]]
- ; CI-MESA: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; CI-MESA: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C9]]
- ; CI-MESA: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[COPY22]](s32)
+ ; CI-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C9]]
+ ; CI-MESA: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[COPY11]](s32)
; CI-MESA: [[TRUNC23:%[0-9]+]]:_(s16) = G_TRUNC [[SHL15]](s32)
; CI-MESA: [[OR15:%[0-9]+]]:_(s16) = G_OR [[AND22]], [[TRUNC23]]
; CI-MESA: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[OR12]](s16)
@@ -16332,31 +14687,27 @@ body: |
; SI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; SI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; SI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; SI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; SI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -16389,34 +14740,30 @@ body: |
; SI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p1) :: (load (s8) from unknown-address + 15, addrspace 1)
; SI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD8]](s32)
; SI: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C7]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C9]]
- ; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY8]](s32)
+ ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C9]]
+ ; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY4]](s32)
; SI: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; SI: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
; SI: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD10]](s32)
; SI: [[AND10:%[0-9]+]]:_(s16) = G_AND [[TRUNC10]], [[C7]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C9]]
- ; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY10]](s32)
+ ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C9]]
+ ; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY5]](s32)
; SI: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL7]](s32)
; SI: [[OR7:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC11]]
; SI: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD12]](s32)
; SI: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC12]], [[C7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C9]]
- ; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY12]](s32)
+ ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C9]]
+ ; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY6]](s32)
; SI: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
; SI: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[TRUNC13]]
; SI: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD14]](s32)
; SI: [[AND14:%[0-9]+]]:_(s16) = G_AND [[TRUNC14]], [[C7]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C9]]
- ; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY14]](s32)
+ ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C9]]
+ ; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY7]](s32)
; SI: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[SHL9]](s32)
; SI: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[TRUNC15]]
; SI: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
@@ -16447,34 +14794,30 @@ body: |
; SI: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p1) :: (load (s8) from unknown-address + 23, addrspace 1)
; SI: [[TRUNC16:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD16]](s32)
; SI: [[AND16:%[0-9]+]]:_(s16) = G_AND [[TRUNC16]], [[C7]]
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; SI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C9]]
- ; SI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[COPY16]](s32)
+ ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C9]]
+ ; SI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[COPY8]](s32)
; SI: [[TRUNC17:%[0-9]+]]:_(s16) = G_TRUNC [[SHL12]](s32)
; SI: [[OR12:%[0-9]+]]:_(s16) = G_OR [[AND16]], [[TRUNC17]]
; SI: [[TRUNC18:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD18]](s32)
; SI: [[AND18:%[0-9]+]]:_(s16) = G_AND [[TRUNC18]], [[C7]]
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; SI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C9]]
- ; SI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[COPY18]](s32)
+ ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C9]]
+ ; SI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[COPY9]](s32)
; SI: [[TRUNC19:%[0-9]+]]:_(s16) = G_TRUNC [[SHL13]](s32)
; SI: [[OR13:%[0-9]+]]:_(s16) = G_OR [[AND18]], [[TRUNC19]]
; SI: [[TRUNC20:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD20]](s32)
; SI: [[AND20:%[0-9]+]]:_(s16) = G_AND [[TRUNC20]], [[C7]]
- ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; SI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C9]]
- ; SI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[COPY20]](s32)
+ ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C9]]
+ ; SI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[COPY10]](s32)
; SI: [[TRUNC21:%[0-9]+]]:_(s16) = G_TRUNC [[SHL14]](s32)
; SI: [[OR14:%[0-9]+]]:_(s16) = G_OR [[AND20]], [[TRUNC21]]
; SI: [[TRUNC22:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD22]](s32)
; SI: [[AND22:%[0-9]+]]:_(s16) = G_AND [[TRUNC22]], [[C7]]
- ; SI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; SI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C9]]
- ; SI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[COPY22]](s32)
+ ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C9]]
+ ; SI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[COPY11]](s32)
; SI: [[TRUNC23:%[0-9]+]]:_(s16) = G_TRUNC [[SHL15]](s32)
; SI: [[OR15:%[0-9]+]]:_(s16) = G_OR [[AND22]], [[TRUNC23]]
; SI: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[OR12]](s16)
@@ -16505,34 +14848,30 @@ body: |
; SI: [[LOAD31:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD30]](p1) :: (load (s8) from unknown-address + 31, addrspace 1)
; SI: [[TRUNC24:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD24]](s32)
; SI: [[AND24:%[0-9]+]]:_(s16) = G_AND [[TRUNC24]], [[C7]]
- ; SI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LOAD25]](s32)
- ; SI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C9]]
- ; SI: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[COPY24]](s32)
+ ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LOAD25]], [[C9]]
+ ; SI: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[COPY12]](s32)
; SI: [[TRUNC25:%[0-9]+]]:_(s16) = G_TRUNC [[SHL18]](s32)
; SI: [[OR18:%[0-9]+]]:_(s16) = G_OR [[AND24]], [[TRUNC25]]
; SI: [[TRUNC26:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD26]](s32)
; SI: [[AND26:%[0-9]+]]:_(s16) = G_AND [[TRUNC26]], [[C7]]
- ; SI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LOAD27]](s32)
- ; SI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C9]]
- ; SI: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[COPY26]](s32)
+ ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LOAD27]], [[C9]]
+ ; SI: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[COPY13]](s32)
; SI: [[TRUNC27:%[0-9]+]]:_(s16) = G_TRUNC [[SHL19]](s32)
; SI: [[OR19:%[0-9]+]]:_(s16) = G_OR [[AND26]], [[TRUNC27]]
; SI: [[TRUNC28:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD28]](s32)
; SI: [[AND28:%[0-9]+]]:_(s16) = G_AND [[TRUNC28]], [[C7]]
- ; SI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LOAD29]](s32)
- ; SI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C9]]
- ; SI: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[COPY28]](s32)
+ ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LOAD29]], [[C9]]
+ ; SI: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[COPY14]](s32)
; SI: [[TRUNC29:%[0-9]+]]:_(s16) = G_TRUNC [[SHL20]](s32)
; SI: [[OR20:%[0-9]+]]:_(s16) = G_OR [[AND28]], [[TRUNC29]]
; SI: [[TRUNC30:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD30]](s32)
; SI: [[AND30:%[0-9]+]]:_(s16) = G_AND [[TRUNC30]], [[C7]]
- ; SI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LOAD31]](s32)
- ; SI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C9]]
- ; SI: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[COPY30]](s32)
+ ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LOAD31]], [[C9]]
+ ; SI: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[COPY15]](s32)
; SI: [[TRUNC31:%[0-9]+]]:_(s16) = G_TRUNC [[SHL21]](s32)
; SI: [[OR21:%[0-9]+]]:_(s16) = G_OR [[AND30]], [[TRUNC31]]
; SI: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[OR18]](s16)
@@ -16580,31 +14919,27 @@ body: |
; CI-MESA: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI-MESA: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-MESA: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-MESA: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI-MESA: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-MESA: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI-MESA: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI-MESA: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI-MESA: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI-MESA: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI-MESA: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -16637,34 +14972,30 @@ body: |
; CI-MESA: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p1) :: (load (s8) from unknown-address + 15, addrspace 1)
; CI-MESA: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD8]](s32)
; CI-MESA: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C7]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C9]]
- ; CI-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY8]](s32)
+ ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C9]]
+ ; CI-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY4]](s32)
; CI-MESA: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; CI-MESA: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
; CI-MESA: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD10]](s32)
; CI-MESA: [[AND10:%[0-9]+]]:_(s16) = G_AND [[TRUNC10]], [[C7]]
- ; CI-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C9]]
- ; CI-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY10]](s32)
+ ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C9]]
+ ; CI-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY5]](s32)
; CI-MESA: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL7]](s32)
; CI-MESA: [[OR7:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC11]]
; CI-MESA: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD12]](s32)
; CI-MESA: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC12]], [[C7]]
- ; CI-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C9]]
- ; CI-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY12]](s32)
+ ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C9]]
+ ; CI-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY6]](s32)
; CI-MESA: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
; CI-MESA: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[TRUNC13]]
; CI-MESA: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD14]](s32)
; CI-MESA: [[AND14:%[0-9]+]]:_(s16) = G_AND [[TRUNC14]], [[C7]]
- ; CI-MESA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C9]]
- ; CI-MESA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY14]](s32)
+ ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C9]]
+ ; CI-MESA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY7]](s32)
; CI-MESA: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[SHL9]](s32)
; CI-MESA: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[TRUNC15]]
; CI-MESA: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
@@ -16695,34 +15026,30 @@ body: |
; CI-MESA: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p1) :: (load (s8) from unknown-address + 23, addrspace 1)
; CI-MESA: [[TRUNC16:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD16]](s32)
; CI-MESA: [[AND16:%[0-9]+]]:_(s16) = G_AND [[TRUNC16]], [[C7]]
- ; CI-MESA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; CI-MESA: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C9]]
- ; CI-MESA: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[COPY16]](s32)
+ ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C9]]
+ ; CI-MESA: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[COPY8]](s32)
; CI-MESA: [[TRUNC17:%[0-9]+]]:_(s16) = G_TRUNC [[SHL12]](s32)
; CI-MESA: [[OR12:%[0-9]+]]:_(s16) = G_OR [[AND16]], [[TRUNC17]]
; CI-MESA: [[TRUNC18:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD18]](s32)
; CI-MESA: [[AND18:%[0-9]+]]:_(s16) = G_AND [[TRUNC18]], [[C7]]
- ; CI-MESA: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; CI-MESA: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C9]]
- ; CI-MESA: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[COPY18]](s32)
+ ; CI-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C9]]
+ ; CI-MESA: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[COPY9]](s32)
; CI-MESA: [[TRUNC19:%[0-9]+]]:_(s16) = G_TRUNC [[SHL13]](s32)
; CI-MESA: [[OR13:%[0-9]+]]:_(s16) = G_OR [[AND18]], [[TRUNC19]]
; CI-MESA: [[TRUNC20:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD20]](s32)
; CI-MESA: [[AND20:%[0-9]+]]:_(s16) = G_AND [[TRUNC20]], [[C7]]
- ; CI-MESA: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; CI-MESA: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C9]]
- ; CI-MESA: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[COPY20]](s32)
+ ; CI-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C9]]
+ ; CI-MESA: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[COPY10]](s32)
; CI-MESA: [[TRUNC21:%[0-9]+]]:_(s16) = G_TRUNC [[SHL14]](s32)
; CI-MESA: [[OR14:%[0-9]+]]:_(s16) = G_OR [[AND20]], [[TRUNC21]]
; CI-MESA: [[TRUNC22:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD22]](s32)
; CI-MESA: [[AND22:%[0-9]+]]:_(s16) = G_AND [[TRUNC22]], [[C7]]
- ; CI-MESA: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; CI-MESA: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C9]]
- ; CI-MESA: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[COPY22]](s32)
+ ; CI-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C9]]
+ ; CI-MESA: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[COPY11]](s32)
; CI-MESA: [[TRUNC23:%[0-9]+]]:_(s16) = G_TRUNC [[SHL15]](s32)
; CI-MESA: [[OR15:%[0-9]+]]:_(s16) = G_OR [[AND22]], [[TRUNC23]]
; CI-MESA: [[ZEXT8:%[0-9]+]]:_(s32) = G_ZEXT [[OR12]](s16)
@@ -16753,34 +15080,30 @@ body: |
; CI-MESA: [[LOAD31:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD30]](p1) :: (load (s8) from unknown-address + 31, addrspace 1)
; CI-MESA: [[TRUNC24:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD24]](s32)
; CI-MESA: [[AND24:%[0-9]+]]:_(s16) = G_AND [[TRUNC24]], [[C7]]
- ; CI-MESA: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LOAD25]](s32)
- ; CI-MESA: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C9]]
- ; CI-MESA: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[COPY24]](s32)
+ ; CI-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LOAD25]], [[C9]]
+ ; CI-MESA: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[COPY12]](s32)
; CI-MESA: [[TRUNC25:%[0-9]+]]:_(s16) = G_TRUNC [[SHL18]](s32)
; CI-MESA: [[OR18:%[0-9]+]]:_(s16) = G_OR [[AND24]], [[TRUNC25]]
; CI-MESA: [[TRUNC26:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD26]](s32)
; CI-MESA: [[AND26:%[0-9]+]]:_(s16) = G_AND [[TRUNC26]], [[C7]]
- ; CI-MESA: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LOAD27]](s32)
- ; CI-MESA: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C9]]
- ; CI-MESA: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[COPY26]](s32)
+ ; CI-MESA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND27:%[0-9]+]]:_(s32) = G_AND [[LOAD27]], [[C9]]
+ ; CI-MESA: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[COPY13]](s32)
; CI-MESA: [[TRUNC27:%[0-9]+]]:_(s16) = G_TRUNC [[SHL19]](s32)
; CI-MESA: [[OR19:%[0-9]+]]:_(s16) = G_OR [[AND26]], [[TRUNC27]]
; CI-MESA: [[TRUNC28:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD28]](s32)
; CI-MESA: [[AND28:%[0-9]+]]:_(s16) = G_AND [[TRUNC28]], [[C7]]
- ; CI-MESA: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LOAD29]](s32)
- ; CI-MESA: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C9]]
- ; CI-MESA: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[COPY28]](s32)
+ ; CI-MESA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND29:%[0-9]+]]:_(s32) = G_AND [[LOAD29]], [[C9]]
+ ; CI-MESA: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[COPY14]](s32)
; CI-MESA: [[TRUNC29:%[0-9]+]]:_(s16) = G_TRUNC [[SHL20]](s32)
; CI-MESA: [[OR20:%[0-9]+]]:_(s16) = G_OR [[AND28]], [[TRUNC29]]
; CI-MESA: [[TRUNC30:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD30]](s32)
; CI-MESA: [[AND30:%[0-9]+]]:_(s16) = G_AND [[TRUNC30]], [[C7]]
- ; CI-MESA: [[COPY30:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-MESA: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LOAD31]](s32)
- ; CI-MESA: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C9]]
- ; CI-MESA: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[COPY30]](s32)
+ ; CI-MESA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-MESA: [[AND31:%[0-9]+]]:_(s32) = G_AND [[LOAD31]], [[C9]]
+ ; CI-MESA: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[COPY15]](s32)
; CI-MESA: [[TRUNC31:%[0-9]+]]:_(s16) = G_TRUNC [[SHL21]](s32)
; CI-MESA: [[OR21:%[0-9]+]]:_(s16) = G_OR [[AND30]], [[TRUNC31]]
; CI-MESA: [[ZEXT12:%[0-9]+]]:_(s32) = G_ZEXT [[OR18]](s16)
@@ -17410,20 +15733,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -17436,18 +15755,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -17459,18 +15774,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s8) from unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
@@ -17482,18 +15793,14 @@ body: |
; SI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p1) :: (load (s8) from unknown-address + 14, addrspace 1)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; SI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p1) :: (load (s8) from unknown-address + 15, addrspace 1)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; SI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; SI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -17517,20 +15824,16 @@ body: |
; CI-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -17543,18 +15846,14 @@ body: |
; CI-MESA: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; CI-MESA: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI-MESA: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -17566,18 +15865,14 @@ body: |
; CI-MESA: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s8) from unknown-address + 10, addrspace 1)
; CI-MESA: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; CI-MESA: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; CI-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI-MESA: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI-MESA: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI-MESA: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI-MESA: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
@@ -17589,18 +15884,14 @@ body: |
; CI-MESA: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p1) :: (load (s8) from unknown-address + 14, addrspace 1)
; CI-MESA: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; CI-MESA: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p1) :: (load (s8) from unknown-address + 15, addrspace 1)
- ; CI-MESA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI-MESA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI-MESA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI-MESA: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI-MESA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI-MESA: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI-MESA: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI-MESA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI-MESA: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI-MESA: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -17619,20 +15910,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -17645,18 +15932,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -17668,18 +15951,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s8) from unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
@@ -17691,18 +15970,14 @@ body: |
; VI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p1) :: (load (s8) from unknown-address + 14, addrspace 1)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; VI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p1) :: (load (s8) from unknown-address + 15, addrspace 1)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -17726,20 +16001,16 @@ body: |
; GFX9-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; GFX9-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -17752,18 +16023,14 @@ body: |
; GFX9-MESA: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; GFX9-MESA: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9-MESA: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -17775,18 +16042,14 @@ body: |
; GFX9-MESA: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s8) from unknown-address + 10, addrspace 1)
; GFX9-MESA: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; GFX9-MESA: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; GFX9-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9-MESA: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9-MESA: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9-MESA: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9-MESA: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
@@ -17798,18 +16061,14 @@ body: |
; GFX9-MESA: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p1) :: (load (s8) from unknown-address + 14, addrspace 1)
; GFX9-MESA: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; GFX9-MESA: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p1) :: (load (s8) from unknown-address + 15, addrspace 1)
- ; GFX9-MESA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX9-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9-MESA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX9-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX9-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX9-MESA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX9-MESA: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9-MESA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX9-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX9-MESA: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX9-MESA: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9-MESA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX9-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX9-MESA: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX9-MESA: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -17950,20 +16209,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -17977,18 +16232,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR5]](s32)
@@ -18011,20 +16262,16 @@ body: |
; CI-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -18038,18 +16285,14 @@ body: |
; CI-MESA: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; CI-MESA: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI-MESA: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR5]](s32)
@@ -18068,20 +16311,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -18095,18 +16334,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR5]](s32)
@@ -18129,20 +16364,16 @@ body: |
; GFX9-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; GFX9-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -18156,18 +16387,14 @@ body: |
; GFX9-MESA: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; GFX9-MESA: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9-MESA: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[OR5]](s32)
@@ -18270,15 +16497,13 @@ body: |
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -18287,8 +16512,7 @@ body: |
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[OR2]](s32)
; CI-HSA-LABEL: name: test_ext_load_global_s32_from_s24_align1
; CI-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), align 1, addrspace 1)
@@ -18315,15 +16539,13 @@ body: |
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-MESA: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-MESA: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CI-MESA: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -18332,8 +16554,7 @@ body: |
; CI-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI-MESA: $vgpr0 = COPY [[COPY4]](s32)
+ ; CI-MESA: $vgpr0 = COPY [[OR2]](s32)
; VI-LABEL: name: test_ext_load_global_s32_from_s24_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
@@ -18363,8 +16584,7 @@ body: |
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[OR2]](s32)
; GFX9-HSA-LABEL: name: test_ext_load_global_s32_from_s24_align1
; GFX9-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), align 1, addrspace 1)
@@ -18404,8 +16624,7 @@ body: |
; GFX9-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9-MESA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-MESA: $vgpr0 = COPY [[OR2]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = G_LOAD %0 :: (load (s24), align 1, addrspace 1)
$vgpr0 = COPY %1
@@ -18434,25 +16653,22 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD1]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C5]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; SI: $vgpr0 = COPY [[COPY5]](s32)
+ ; SI: $vgpr0 = COPY [[OR2]](s32)
; CI-HSA-LABEL: name: test_ext_load_global_s32_from_s24_align2
; CI-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), addrspace 1)
@@ -18481,25 +16697,22 @@ body: |
; CI-MESA: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CI-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-MESA: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-MESA: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD1]](s32)
; CI-MESA: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
- ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C5]]
+ ; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI-MESA: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-MESA: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CI-MESA: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI-MESA: $vgpr0 = COPY [[COPY5]](s32)
+ ; CI-MESA: $vgpr0 = COPY [[OR2]](s32)
; VI-LABEL: name: test_ext_load_global_s32_from_s24_align2
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
@@ -18531,8 +16744,7 @@ body: |
; VI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[OR2]](s32)
; GFX9-HSA-LABEL: name: test_ext_load_global_s32_from_s24_align2
; GFX9-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), addrspace 1)
@@ -18574,8 +16786,7 @@ body: |
; GFX9-MESA: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9-MESA: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-MESA: $vgpr0 = COPY [[OR2]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = G_LOAD %0 :: (load (s24), align 2, addrspace 1)
$vgpr0 = COPY %1
@@ -19079,20 +17290,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -19105,18 +17312,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -19128,18 +17331,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s8) from unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -19153,18 +17352,14 @@ body: |
; SI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p1) :: (load (s8) from unknown-address + 14, addrspace 1)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; SI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p1) :: (load (s8) from unknown-address + 15, addrspace 1)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; SI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; SI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; SI: [[PTR_ADD15:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C7]](s64)
@@ -19175,18 +17370,14 @@ body: |
; SI: [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD17]](p1) :: (load (s8) from unknown-address + 18, addrspace 1)
; SI: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C2]](s64)
; SI: [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD18]](p1) :: (load (s8) from unknown-address + 19, addrspace 1)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD16]](s32)
- ; SI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; SI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; SI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LOAD16]], [[C3]]
+ ; SI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C3]]
; SI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; SI: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD18]](s32)
- ; SI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; SI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LOAD18]], [[C3]]
; SI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C5]](s32)
; SI: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; SI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; SI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C3]]
; SI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C6]](s32)
; SI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; SI: [[PTR_ADD19:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C8]](s64)
@@ -19197,26 +17388,22 @@ body: |
; SI: [[LOAD22:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD21]](p1) :: (load (s8) from unknown-address + 22, addrspace 1)
; SI: [[PTR_ADD22:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C2]](s64)
; SI: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p1) :: (load (s8) from unknown-address + 23, addrspace 1)
- ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD20]](s32)
- ; SI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; SI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; SI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; SI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD20]], [[C3]]
+ ; SI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C3]]
; SI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C4]](s32)
; SI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; SI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD22]](s32)
- ; SI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; SI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD22]], [[C3]]
; SI: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C5]](s32)
; SI: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; SI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; SI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; SI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C3]]
; SI: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C6]](s32)
; SI: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR11]](s32), [[OR14]](s32), [[OR17]](s32)
; SI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; SI: [[COPY25:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; SI: [[COPY26:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; SI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY25]](s96)
- ; SI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY26]](s96)
+ ; SI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; SI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; SI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; SI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; CI-HSA-LABEL: name: test_global_v2s96_align1
; CI-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 1, addrspace 1)
@@ -19242,20 +17429,16 @@ body: |
; CI-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; CI-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -19268,18 +17451,14 @@ body: |
; CI-MESA: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; CI-MESA: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; CI-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI-MESA: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -19291,18 +17470,14 @@ body: |
; CI-MESA: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s8) from unknown-address + 10, addrspace 1)
; CI-MESA: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; CI-MESA: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; CI-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI-MESA: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI-MESA: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI-MESA: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -19316,18 +17491,14 @@ body: |
; CI-MESA: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p1) :: (load (s8) from unknown-address + 14, addrspace 1)
; CI-MESA: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; CI-MESA: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p1) :: (load (s8) from unknown-address + 15, addrspace 1)
- ; CI-MESA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI-MESA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI-MESA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI-MESA: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI-MESA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI-MESA: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI-MESA: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI-MESA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI-MESA: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI-MESA: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI-MESA: [[PTR_ADD15:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C7]](s64)
@@ -19338,18 +17509,14 @@ body: |
; CI-MESA: [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD17]](p1) :: (load (s8) from unknown-address + 18, addrspace 1)
; CI-MESA: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C2]](s64)
; CI-MESA: [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD18]](p1) :: (load (s8) from unknown-address + 19, addrspace 1)
- ; CI-MESA: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD16]](s32)
- ; CI-MESA: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; CI-MESA: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; CI-MESA: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; CI-MESA: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LOAD16]], [[C3]]
+ ; CI-MESA: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C3]]
; CI-MESA: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; CI-MESA: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; CI-MESA: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD18]](s32)
- ; CI-MESA: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; CI-MESA: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LOAD18]], [[C3]]
; CI-MESA: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C5]](s32)
; CI-MESA: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; CI-MESA: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; CI-MESA: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; CI-MESA: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C3]]
; CI-MESA: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C6]](s32)
; CI-MESA: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; CI-MESA: [[PTR_ADD19:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C8]](s64)
@@ -19360,26 +17527,22 @@ body: |
; CI-MESA: [[LOAD22:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD21]](p1) :: (load (s8) from unknown-address + 22, addrspace 1)
; CI-MESA: [[PTR_ADD22:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C2]](s64)
; CI-MESA: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p1) :: (load (s8) from unknown-address + 23, addrspace 1)
- ; CI-MESA: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD20]](s32)
- ; CI-MESA: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; CI-MESA: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; CI-MESA: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; CI-MESA: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD20]], [[C3]]
+ ; CI-MESA: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C3]]
; CI-MESA: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C4]](s32)
; CI-MESA: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; CI-MESA: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD22]](s32)
- ; CI-MESA: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; CI-MESA: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD22]], [[C3]]
; CI-MESA: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C5]](s32)
; CI-MESA: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; CI-MESA: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; CI-MESA: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; CI-MESA: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C3]]
; CI-MESA: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C6]](s32)
; CI-MESA: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; CI-MESA: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR11]](s32), [[OR14]](s32), [[OR17]](s32)
; CI-MESA: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; CI-MESA: [[COPY25:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; CI-MESA: [[COPY26:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; CI-MESA: $vgpr0_vgpr1_vgpr2 = COPY [[COPY25]](s96)
- ; CI-MESA: $vgpr3_vgpr4_vgpr5 = COPY [[COPY26]](s96)
+ ; CI-MESA: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; CI-MESA: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; CI-MESA: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; CI-MESA: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; VI-LABEL: name: test_global_v2s96_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s8), addrspace 1)
@@ -19393,20 +17556,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -19419,18 +17578,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -19442,18 +17597,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s8) from unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -19467,18 +17618,14 @@ body: |
; VI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p1) :: (load (s8) from unknown-address + 14, addrspace 1)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; VI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p1) :: (load (s8) from unknown-address + 15, addrspace 1)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[PTR_ADD15:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C7]](s64)
@@ -19489,18 +17636,14 @@ body: |
; VI: [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD17]](p1) :: (load (s8) from unknown-address + 18, addrspace 1)
; VI: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C2]](s64)
; VI: [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD18]](p1) :: (load (s8) from unknown-address + 19, addrspace 1)
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD16]](s32)
- ; VI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; VI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; VI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; VI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LOAD16]], [[C3]]
+ ; VI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C3]]
; VI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; VI: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; VI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD18]](s32)
- ; VI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; VI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LOAD18]], [[C3]]
; VI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C5]](s32)
; VI: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; VI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; VI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; VI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C3]]
; VI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C6]](s32)
; VI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; VI: [[PTR_ADD19:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C8]](s64)
@@ -19511,26 +17654,22 @@ body: |
; VI: [[LOAD22:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD21]](p1) :: (load (s8) from unknown-address + 22, addrspace 1)
; VI: [[PTR_ADD22:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C2]](s64)
; VI: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p1) :: (load (s8) from unknown-address + 23, addrspace 1)
- ; VI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD20]](s32)
- ; VI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; VI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; VI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; VI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD20]], [[C3]]
+ ; VI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C3]]
; VI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C4]](s32)
; VI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; VI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD22]](s32)
- ; VI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; VI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD22]], [[C3]]
; VI: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C5]](s32)
; VI: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; VI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; VI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; VI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C3]]
; VI: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C6]](s32)
; VI: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; VI: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR11]](s32), [[OR14]](s32), [[OR17]](s32)
; VI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; VI: [[COPY25:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; VI: [[COPY26:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY25]](s96)
- ; VI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY26]](s96)
+ ; VI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; VI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; VI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; GFX9-HSA-LABEL: name: test_global_v2s96_align1
; GFX9-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 1, addrspace 1)
@@ -19556,20 +17695,16 @@ body: |
; GFX9-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; GFX9-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s8) from unknown-address + 3, addrspace 1)
; GFX9-MESA: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9-MESA: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9-MESA: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -19582,18 +17717,14 @@ body: |
; GFX9-MESA: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s8) from unknown-address + 6, addrspace 1)
; GFX9-MESA: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; GFX9-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s8) from unknown-address + 7, addrspace 1)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9-MESA: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -19605,18 +17736,14 @@ body: |
; GFX9-MESA: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s8) from unknown-address + 10, addrspace 1)
; GFX9-MESA: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; GFX9-MESA: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s8) from unknown-address + 11, addrspace 1)
- ; GFX9-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9-MESA: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9-MESA: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9-MESA: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9-MESA: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9-MESA: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9-MESA: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -19630,18 +17757,14 @@ body: |
; GFX9-MESA: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p1) :: (load (s8) from unknown-address + 14, addrspace 1)
; GFX9-MESA: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; GFX9-MESA: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p1) :: (load (s8) from unknown-address + 15, addrspace 1)
- ; GFX9-MESA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX9-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9-MESA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX9-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9-MESA: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX9-MESA: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX9-MESA: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX9-MESA: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9-MESA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX9-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9-MESA: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX9-MESA: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX9-MESA: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9-MESA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX9-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9-MESA: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX9-MESA: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX9-MESA: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9-MESA: [[PTR_ADD15:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C7]](s64)
@@ -19652,18 +17775,14 @@ body: |
; GFX9-MESA: [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD17]](p1) :: (load (s8) from unknown-address + 18, addrspace 1)
; GFX9-MESA: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C2]](s64)
; GFX9-MESA: [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD18]](p1) :: (load (s8) from unknown-address + 19, addrspace 1)
- ; GFX9-MESA: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD16]](s32)
- ; GFX9-MESA: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; GFX9-MESA: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; GFX9-MESA: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; GFX9-MESA: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LOAD16]], [[C3]]
+ ; GFX9-MESA: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C3]]
; GFX9-MESA: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; GFX9-MESA: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; GFX9-MESA: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD18]](s32)
- ; GFX9-MESA: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; GFX9-MESA: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LOAD18]], [[C3]]
; GFX9-MESA: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C5]](s32)
; GFX9-MESA: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; GFX9-MESA: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; GFX9-MESA: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; GFX9-MESA: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C3]]
; GFX9-MESA: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C6]](s32)
; GFX9-MESA: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; GFX9-MESA: [[PTR_ADD19:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C8]](s64)
@@ -19674,26 +17793,22 @@ body: |
; GFX9-MESA: [[LOAD22:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD21]](p1) :: (load (s8) from unknown-address + 22, addrspace 1)
; GFX9-MESA: [[PTR_ADD22:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C2]](s64)
; GFX9-MESA: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p1) :: (load (s8) from unknown-address + 23, addrspace 1)
- ; GFX9-MESA: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD20]](s32)
- ; GFX9-MESA: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; GFX9-MESA: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; GFX9-MESA: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; GFX9-MESA: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD20]], [[C3]]
+ ; GFX9-MESA: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C3]]
; GFX9-MESA: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C4]](s32)
; GFX9-MESA: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; GFX9-MESA: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD22]](s32)
- ; GFX9-MESA: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; GFX9-MESA: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD22]], [[C3]]
; GFX9-MESA: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C5]](s32)
; GFX9-MESA: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; GFX9-MESA: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; GFX9-MESA: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; GFX9-MESA: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C3]]
; GFX9-MESA: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C6]](s32)
; GFX9-MESA: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; GFX9-MESA: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR11]](s32), [[OR14]](s32), [[OR17]](s32)
; GFX9-MESA: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; GFX9-MESA: [[COPY25:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; GFX9-MESA: [[COPY26:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; GFX9-MESA: $vgpr0_vgpr1_vgpr2 = COPY [[COPY25]](s96)
- ; GFX9-MESA: $vgpr3_vgpr4_vgpr5 = COPY [[COPY26]](s96)
+ ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; GFX9-MESA: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; GFX9-MESA: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(<2 x s96>) = G_LOAD %0 :: (load (<2 x s96>), align 1, addrspace 1)
%2:_(s96) = G_EXTRACT %1, 0
@@ -19715,10 +17830,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -19727,10 +17840,8 @@ body: |
; SI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s16) from unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -19738,10 +17849,8 @@ body: |
; SI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p1) :: (load (s16) from unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; SI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p1) :: (load (s16) from unknown-address + 10, addrspace 1)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -19751,38 +17860,32 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s16) from unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C]](s64)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s16) from unknown-address + 14, addrspace 1)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; SI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s64)
; SI: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD7]](p1) :: (load (s16) from unknown-address + 16, addrspace 1)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C]](s64)
; SI: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p1) :: (load (s16) from unknown-address + 18, addrspace 1)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C1]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C1]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; SI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C4]](s64)
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s16) from unknown-address + 20, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD9]], [[C]](s64)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s16) from unknown-address + 22, addrspace 1)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C1]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C1]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR3]](s32), [[OR4]](s32), [[OR5]](s32)
; SI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; SI: [[COPY13:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; SI: [[COPY14:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; SI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY13]](s96)
- ; SI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY14]](s96)
+ ; SI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; SI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; SI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; SI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; CI-HSA-LABEL: name: test_global_v2s96_align2
; CI-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI-HSA: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 2, addrspace 1)
@@ -19802,10 +17905,8 @@ body: |
; CI-MESA: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; CI-MESA: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; CI-MESA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -19814,10 +17915,8 @@ body: |
; CI-MESA: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s16) from unknown-address + 4, addrspace 1)
; CI-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; CI-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-MESA: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -19825,10 +17924,8 @@ body: |
; CI-MESA: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p1) :: (load (s16) from unknown-address + 8, addrspace 1)
; CI-MESA: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; CI-MESA: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p1) :: (load (s16) from unknown-address + 10, addrspace 1)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; CI-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; CI-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -19838,38 +17935,32 @@ body: |
; CI-MESA: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s16) from unknown-address + 12, addrspace 1)
; CI-MESA: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C]](s64)
; CI-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s16) from unknown-address + 14, addrspace 1)
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; CI-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; CI-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; CI-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI-MESA: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s64)
; CI-MESA: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD7]](p1) :: (load (s16) from unknown-address + 16, addrspace 1)
; CI-MESA: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C]](s64)
; CI-MESA: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p1) :: (load (s16) from unknown-address + 18, addrspace 1)
- ; CI-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; CI-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; CI-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C1]]
+ ; CI-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C1]]
; CI-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
; CI-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; CI-MESA: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C4]](s64)
; CI-MESA: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s16) from unknown-address + 20, addrspace 1)
; CI-MESA: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD9]], [[C]](s64)
; CI-MESA: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s16) from unknown-address + 22, addrspace 1)
- ; CI-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; CI-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; CI-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C1]]
+ ; CI-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C1]]
; CI-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; CI-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; CI-MESA: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR3]](s32), [[OR4]](s32), [[OR5]](s32)
; CI-MESA: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; CI-MESA: [[COPY13:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; CI-MESA: [[COPY14:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; CI-MESA: $vgpr0_vgpr1_vgpr2 = COPY [[COPY13]](s96)
- ; CI-MESA: $vgpr3_vgpr4_vgpr5 = COPY [[COPY14]](s96)
+ ; CI-MESA: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; CI-MESA: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; CI-MESA: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; CI-MESA: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; VI-LABEL: name: test_global_v2s96_align2
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s16), addrspace 1)
@@ -19877,10 +17968,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -19889,10 +17978,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s16) from unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -19900,10 +17987,8 @@ body: |
; VI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p1) :: (load (s16) from unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; VI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p1) :: (load (s16) from unknown-address + 10, addrspace 1)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -19913,38 +17998,32 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s16) from unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C]](s64)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s16) from unknown-address + 14, addrspace 1)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; VI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s64)
; VI: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD7]](p1) :: (load (s16) from unknown-address + 16, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C]](s64)
; VI: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p1) :: (load (s16) from unknown-address + 18, addrspace 1)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C1]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C1]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; VI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C4]](s64)
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s16) from unknown-address + 20, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD9]], [[C]](s64)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s16) from unknown-address + 22, addrspace 1)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C1]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C1]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; VI: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR3]](s32), [[OR4]](s32), [[OR5]](s32)
; VI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; VI: [[COPY13:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; VI: [[COPY14:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY13]](s96)
- ; VI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY14]](s96)
+ ; VI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; VI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; VI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; GFX9-HSA-LABEL: name: test_global_v2s96_align2
; GFX9-HSA: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9-HSA: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p1) :: (load (<3 x s32>), align 2, addrspace 1)
@@ -19964,10 +18043,8 @@ body: |
; GFX9-MESA: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
; GFX9-MESA: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s16) from unknown-address + 2, addrspace 1)
; GFX9-MESA: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9-MESA: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9-MESA: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9-MESA: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-MESA: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9-MESA: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -19976,10 +18053,8 @@ body: |
; GFX9-MESA: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s16) from unknown-address + 4, addrspace 1)
; GFX9-MESA: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)
; GFX9-MESA: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s16) from unknown-address + 6, addrspace 1)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9-MESA: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9-MESA: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9-MESA: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9-MESA: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9-MESA: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -19987,10 +18062,8 @@ body: |
; GFX9-MESA: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p1) :: (load (s16) from unknown-address + 8, addrspace 1)
; GFX9-MESA: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)
; GFX9-MESA: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p1) :: (load (s16) from unknown-address + 10, addrspace 1)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX9-MESA: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX9-MESA: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX9-MESA: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX9-MESA: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX9-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -20000,38 +18073,32 @@ body: |
; GFX9-MESA: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p1) :: (load (s16) from unknown-address + 12, addrspace 1)
; GFX9-MESA: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C]](s64)
; GFX9-MESA: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p1) :: (load (s16) from unknown-address + 14, addrspace 1)
- ; GFX9-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; GFX9-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; GFX9-MESA: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; GFX9-MESA: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; GFX9-MESA: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX9-MESA: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX9-MESA: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s64)
; GFX9-MESA: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD7]](p1) :: (load (s16) from unknown-address + 16, addrspace 1)
; GFX9-MESA: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C]](s64)
; GFX9-MESA: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p1) :: (load (s16) from unknown-address + 18, addrspace 1)
- ; GFX9-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; GFX9-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; GFX9-MESA: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C1]]
+ ; GFX9-MESA: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C1]]
; GFX9-MESA: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
; GFX9-MESA: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; GFX9-MESA: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C4]](s64)
; GFX9-MESA: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p1) :: (load (s16) from unknown-address + 20, addrspace 1)
; GFX9-MESA: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD9]], [[C]](s64)
; GFX9-MESA: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p1) :: (load (s16) from unknown-address + 22, addrspace 1)
- ; GFX9-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; GFX9-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; GFX9-MESA: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C1]]
+ ; GFX9-MESA: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C1]]
; GFX9-MESA: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; GFX9-MESA: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; GFX9-MESA: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR3]](s32), [[OR4]](s32), [[OR5]](s32)
; GFX9-MESA: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; GFX9-MESA: [[COPY13:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; GFX9-MESA: [[COPY14:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; GFX9-MESA: $vgpr0_vgpr1_vgpr2 = COPY [[COPY13]](s96)
- ; GFX9-MESA: $vgpr3_vgpr4_vgpr5 = COPY [[COPY14]](s96)
+ ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; GFX9-MESA: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; GFX9-MESA: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(<2 x s96>) = G_LOAD %0 :: (load (<2 x s96>), align 2, addrspace 1)
%2:_(s96) = G_EXTRACT %1, 0
@@ -20298,39 +18365,7 @@ body: |
; SI: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C29]](s32)
; SI: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; SI: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C30]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; SI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; SI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; SI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; SI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; SI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR24]](s32)
- ; SI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR25]](s32)
- ; SI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR26]](s32)
- ; SI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LSHR27]](s32)
- ; SI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR28]](s32)
- ; SI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR29]](s32)
- ; SI: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR30]](s32)
- ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32), [[COPY32]](s32)
+ ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32), [[LSHR3]](s32), [[LSHR4]](s32), [[LSHR5]](s32), [[LSHR6]](s32), [[LSHR7]](s32), [[LSHR8]](s32), [[LSHR9]](s32), [[LSHR10]](s32), [[LSHR11]](s32), [[LSHR12]](s32), [[LSHR13]](s32), [[LSHR14]](s32), [[LSHR15]](s32), [[LSHR16]](s32), [[LSHR17]](s32), [[LSHR18]](s32), [[LSHR19]](s32), [[LSHR20]](s32), [[LSHR21]](s32), [[LSHR22]](s32), [[LSHR23]](s32), [[LSHR24]](s32), [[LSHR25]](s32), [[LSHR26]](s32), [[LSHR27]](s32), [[LSHR28]](s32), [[LSHR29]](s32), [[LSHR30]](s32)
; SI: [[TRUNC:%[0-9]+]]:_(<32 x s1>) = G_TRUNC [[BUILD_VECTOR]](<32 x s32>)
; SI: $vgpr0 = COPY [[TRUNC]](<32 x s1>)
; CI-HSA-LABEL: name: test_load_global_v32s1_align4
@@ -20398,39 +18433,7 @@ body: |
; CI-HSA: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C29]](s32)
; CI-HSA: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CI-HSA: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C30]](s32)
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI-HSA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CI-HSA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CI-HSA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CI-HSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; CI-HSA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; CI-HSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; CI-HSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; CI-HSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; CI-HSA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; CI-HSA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; CI-HSA: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; CI-HSA: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; CI-HSA: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; CI-HSA: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; CI-HSA: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; CI-HSA: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; CI-HSA: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; CI-HSA: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; CI-HSA: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; CI-HSA: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR24]](s32)
- ; CI-HSA: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR25]](s32)
- ; CI-HSA: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR26]](s32)
- ; CI-HSA: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LSHR27]](s32)
- ; CI-HSA: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR28]](s32)
- ; CI-HSA: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR29]](s32)
- ; CI-HSA: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR30]](s32)
- ; CI-HSA: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32), [[COPY32]](s32)
+ ; CI-HSA: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32), [[LSHR3]](s32), [[LSHR4]](s32), [[LSHR5]](s32), [[LSHR6]](s32), [[LSHR7]](s32), [[LSHR8]](s32), [[LSHR9]](s32), [[LSHR10]](s32), [[LSHR11]](s32), [[LSHR12]](s32), [[LSHR13]](s32), [[LSHR14]](s32), [[LSHR15]](s32), [[LSHR16]](s32), [[LSHR17]](s32), [[LSHR18]](s32), [[LSHR19]](s32), [[LSHR20]](s32), [[LSHR21]](s32), [[LSHR22]](s32), [[LSHR23]](s32), [[LSHR24]](s32), [[LSHR25]](s32), [[LSHR26]](s32), [[LSHR27]](s32), [[LSHR28]](s32), [[LSHR29]](s32), [[LSHR30]](s32)
; CI-HSA: [[TRUNC:%[0-9]+]]:_(<32 x s1>) = G_TRUNC [[BUILD_VECTOR]](<32 x s32>)
; CI-HSA: $vgpr0 = COPY [[TRUNC]](<32 x s1>)
; CI-MESA-LABEL: name: test_load_global_v32s1_align4
@@ -20498,39 +18501,7 @@ body: |
; CI-MESA: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C29]](s32)
; CI-MESA: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CI-MESA: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C30]](s32)
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CI-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CI-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; CI-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; CI-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; CI-MESA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; CI-MESA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; CI-MESA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; CI-MESA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; CI-MESA: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; CI-MESA: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; CI-MESA: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; CI-MESA: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; CI-MESA: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; CI-MESA: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; CI-MESA: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; CI-MESA: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; CI-MESA: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; CI-MESA: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR24]](s32)
- ; CI-MESA: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR25]](s32)
- ; CI-MESA: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR26]](s32)
- ; CI-MESA: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LSHR27]](s32)
- ; CI-MESA: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR28]](s32)
- ; CI-MESA: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR29]](s32)
- ; CI-MESA: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR30]](s32)
- ; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32), [[COPY32]](s32)
+ ; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32), [[LSHR3]](s32), [[LSHR4]](s32), [[LSHR5]](s32), [[LSHR6]](s32), [[LSHR7]](s32), [[LSHR8]](s32), [[LSHR9]](s32), [[LSHR10]](s32), [[LSHR11]](s32), [[LSHR12]](s32), [[LSHR13]](s32), [[LSHR14]](s32), [[LSHR15]](s32), [[LSHR16]](s32), [[LSHR17]](s32), [[LSHR18]](s32), [[LSHR19]](s32), [[LSHR20]](s32), [[LSHR21]](s32), [[LSHR22]](s32), [[LSHR23]](s32), [[LSHR24]](s32), [[LSHR25]](s32), [[LSHR26]](s32), [[LSHR27]](s32), [[LSHR28]](s32), [[LSHR29]](s32), [[LSHR30]](s32)
; CI-MESA: [[TRUNC:%[0-9]+]]:_(<32 x s1>) = G_TRUNC [[BUILD_VECTOR]](<32 x s32>)
; CI-MESA: $vgpr0 = COPY [[TRUNC]](<32 x s1>)
; VI-LABEL: name: test_load_global_v32s1_align4
@@ -20598,39 +18569,7 @@ body: |
; VI: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C29]](s32)
; VI: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; VI: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C30]](s32)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; VI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; VI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; VI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; VI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; VI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; VI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; VI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; VI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; VI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR24]](s32)
- ; VI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR25]](s32)
- ; VI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR26]](s32)
- ; VI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LSHR27]](s32)
- ; VI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR28]](s32)
- ; VI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR29]](s32)
- ; VI: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR30]](s32)
- ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32), [[COPY32]](s32)
+ ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32), [[LSHR3]](s32), [[LSHR4]](s32), [[LSHR5]](s32), [[LSHR6]](s32), [[LSHR7]](s32), [[LSHR8]](s32), [[LSHR9]](s32), [[LSHR10]](s32), [[LSHR11]](s32), [[LSHR12]](s32), [[LSHR13]](s32), [[LSHR14]](s32), [[LSHR15]](s32), [[LSHR16]](s32), [[LSHR17]](s32), [[LSHR18]](s32), [[LSHR19]](s32), [[LSHR20]](s32), [[LSHR21]](s32), [[LSHR22]](s32), [[LSHR23]](s32), [[LSHR24]](s32), [[LSHR25]](s32), [[LSHR26]](s32), [[LSHR27]](s32), [[LSHR28]](s32), [[LSHR29]](s32), [[LSHR30]](s32)
; VI: [[TRUNC:%[0-9]+]]:_(<32 x s1>) = G_TRUNC [[BUILD_VECTOR]](<32 x s32>)
; VI: $vgpr0 = COPY [[TRUNC]](<32 x s1>)
; GFX9-HSA-LABEL: name: test_load_global_v32s1_align4
@@ -20698,54 +18637,22 @@ body: |
; GFX9-HSA: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C29]](s32)
; GFX9-HSA: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX9-HSA: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C30]](s32)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9-HSA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9-HSA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
- ; GFX9-HSA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX9-HSA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
- ; GFX9-HSA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; GFX9-HSA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
- ; GFX9-HSA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; GFX9-HSA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
- ; GFX9-HSA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; GFX9-HSA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
- ; GFX9-HSA: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; GFX9-HSA: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)
- ; GFX9-HSA: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; GFX9-HSA: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC9:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
- ; GFX9-HSA: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; GFX9-HSA: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC10:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
- ; GFX9-HSA: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; GFX9-HSA: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC11:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
- ; GFX9-HSA: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; GFX9-HSA: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR24]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC12:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY25]](s32), [[COPY26]](s32)
- ; GFX9-HSA: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR25]](s32)
- ; GFX9-HSA: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR26]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC13:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY27]](s32), [[COPY28]](s32)
- ; GFX9-HSA: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LSHR27]](s32)
- ; GFX9-HSA: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR28]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC14:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY29]](s32), [[COPY30]](s32)
- ; GFX9-HSA: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR29]](s32)
- ; GFX9-HSA: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR30]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC15:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY31]](s32), [[COPY32]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LSHR]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR1]](s32), [[LSHR2]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR3]](s32), [[LSHR4]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR5]](s32), [[LSHR6]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR7]](s32), [[LSHR8]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR9]](s32), [[LSHR10]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR11]](s32), [[LSHR12]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR13]](s32), [[LSHR14]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR15]](s32), [[LSHR16]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC9:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR17]](s32), [[LSHR18]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC10:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR19]](s32), [[LSHR20]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC11:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR21]](s32), [[LSHR22]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC12:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR23]](s32), [[LSHR24]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC13:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR25]](s32), [[LSHR26]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC14:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR27]](s32), [[LSHR28]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC15:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR29]](s32), [[LSHR30]](s32)
; GFX9-HSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>), [[BUILD_VECTOR_TRUNC4]](<2 x s16>), [[BUILD_VECTOR_TRUNC5]](<2 x s16>), [[BUILD_VECTOR_TRUNC6]](<2 x s16>), [[BUILD_VECTOR_TRUNC7]](<2 x s16>), [[BUILD_VECTOR_TRUNC8]](<2 x s16>), [[BUILD_VECTOR_TRUNC9]](<2 x s16>), [[BUILD_VECTOR_TRUNC10]](<2 x s16>), [[BUILD_VECTOR_TRUNC11]](<2 x s16>), [[BUILD_VECTOR_TRUNC12]](<2 x s16>), [[BUILD_VECTOR_TRUNC13]](<2 x s16>), [[BUILD_VECTOR_TRUNC14]](<2 x s16>), [[BUILD_VECTOR_TRUNC15]](<2 x s16>)
; GFX9-HSA: [[TRUNC:%[0-9]+]]:_(<32 x s1>) = G_TRUNC [[CONCAT_VECTORS]](<32 x s16>)
; GFX9-HSA: $vgpr0 = COPY [[TRUNC]](<32 x s1>)
@@ -20814,54 +18721,22 @@ body: |
; GFX9-MESA: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C29]](s32)
; GFX9-MESA: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX9-MESA: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C30]](s32)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
- ; GFX9-MESA: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX9-MESA: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
- ; GFX9-MESA: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; GFX9-MESA: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
- ; GFX9-MESA: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; GFX9-MESA: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
- ; GFX9-MESA: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; GFX9-MESA: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
- ; GFX9-MESA: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; GFX9-MESA: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY17]](s32), [[COPY18]](s32)
- ; GFX9-MESA: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; GFX9-MESA: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC9:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY19]](s32), [[COPY20]](s32)
- ; GFX9-MESA: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; GFX9-MESA: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC10:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY21]](s32), [[COPY22]](s32)
- ; GFX9-MESA: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; GFX9-MESA: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC11:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY23]](s32), [[COPY24]](s32)
- ; GFX9-MESA: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; GFX9-MESA: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR24]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC12:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY25]](s32), [[COPY26]](s32)
- ; GFX9-MESA: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR25]](s32)
- ; GFX9-MESA: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR26]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC13:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY27]](s32), [[COPY28]](s32)
- ; GFX9-MESA: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LSHR27]](s32)
- ; GFX9-MESA: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR28]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC14:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY29]](s32), [[COPY30]](s32)
- ; GFX9-MESA: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR29]](s32)
- ; GFX9-MESA: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR30]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC15:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY31]](s32), [[COPY32]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LSHR]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR1]](s32), [[LSHR2]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR3]](s32), [[LSHR4]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR5]](s32), [[LSHR6]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR7]](s32), [[LSHR8]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR9]](s32), [[LSHR10]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR11]](s32), [[LSHR12]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR13]](s32), [[LSHR14]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC8:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR15]](s32), [[LSHR16]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC9:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR17]](s32), [[LSHR18]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC10:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR19]](s32), [[LSHR20]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC11:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR21]](s32), [[LSHR22]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC12:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR23]](s32), [[LSHR24]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC13:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR25]](s32), [[LSHR26]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC14:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR27]](s32), [[LSHR28]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC15:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR29]](s32), [[LSHR30]](s32)
; GFX9-MESA: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>), [[BUILD_VECTOR_TRUNC4]](<2 x s16>), [[BUILD_VECTOR_TRUNC5]](<2 x s16>), [[BUILD_VECTOR_TRUNC6]](<2 x s16>), [[BUILD_VECTOR_TRUNC7]](<2 x s16>), [[BUILD_VECTOR_TRUNC8]](<2 x s16>), [[BUILD_VECTOR_TRUNC9]](<2 x s16>), [[BUILD_VECTOR_TRUNC10]](<2 x s16>), [[BUILD_VECTOR_TRUNC11]](<2 x s16>), [[BUILD_VECTOR_TRUNC12]](<2 x s16>), [[BUILD_VECTOR_TRUNC13]](<2 x s16>), [[BUILD_VECTOR_TRUNC14]](<2 x s16>), [[BUILD_VECTOR_TRUNC15]](<2 x s16>)
; GFX9-MESA: [[TRUNC:%[0-9]+]]:_(<32 x s1>) = G_TRUNC [[CONCAT_VECTORS]](<32 x s16>)
; GFX9-MESA: $vgpr0 = COPY [[TRUNC]](<32 x s1>)
@@ -20893,15 +18768,7 @@ body: |
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C5]](s32)
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C6]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32)
+ ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32), [[LSHR3]](s32), [[LSHR4]](s32), [[LSHR5]](s32), [[LSHR6]](s32)
; SI: [[TRUNC:%[0-9]+]]:_(<8 x s4>) = G_TRUNC [[BUILD_VECTOR]](<8 x s32>)
; SI: $vgpr0 = COPY [[TRUNC]](<8 x s4>)
; CI-HSA-LABEL: name: test_load_global_v8s4_align4
@@ -20921,15 +18788,7 @@ body: |
; CI-HSA: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C5]](s32)
; CI-HSA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
; CI-HSA: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C6]](s32)
- ; CI-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI-HSA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CI-HSA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CI-HSA: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32)
+ ; CI-HSA: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32), [[LSHR3]](s32), [[LSHR4]](s32), [[LSHR5]](s32), [[LSHR6]](s32)
; CI-HSA: [[TRUNC:%[0-9]+]]:_(<8 x s4>) = G_TRUNC [[BUILD_VECTOR]](<8 x s32>)
; CI-HSA: $vgpr0 = COPY [[TRUNC]](<8 x s4>)
; CI-MESA-LABEL: name: test_load_global_v8s4_align4
@@ -20949,15 +18808,7 @@ body: |
; CI-MESA: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C5]](s32)
; CI-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
; CI-MESA: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C6]](s32)
- ; CI-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CI-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32)
+ ; CI-MESA: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32), [[LSHR3]](s32), [[LSHR4]](s32), [[LSHR5]](s32), [[LSHR6]](s32)
; CI-MESA: [[TRUNC:%[0-9]+]]:_(<8 x s4>) = G_TRUNC [[BUILD_VECTOR]](<8 x s32>)
; CI-MESA: $vgpr0 = COPY [[TRUNC]](<8 x s4>)
; VI-LABEL: name: test_load_global_v8s4_align4
@@ -20977,15 +18828,7 @@ body: |
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C5]](s32)
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
; VI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C6]](s32)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32)
+ ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32), [[LSHR1]](s32), [[LSHR2]](s32), [[LSHR3]](s32), [[LSHR4]](s32), [[LSHR5]](s32), [[LSHR6]](s32)
; VI: [[TRUNC:%[0-9]+]]:_(<8 x s4>) = G_TRUNC [[BUILD_VECTOR]](<8 x s32>)
; VI: $vgpr0 = COPY [[TRUNC]](<8 x s4>)
; GFX9-HSA-LABEL: name: test_load_global_v8s4_align4
@@ -21005,18 +18848,10 @@ body: |
; GFX9-HSA: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C5]](s32)
; GFX9-HSA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
; GFX9-HSA: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C6]](s32)
- ; GFX9-HSA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-HSA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-HSA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-HSA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-HSA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9-HSA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9-HSA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9-HSA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9-HSA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LSHR]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR1]](s32), [[LSHR2]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR3]](s32), [[LSHR4]](s32)
+ ; GFX9-HSA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR5]](s32), [[LSHR6]](s32)
; GFX9-HSA: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>)
; GFX9-HSA: [[TRUNC:%[0-9]+]]:_(<8 x s4>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>)
; GFX9-HSA: $vgpr0 = COPY [[TRUNC]](<8 x s4>)
@@ -21037,18 +18872,10 @@ body: |
; GFX9-MESA: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C5]](s32)
; GFX9-MESA: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
; GFX9-MESA: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C6]](s32)
- ; GFX9-MESA: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-MESA: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-MESA: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-MESA: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-MESA: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9-MESA: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
- ; GFX9-MESA: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9-MESA: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9-MESA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LSHR]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR1]](s32), [[LSHR2]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR3]](s32), [[LSHR4]](s32)
+ ; GFX9-MESA: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR5]](s32), [[LSHR6]](s32)
; GFX9-MESA: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>), [[BUILD_VECTOR_TRUNC3]](<2 x s16>)
; GFX9-MESA: [[TRUNC:%[0-9]+]]:_(<8 x s4>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>)
; GFX9-MESA: $vgpr0 = COPY [[TRUNC]](<8 x s4>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
index 6606f50c85ec6..ef9c88b930160 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
@@ -18,57 +18,49 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; SI: $vgpr0 = COPY [[AND]](s32)
; CI-LABEL: name: test_load_local_s1_align1
; CI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI: $vgpr0 = COPY [[AND]](s32)
; CI-DS128-LABEL: name: test_load_local_s1_align1
; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; CI-DS128: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI-DS128: $vgpr0 = COPY [[AND]](s32)
; VI-LABEL: name: test_load_local_s1_align1
; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; VI: $vgpr0 = COPY [[AND]](s32)
; GFX9-LABEL: name: test_load_local_s1_align1
; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9: $vgpr0 = COPY [[AND]](s32)
; GFX9-UNALIGNED-LABEL: name: test_load_local_s1_align1
; GFX9-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; GFX9-UNALIGNED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX9-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9-UNALIGNED: $vgpr0 = COPY [[AND]](s32)
; GFX10-LABEL: name: test_load_local_s1_align1
; GFX10: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; GFX10: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX10: $vgpr0 = COPY [[AND]](s32)
; GFX10-UNALIGNED-LABEL: name: test_load_local_s1_align1
; GFX10-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; GFX10-UNALIGNED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX10-UNALIGNED: $vgpr0 = COPY [[AND]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s1) = G_LOAD %0 :: (load (s1), align 1, addrspace 3)
@@ -86,57 +78,49 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; SI: $vgpr0 = COPY [[AND]](s32)
; CI-LABEL: name: test_load_local_s2_align1
; CI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI: $vgpr0 = COPY [[AND]](s32)
; CI-DS128-LABEL: name: test_load_local_s2_align1
; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; CI-DS128: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI-DS128: $vgpr0 = COPY [[AND]](s32)
; VI-LABEL: name: test_load_local_s2_align1
; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; VI: $vgpr0 = COPY [[AND]](s32)
; GFX9-LABEL: name: test_load_local_s2_align1
; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9: $vgpr0 = COPY [[AND]](s32)
; GFX9-UNALIGNED-LABEL: name: test_load_local_s2_align1
; GFX9-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; GFX9-UNALIGNED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX9-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9-UNALIGNED: $vgpr0 = COPY [[AND]](s32)
; GFX10-LABEL: name: test_load_local_s2_align1
; GFX10: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; GFX10: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX10: $vgpr0 = COPY [[AND]](s32)
; GFX10-UNALIGNED-LABEL: name: test_load_local_s2_align1
; GFX10-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; GFX10-UNALIGNED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX10-UNALIGNED: $vgpr0 = COPY [[AND]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s2) = G_LOAD %0 :: (load (s2), align 1, addrspace 3)
@@ -153,43 +137,35 @@ body: |
; SI-LABEL: name: test_load_local_s8_align4
; SI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[LOAD]](s32)
; CI-LABEL: name: test_load_local_s8_align4
; CI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; CI-DS128-LABEL: name: test_load_local_s8_align4
; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-DS128: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_local_s8_align4
; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_local_s8_align4
; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-UNALIGNED-LABEL: name: test_load_local_s8_align4
; GFX9-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-UNALIGNED: $vgpr0 = COPY [[LOAD]](s32)
; GFX10-LABEL: name: test_load_local_s8_align4
; GFX10: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX10: $vgpr0 = COPY [[LOAD]](s32)
; GFX10-UNALIGNED-LABEL: name: test_load_local_s8_align4
; GFX10-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), align 4, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX10-UNALIGNED: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s8) = G_LOAD %0 :: (load (s8), align 4, addrspace 3)
%2:_(s32) = G_ANYEXT %1
@@ -205,43 +181,35 @@ body: |
; SI-LABEL: name: test_load_local_s8_align1
; SI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[LOAD]](s32)
; CI-LABEL: name: test_load_local_s8_align1
; CI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; CI-DS128-LABEL: name: test_load_local_s8_align1
; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-DS128: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_local_s8_align1
; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_local_s8_align1
; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-UNALIGNED-LABEL: name: test_load_local_s8_align1
; GFX9-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-UNALIGNED: $vgpr0 = COPY [[LOAD]](s32)
; GFX10-LABEL: name: test_load_local_s8_align1
; GFX10: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX10: $vgpr0 = COPY [[LOAD]](s32)
; GFX10-UNALIGNED-LABEL: name: test_load_local_s8_align1
; GFX10-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX10-UNALIGNED: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s8) = G_LOAD %0 :: (load (s8), align 1, addrspace 3)
%2:_(s32) = G_ANYEXT %1
@@ -257,43 +225,35 @@ body: |
; SI-LABEL: name: test_load_local_s16_align4
; SI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[LOAD]](s32)
; CI-LABEL: name: test_load_local_s16_align4
; CI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; CI-DS128-LABEL: name: test_load_local_s16_align4
; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-DS128: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_local_s16_align4
; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_local_s16_align4
; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-UNALIGNED-LABEL: name: test_load_local_s16_align4
; GFX9-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-UNALIGNED: $vgpr0 = COPY [[LOAD]](s32)
; GFX10-LABEL: name: test_load_local_s16_align4
; GFX10: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX10: $vgpr0 = COPY [[LOAD]](s32)
; GFX10-UNALIGNED-LABEL: name: test_load_local_s16_align4
; GFX10-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 4, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX10-UNALIGNED: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s16) = G_LOAD %0 :: (load (s16), align 4, addrspace 3)
%2:_(s32) = G_ANYEXT %1
@@ -309,43 +269,35 @@ body: |
; SI-LABEL: name: test_load_local_s16_align2
; SI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[LOAD]](s32)
; CI-LABEL: name: test_load_local_s16_align2
; CI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; CI-DS128-LABEL: name: test_load_local_s16_align2
; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-DS128: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_local_s16_align2
; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_local_s16_align2
; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-UNALIGNED-LABEL: name: test_load_local_s16_align2
; GFX9-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-UNALIGNED: $vgpr0 = COPY [[LOAD]](s32)
; GFX10-LABEL: name: test_load_local_s16_align2
; GFX10: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX10: $vgpr0 = COPY [[LOAD]](s32)
; GFX10-UNALIGNED-LABEL: name: test_load_local_s16_align2
; GFX10-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX10-UNALIGNED: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s16) = G_LOAD %0 :: (load (s16), align 2, addrspace 3)
%2:_(s32) = G_ANYEXT %1
@@ -369,8 +321,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -387,8 +338,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -405,8 +355,7 @@ body: |
; CI-DS128: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI-DS128: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-DS128: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -447,8 +396,7 @@ body: |
; GFX9-UNALIGNED-LABEL: name: test_load_local_s16_align1
; GFX9-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), align 1, addrspace 3)
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-UNALIGNED: $vgpr0 = COPY [[LOAD]](s32)
; GFX10-LABEL: name: test_load_local_s16_align1
; GFX10: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
@@ -543,10 +491,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -558,10 +504,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -573,10 +517,8 @@ body: |
; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI-DS128: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; CI-DS128: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI-DS128: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -588,10 +530,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -603,10 +543,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -622,10 +560,8 @@ body: |
; GFX10: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX10: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX10: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX10: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -637,10 +573,8 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX10-UNALIGNED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX10-UNALIGNED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -669,20 +603,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -700,20 +630,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -731,20 +657,16 @@ body: |
; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-DS128: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI-DS128: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-DS128: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -762,20 +684,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -793,20 +711,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -828,20 +742,16 @@ body: |
; GFX10: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -859,20 +769,16 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10-UNALIGNED: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10-UNALIGNED: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10-UNALIGNED: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10-UNALIGNED: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -891,43 +797,35 @@ body: |
; SI-LABEL: name: test_load_local_s24_align8
; SI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 8, addrspace 3)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[LOAD]](s32)
; CI-LABEL: name: test_load_local_s24_align8
; CI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 8, addrspace 3)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; CI-DS128-LABEL: name: test_load_local_s24_align8
; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 8, addrspace 3)
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-DS128: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_local_s24_align8
; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 8, addrspace 3)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_local_s24_align8
; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 8, addrspace 3)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-UNALIGNED-LABEL: name: test_load_local_s24_align8
; GFX9-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 8, addrspace 3)
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-UNALIGNED: $vgpr0 = COPY [[LOAD]](s32)
; GFX10-LABEL: name: test_load_local_s24_align8
; GFX10: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 8, addrspace 3)
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX10: $vgpr0 = COPY [[LOAD]](s32)
; GFX10-UNALIGNED-LABEL: name: test_load_local_s24_align8
; GFX10-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), align 8, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX10-UNALIGNED: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s24) = G_LOAD %0 :: (load (s24), align 8, addrspace 3)
%2:_(s32) = G_ANYEXT %1
@@ -943,43 +841,35 @@ body: |
; SI-LABEL: name: test_load_local_s24_align4
; SI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[LOAD]](s32)
; CI-LABEL: name: test_load_local_s24_align4
; CI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; CI-DS128-LABEL: name: test_load_local_s24_align4
; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI-DS128: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_local_s24_align4
; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_local_s24_align4
; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-UNALIGNED-LABEL: name: test_load_local_s24_align4
; GFX9-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-UNALIGNED: $vgpr0 = COPY [[LOAD]](s32)
; GFX10-LABEL: name: test_load_local_s24_align4
; GFX10: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX10: $vgpr0 = COPY [[LOAD]](s32)
; GFX10-UNALIGNED-LABEL: name: test_load_local_s24_align4
; GFX10-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX10-UNALIGNED: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s24) = G_LOAD %0 :: (load (s24), align 4, addrspace 3)
%2:_(s32) = G_ANYEXT %1
@@ -1010,25 +900,22 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD1]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C5]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; SI: $vgpr0 = COPY [[COPY5]](s32)
+ ; SI: $vgpr0 = COPY [[OR2]](s32)
; CI-LABEL: name: test_load_local_s24_align2
; CI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
@@ -1047,25 +934,22 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD1]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C5]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI: $vgpr0 = COPY [[COPY5]](s32)
+ ; CI: $vgpr0 = COPY [[OR2]](s32)
; CI-DS128-LABEL: name: test_load_local_s24_align2
; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
@@ -1084,25 +968,22 @@ body: |
; CI-DS128: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CI-DS128: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-DS128: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-DS128: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD1]](s32)
; CI-DS128: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
- ; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C5]]
+ ; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI-DS128: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-DS128: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CI-DS128: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI-DS128: $vgpr0 = COPY [[COPY5]](s32)
+ ; CI-DS128: $vgpr0 = COPY [[OR2]](s32)
; VI-LABEL: name: test_load_local_s24_align2
; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
@@ -1134,8 +1015,7 @@ body: |
; VI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[OR2]](s32)
; GFX9-LABEL: name: test_load_local_s24_align2
; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
@@ -1167,8 +1047,7 @@ body: |
; GFX9: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[OR2]](s32)
; GFX9-UNALIGNED-LABEL: name: test_load_local_s24_align2
; GFX9-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load (s16), addrspace 3)
@@ -1178,8 +1057,7 @@ body: |
; GFX9-UNALIGNED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX9-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; GFX9-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-UNALIGNED: $vgpr0 = COPY [[OR]](s32)
; GFX10-LABEL: name: test_load_local_s24_align2
; GFX10: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
@@ -1211,8 +1089,7 @@ body: |
; GFX10: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX10: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX10: $vgpr0 = COPY [[OR2]](s32)
; GFX10-UNALIGNED-LABEL: name: test_load_local_s24_align2
; GFX10-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
@@ -1244,8 +1121,7 @@ body: |
; GFX10-UNALIGNED: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX10-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX10-UNALIGNED: $vgpr0 = COPY [[OR2]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s24) = G_LOAD %0 :: (load (s24), align 2, addrspace 3)
%2:_(s32) = G_ANYEXT %1
@@ -1274,15 +1150,13 @@ body: |
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -1291,8 +1165,7 @@ body: |
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[OR2]](s32)
; CI-LABEL: name: test_load_local_s24_align1
; CI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
@@ -1309,15 +1182,13 @@ body: |
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -1326,8 +1197,7 @@ body: |
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI: $vgpr0 = COPY [[COPY4]](s32)
+ ; CI: $vgpr0 = COPY [[OR2]](s32)
; CI-DS128-LABEL: name: test_load_local_s24_align1
; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
@@ -1344,15 +1214,13 @@ body: |
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CI-DS128: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-DS128: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-DS128: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-DS128: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CI-DS128: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -1361,8 +1229,7 @@ body: |
; CI-DS128: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI-DS128: $vgpr0 = COPY [[COPY4]](s32)
+ ; CI-DS128: $vgpr0 = COPY [[OR2]](s32)
; VI-LABEL: name: test_load_local_s24_align1
; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
@@ -1392,8 +1259,7 @@ body: |
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[OR2]](s32)
; GFX9-LABEL: name: test_load_local_s24_align1
; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
@@ -1423,8 +1289,7 @@ body: |
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[OR2]](s32)
; GFX9-UNALIGNED-LABEL: name: test_load_local_s24_align1
; GFX9-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load (s16), align 1, addrspace 3)
@@ -1434,8 +1299,7 @@ body: |
; GFX9-UNALIGNED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32)
; GFX9-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; GFX9-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-UNALIGNED: $vgpr0 = COPY [[OR]](s32)
; GFX10-LABEL: name: test_load_local_s24_align1
; GFX10: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
@@ -1465,8 +1329,7 @@ body: |
; GFX10: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX10: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX10: $vgpr0 = COPY [[OR2]](s32)
; GFX10-UNALIGNED-LABEL: name: test_load_local_s24_align1
; GFX10-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
@@ -1496,8 +1359,7 @@ body: |
; GFX10-UNALIGNED: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX10-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX10-UNALIGNED: $vgpr0 = COPY [[OR2]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s24) = G_LOAD %0 :: (load (s24), align 1, addrspace 3)
%2:_(s32) = G_ANYEXT %1
@@ -1513,43 +1375,35 @@ body: |
; SI-LABEL: name: test_load_local_s48_align8
; SI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; SI: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
- ; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; SI: $vgpr0_vgpr1 = COPY [[COPY1]](s64)
+ ; SI: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
; CI-LABEL: name: test_load_local_s48_align8
; CI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
- ; CI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; CI: $vgpr0_vgpr1 = COPY [[COPY1]](s64)
+ ; CI: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
; CI-DS128-LABEL: name: test_load_local_s48_align8
; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; CI-DS128: $vgpr0_vgpr1 = COPY [[COPY1]](s64)
+ ; CI-DS128: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
; VI-LABEL: name: test_load_local_s48_align8
; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
- ; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; VI: $vgpr0_vgpr1 = COPY [[COPY1]](s64)
+ ; VI: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
; GFX9-LABEL: name: test_load_local_s48_align8
; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; GFX9: $vgpr0_vgpr1 = COPY [[COPY1]](s64)
+ ; GFX9: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
; GFX9-UNALIGNED-LABEL: name: test_load_local_s48_align8
; GFX9-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; GFX9-UNALIGNED: $vgpr0_vgpr1 = COPY [[COPY1]](s64)
+ ; GFX9-UNALIGNED: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
; GFX10-LABEL: name: test_load_local_s48_align8
; GFX10: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
- ; GFX10: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; GFX10: $vgpr0_vgpr1 = COPY [[COPY1]](s64)
+ ; GFX10: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
; GFX10-UNALIGNED-LABEL: name: test_load_local_s48_align8
; GFX10-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p3) :: (load (s64), addrspace 3)
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; GFX10-UNALIGNED: $vgpr0_vgpr1 = COPY [[COPY1]](s64)
+ ; GFX10-UNALIGNED: $vgpr0_vgpr1 = COPY [[LOAD]](s64)
%0:_(p3) = COPY $vgpr0
%1:_(s48) = G_LOAD %0 :: (load (s48), align 8, addrspace 3)
%2:_(s64) = G_ANYEXT %1
@@ -1661,17 +1515,13 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -1689,17 +1539,13 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -1717,17 +1563,13 @@ body: |
; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-DS128: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-DS128: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -1745,17 +1587,13 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -1773,17 +1611,13 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -1805,17 +1639,13 @@ body: |
; GFX10: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
; GFX10: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX10: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -1833,17 +1663,13 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
; GFX10-UNALIGNED: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10-UNALIGNED: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX10-UNALIGNED: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -1889,31 +1715,27 @@ body: |
; SI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; SI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; SI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; SI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; SI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -1958,31 +1780,27 @@ body: |
; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -2027,31 +1845,27 @@ body: |
; CI-DS128: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI-DS128: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-DS128: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-DS128: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-DS128: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI-DS128: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-DS128: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI-DS128: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI-DS128: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI-DS128: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI-DS128: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI-DS128: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI-DS128: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI-DS128: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI-DS128: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -2338,20 +2152,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2364,18 +2174,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -2386,18 +2192,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -2416,20 +2218,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2442,18 +2240,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -2464,18 +2258,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -2494,20 +2284,16 @@ body: |
; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-DS128: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI-DS128: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-DS128: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2520,18 +2306,14 @@ body: |
; CI-DS128: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; CI-DS128: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI-DS128: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI-DS128: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-DS128: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-DS128: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI-DS128: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI-DS128: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-DS128: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI-DS128: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-DS128: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI-DS128: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -2542,18 +2324,14 @@ body: |
; CI-DS128: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; CI-DS128: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI-DS128: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; CI-DS128: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI-DS128: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI-DS128: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-DS128: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI-DS128: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI-DS128: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI-DS128: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI-DS128: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI-DS128: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI-DS128: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI-DS128: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI-DS128: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI-DS128: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI-DS128: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI-DS128: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI-DS128: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI-DS128: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI-DS128: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -2572,20 +2350,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2598,18 +2372,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -2620,18 +2390,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -2650,20 +2416,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2676,18 +2438,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -2698,18 +2456,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -2733,20 +2487,16 @@ body: |
; GFX10: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2759,18 +2509,14 @@ body: |
; GFX10: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX10: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX10: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX10: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX10: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX10: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX10: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX10: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX10: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX10: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX10: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX10: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX10: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -2781,18 +2527,14 @@ body: |
; GFX10: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX10: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX10: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX10: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX10: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX10: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX10: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX10: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX10: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX10: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX10: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX10: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX10: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX10: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX10: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX10: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX10: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX10: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -2811,20 +2553,16 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10-UNALIGNED: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10-UNALIGNED: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10-UNALIGNED: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10-UNALIGNED: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2837,18 +2575,14 @@ body: |
; GFX10-UNALIGNED: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX10-UNALIGNED: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX10-UNALIGNED: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX10-UNALIGNED: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX10-UNALIGNED: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX10-UNALIGNED: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX10-UNALIGNED: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -2859,18 +2593,14 @@ body: |
; GFX10-UNALIGNED: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX10-UNALIGNED: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX10-UNALIGNED: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX10-UNALIGNED: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX10-UNALIGNED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX10-UNALIGNED: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX10-UNALIGNED: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX10-UNALIGNED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX10-UNALIGNED: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX10-UNALIGNED: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX10-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -3066,10 +2796,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -3078,10 +2806,8 @@ body: |
; SI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -3089,10 +2815,8 @@ body: |
; SI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; SI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -3105,10 +2829,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -3117,10 +2839,8 @@ body: |
; CI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; CI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -3128,10 +2848,8 @@ body: |
; CI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; CI: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; CI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -3144,10 +2862,8 @@ body: |
; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI-DS128: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; CI-DS128: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI-DS128: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -3156,10 +2872,8 @@ body: |
; CI-DS128: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-DS128: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -3167,10 +2881,8 @@ body: |
; CI-DS128: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; CI-DS128: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; CI-DS128: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -3183,10 +2895,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -3195,10 +2905,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -3206,10 +2914,8 @@ body: |
; VI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; VI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -3222,10 +2928,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -3234,10 +2938,8 @@ body: |
; GFX9: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -3245,10 +2947,8 @@ body: |
; GFX9: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; GFX9: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; GFX9: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -3266,10 +2966,8 @@ body: |
; GFX10: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX10: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX10: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX10: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -3278,10 +2976,8 @@ body: |
; GFX10: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; GFX10: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX10: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX10: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -3289,10 +2985,8 @@ body: |
; GFX10: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; GFX10: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; GFX10: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; GFX10: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX10: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -3305,10 +2999,8 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX10-UNALIGNED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX10-UNALIGNED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -3317,10 +3009,8 @@ body: |
; GFX10-UNALIGNED: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX10-UNALIGNED: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -3328,10 +3018,8 @@ body: |
; GFX10-UNALIGNED: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX10-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -3361,20 +3049,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3387,18 +3071,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -3409,18 +3089,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -3439,20 +3115,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3465,18 +3137,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -3487,18 +3155,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -3517,20 +3181,16 @@ body: |
; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-DS128: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI-DS128: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-DS128: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3543,18 +3203,14 @@ body: |
; CI-DS128: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; CI-DS128: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI-DS128: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI-DS128: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-DS128: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-DS128: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI-DS128: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI-DS128: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-DS128: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI-DS128: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-DS128: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI-DS128: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -3565,18 +3221,14 @@ body: |
; CI-DS128: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; CI-DS128: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI-DS128: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; CI-DS128: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI-DS128: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI-DS128: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-DS128: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI-DS128: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI-DS128: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI-DS128: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI-DS128: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI-DS128: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI-DS128: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI-DS128: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI-DS128: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI-DS128: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI-DS128: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI-DS128: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI-DS128: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI-DS128: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI-DS128: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -3595,20 +3247,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3621,18 +3269,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -3643,18 +3287,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -3673,20 +3313,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3699,18 +3335,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -3721,18 +3353,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -3756,20 +3384,16 @@ body: |
; GFX10: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3782,18 +3406,14 @@ body: |
; GFX10: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX10: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX10: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX10: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX10: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX10: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX10: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX10: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX10: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX10: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX10: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX10: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX10: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -3804,18 +3424,14 @@ body: |
; GFX10: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX10: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX10: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX10: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX10: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX10: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX10: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX10: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX10: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX10: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX10: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX10: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX10: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX10: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX10: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX10: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX10: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX10: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -3834,20 +3450,16 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10-UNALIGNED: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10-UNALIGNED: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10-UNALIGNED: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10-UNALIGNED: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3860,18 +3472,14 @@ body: |
; GFX10-UNALIGNED: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX10-UNALIGNED: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX10-UNALIGNED: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX10-UNALIGNED: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX10-UNALIGNED: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX10-UNALIGNED: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX10-UNALIGNED: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -3882,18 +3490,14 @@ body: |
; GFX10-UNALIGNED: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX10-UNALIGNED: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX10-UNALIGNED: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX10-UNALIGNED: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX10-UNALIGNED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX10-UNALIGNED: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX10-UNALIGNED: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX10-UNALIGNED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX10-UNALIGNED: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX10-UNALIGNED: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX10-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -3923,20 +3527,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3949,18 +3549,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -3972,18 +3568,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[PTR_ADD11:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C7]](s32)
@@ -3994,18 +3586,14 @@ body: |
; SI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; SI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; SI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; SI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR8]](s32), [[OR11]](s32)
@@ -4025,20 +3613,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -4051,18 +3635,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -4074,18 +3654,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[PTR_ADD11:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C7]](s32)
@@ -4096,18 +3672,14 @@ body: |
; CI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; CI: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR8]](s32), [[OR11]](s32)
@@ -4127,20 +3699,16 @@ body: |
; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-DS128: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI-DS128: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-DS128: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -4153,18 +3721,14 @@ body: |
; CI-DS128: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; CI-DS128: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI-DS128: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI-DS128: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-DS128: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-DS128: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI-DS128: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI-DS128: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-DS128: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI-DS128: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-DS128: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI-DS128: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -4175,18 +3739,14 @@ body: |
; CI-DS128: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; CI-DS128: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI-DS128: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; CI-DS128: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI-DS128: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI-DS128: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-DS128: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI-DS128: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI-DS128: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI-DS128: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI-DS128: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI-DS128: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI-DS128: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI-DS128: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI-DS128: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI-DS128: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI-DS128: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI-DS128: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI-DS128: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI-DS128: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI-DS128: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI-DS128: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -4198,18 +3758,14 @@ body: |
; CI-DS128: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; CI-DS128: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; CI-DS128: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; CI-DS128: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI-DS128: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI-DS128: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI-DS128: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI-DS128: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI-DS128: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI-DS128: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI-DS128: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI-DS128: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI-DS128: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI-DS128: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI-DS128: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI-DS128: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI-DS128: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI-DS128: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI-DS128: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI-DS128: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI-DS128: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -4228,20 +3784,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -4254,18 +3806,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -4276,18 +3824,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -4299,18 +3843,14 @@ body: |
; VI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; VI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -4329,20 +3869,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -4355,18 +3891,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -4377,18 +3909,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -4400,18 +3928,14 @@ body: |
; GFX9: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; GFX9: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX9: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX9: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX9: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX9: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX9: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX9: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX9: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -4435,20 +3959,16 @@ body: |
; GFX10: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -4461,18 +3981,14 @@ body: |
; GFX10: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX10: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX10: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX10: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX10: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX10: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX10: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX10: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX10: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX10: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX10: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX10: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX10: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -4483,18 +3999,14 @@ body: |
; GFX10: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX10: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX10: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX10: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX10: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX10: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX10: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX10: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX10: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX10: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX10: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX10: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX10: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX10: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX10: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX10: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX10: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX10: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX10: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -4506,18 +4018,14 @@ body: |
; GFX10: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; GFX10: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX10: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX10: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX10: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX10: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX10: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX10: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX10: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX10: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX10: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX10: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX10: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX10: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX10: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX10: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX10: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -4536,20 +4044,16 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10-UNALIGNED: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10-UNALIGNED: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10-UNALIGNED: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10-UNALIGNED: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -4562,18 +4066,14 @@ body: |
; GFX10-UNALIGNED: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX10-UNALIGNED: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX10-UNALIGNED: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX10-UNALIGNED: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX10-UNALIGNED: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX10-UNALIGNED: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX10-UNALIGNED: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -4584,18 +4084,14 @@ body: |
; GFX10-UNALIGNED: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX10-UNALIGNED: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX10-UNALIGNED: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX10-UNALIGNED: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX10-UNALIGNED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX10-UNALIGNED: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX10-UNALIGNED: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX10-UNALIGNED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX10-UNALIGNED: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX10-UNALIGNED: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX10-UNALIGNED: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -4607,18 +4103,14 @@ body: |
; GFX10-UNALIGNED: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX10-UNALIGNED: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX10-UNALIGNED: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX10-UNALIGNED: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX10-UNALIGNED: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX10-UNALIGNED: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX10-UNALIGNED: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX10-UNALIGNED: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX10-UNALIGNED: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX10-UNALIGNED: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX10-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -4810,10 +4302,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -4822,10 +4312,8 @@ body: |
; SI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -4834,20 +4322,16 @@ body: |
; SI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; SI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[PTR_ADD5:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s32)
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR3]](s32)
@@ -4861,10 +4345,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -4873,10 +4355,8 @@ body: |
; CI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; CI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -4885,20 +4365,16 @@ body: |
; CI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; CI: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; CI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[PTR_ADD5:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s32)
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR3]](s32)
@@ -4912,10 +4388,8 @@ body: |
; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI-DS128: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; CI-DS128: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI-DS128: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -4924,10 +4398,8 @@ body: |
; CI-DS128: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -4936,20 +4408,16 @@ body: |
; CI-DS128: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; CI-DS128: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; CI-DS128: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-DS128: [[PTR_ADD5:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s32)
; CI-DS128: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; CI-DS128: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; CI-DS128: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; CI-DS128: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; CI-DS128: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; CI-DS128: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI-DS128: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI-DS128: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR3]](s32)
@@ -4963,10 +4431,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -4975,10 +4441,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -4987,20 +4451,16 @@ body: |
; VI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; VI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[PTR_ADD5:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s32)
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; VI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR3]](s32)
@@ -5014,10 +4474,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -5026,10 +4484,8 @@ body: |
; GFX9: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -5038,20 +4494,16 @@ body: |
; GFX9: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; GFX9: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; GFX9: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX9: [[PTR_ADD5:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s32)
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR3]](s32)
@@ -5070,10 +4522,8 @@ body: |
; GFX10: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX10: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX10: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX10: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -5082,10 +4532,8 @@ body: |
; GFX10: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; GFX10: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX10: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -5094,20 +4542,16 @@ body: |
; GFX10: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; GFX10: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; GFX10: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; GFX10: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX10: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX10: [[PTR_ADD5:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s32)
; GFX10: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; GFX10: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; GFX10: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; GFX10: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; GFX10: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX10: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX10: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR3]](s32)
@@ -5121,10 +4565,8 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX10-UNALIGNED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX10-UNALIGNED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -5133,10 +4575,8 @@ body: |
; GFX10-UNALIGNED: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX10-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -5145,20 +4585,16 @@ body: |
; GFX10-UNALIGNED: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX10-UNALIGNED: [[PTR_ADD5:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s32)
; GFX10-UNALIGNED: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; GFX10-UNALIGNED: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX10-UNALIGNED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR3]](s32)
@@ -5189,20 +4625,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -5215,18 +4647,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -5238,18 +4666,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[PTR_ADD11:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C7]](s32)
@@ -5260,18 +4684,14 @@ body: |
; SI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; SI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; SI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; SI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR8]](s32), [[OR11]](s32)
@@ -5291,20 +4711,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -5317,18 +4733,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -5340,18 +4752,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[PTR_ADD11:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C7]](s32)
@@ -5362,18 +4770,14 @@ body: |
; CI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; CI: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR8]](s32), [[OR11]](s32)
@@ -5393,20 +4797,16 @@ body: |
; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-DS128: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI-DS128: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-DS128: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -5419,18 +4819,14 @@ body: |
; CI-DS128: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; CI-DS128: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI-DS128: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI-DS128: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-DS128: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-DS128: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI-DS128: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI-DS128: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-DS128: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI-DS128: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-DS128: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI-DS128: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -5441,18 +4837,14 @@ body: |
; CI-DS128: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; CI-DS128: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI-DS128: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; CI-DS128: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI-DS128: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI-DS128: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-DS128: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI-DS128: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI-DS128: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI-DS128: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI-DS128: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI-DS128: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI-DS128: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI-DS128: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI-DS128: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI-DS128: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI-DS128: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI-DS128: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI-DS128: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI-DS128: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI-DS128: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI-DS128: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -5464,18 +4856,14 @@ body: |
; CI-DS128: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; CI-DS128: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; CI-DS128: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; CI-DS128: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI-DS128: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI-DS128: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI-DS128: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI-DS128: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI-DS128: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI-DS128: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI-DS128: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI-DS128: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI-DS128: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI-DS128: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI-DS128: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI-DS128: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI-DS128: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI-DS128: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI-DS128: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI-DS128: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI-DS128: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -5494,20 +4882,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -5520,18 +4904,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -5542,18 +4922,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -5565,18 +4941,14 @@ body: |
; VI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; VI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -5595,20 +4967,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -5621,18 +4989,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -5643,18 +5007,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -5666,18 +5026,14 @@ body: |
; GFX9: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; GFX9: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX9: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX9: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX9: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX9: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX9: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX9: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX9: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -5701,20 +5057,16 @@ body: |
; GFX10: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -5727,18 +5079,14 @@ body: |
; GFX10: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX10: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX10: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX10: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX10: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX10: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX10: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX10: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX10: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX10: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX10: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX10: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX10: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -5749,18 +5097,14 @@ body: |
; GFX10: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX10: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX10: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX10: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX10: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX10: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX10: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX10: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX10: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX10: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX10: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX10: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX10: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX10: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX10: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX10: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX10: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX10: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX10: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -5772,18 +5116,14 @@ body: |
; GFX10: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; GFX10: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX10: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX10: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX10: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX10: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX10: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX10: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX10: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX10: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX10: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX10: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX10: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX10: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX10: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX10: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX10: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -5802,20 +5142,16 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10-UNALIGNED: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10-UNALIGNED: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10-UNALIGNED: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10-UNALIGNED: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -5828,18 +5164,14 @@ body: |
; GFX10-UNALIGNED: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX10-UNALIGNED: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX10-UNALIGNED: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX10-UNALIGNED: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX10-UNALIGNED: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX10-UNALIGNED: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX10-UNALIGNED: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -5850,18 +5182,14 @@ body: |
; GFX10-UNALIGNED: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX10-UNALIGNED: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX10-UNALIGNED: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX10-UNALIGNED: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX10-UNALIGNED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX10-UNALIGNED: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX10-UNALIGNED: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX10-UNALIGNED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX10-UNALIGNED: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX10-UNALIGNED: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX10-UNALIGNED: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -5873,18 +5201,14 @@ body: |
; GFX10-UNALIGNED: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX10-UNALIGNED: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX10-UNALIGNED: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX10-UNALIGNED: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX10-UNALIGNED: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX10-UNALIGNED: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX10-UNALIGNED: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX10-UNALIGNED: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX10-UNALIGNED: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX10-UNALIGNED: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX10-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -6000,17 +5324,13 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -6028,17 +5348,13 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -6056,17 +5372,13 @@ body: |
; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-DS128: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-DS128: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -6084,17 +5396,13 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -6112,17 +5420,13 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -6144,17 +5448,13 @@ body: |
; GFX10: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
; GFX10: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX10: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -6172,17 +5472,13 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
; GFX10-UNALIGNED: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10-UNALIGNED: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX10-UNALIGNED: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -6228,31 +5524,27 @@ body: |
; SI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; SI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; SI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; SI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; SI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -6297,31 +5589,27 @@ body: |
; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -6366,31 +5654,27 @@ body: |
; CI-DS128: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI-DS128: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-DS128: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-DS128: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-DS128: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI-DS128: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-DS128: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI-DS128: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI-DS128: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI-DS128: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI-DS128: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI-DS128: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C9]]
+ ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
; CI-DS128: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI-DS128: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI-DS128: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -6714,10 +5998,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -6730,10 +6012,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -6746,10 +6026,8 @@ body: |
; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI-DS128: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; CI-DS128: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI-DS128: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -6762,10 +6040,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -6778,10 +6054,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -6798,10 +6072,8 @@ body: |
; GFX10: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX10: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX10: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX10: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -6814,10 +6086,8 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX10-UNALIGNED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX10-UNALIGNED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -6847,20 +6117,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -6879,20 +6145,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -6911,20 +6173,16 @@ body: |
; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-DS128: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI-DS128: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-DS128: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -6943,20 +6201,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -6975,20 +6229,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7011,20 +6261,16 @@ body: |
; GFX10: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7043,20 +6289,16 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10-UNALIGNED: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10-UNALIGNED: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10-UNALIGNED: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10-UNALIGNED: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7123,10 +6365,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -7139,10 +6379,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -7155,10 +6393,8 @@ body: |
; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI-DS128: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; CI-DS128: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI-DS128: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -7171,10 +6407,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -7187,10 +6421,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -7207,10 +6439,8 @@ body: |
; GFX10: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX10: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX10: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX10: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -7223,10 +6453,8 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX10-UNALIGNED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX10-UNALIGNED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -7256,20 +6484,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7288,20 +6512,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7320,20 +6540,16 @@ body: |
; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-DS128: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI-DS128: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-DS128: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7352,20 +6568,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7384,20 +6596,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7420,20 +6628,16 @@ body: |
; GFX10: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7452,20 +6656,16 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10-UNALIGNED: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10-UNALIGNED: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10-UNALIGNED: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10-UNALIGNED: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7496,8 +6696,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -7517,8 +6716,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -7538,8 +6736,7 @@ body: |
; CI-DS128: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI-DS128: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-DS128: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -7659,11 +6856,7 @@ body: |
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s8) from unknown-address + 1, addrspace 3)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32)
+ ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; CI-LABEL: name: test_load_local_v2s8_align1
; CI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
@@ -7671,11 +6864,7 @@ body: |
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s8) from unknown-address + 1, addrspace 3)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32)
+ ; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; CI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; CI-DS128-LABEL: name: test_load_local_v2s8_align1
; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
@@ -7683,11 +6872,7 @@ body: |
; CI-DS128: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI-DS128: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s8) from unknown-address + 1, addrspace 3)
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32)
+ ; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; CI-DS128: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; VI-LABEL: name: test_load_local_v2s8_align1
; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
@@ -7695,11 +6880,7 @@ body: |
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s8) from unknown-address + 1, addrspace 3)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32)
+ ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_load_local_v2s8_align1
; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
@@ -7707,9 +6888,7 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s8) from unknown-address + 1, addrspace 3)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2s8_align1
; GFX9-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
@@ -7720,9 +6899,7 @@ body: |
; GFX9-UNALIGNED: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX9-UNALIGNED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9-UNALIGNED: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX9-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LSHR]](s32)
; GFX9-UNALIGNED: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX10-LABEL: name: test_load_local_v2s8_align1
; GFX10: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
@@ -7730,9 +6907,7 @@ body: |
; GFX10: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX10: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX10: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s8) from unknown-address + 1, addrspace 3)
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; GFX10: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2s8_align1
; GFX10-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
@@ -7740,9 +6915,7 @@ body: |
; GFX10-UNALIGNED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX10-UNALIGNED: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s8) from unknown-address + 1, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX10-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; GFX10-UNALIGNED: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(p3) = COPY $vgpr0
%1:_(<2 x s8>) = G_LOAD %0 :: (load (<2 x s8>), align 1, addrspace 3)
@@ -7771,25 +6944,22 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; SI: $vgpr0 = COPY [[COPY5]](s32)
+ ; SI: $vgpr0 = COPY [[OR2]](s32)
; CI-LABEL: name: test_load_local_v3s8_align4
; CI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 1)
@@ -7805,25 +6975,22 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI: $vgpr0 = COPY [[COPY5]](s32)
+ ; CI: $vgpr0 = COPY [[OR2]](s32)
; CI-DS128-LABEL: name: test_load_local_v3s8_align4
; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 1)
@@ -7839,25 +7006,22 @@ body: |
; CI-DS128: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI-DS128: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-DS128: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-DS128: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; CI-DS128: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
- ; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
+ ; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI-DS128: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-DS128: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CI-DS128: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI-DS128: $vgpr0 = COPY [[COPY5]](s32)
+ ; CI-DS128: $vgpr0 = COPY [[OR2]](s32)
; VI-LABEL: name: test_load_local_v3s8_align4
; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 1)
@@ -7886,8 +7050,7 @@ body: |
; VI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[OR2]](s32)
; GFX9-LABEL: name: test_load_local_v3s8_align4
; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 1)
@@ -7916,8 +7079,7 @@ body: |
; GFX9: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[OR2]](s32)
; GFX9-UNALIGNED-LABEL: name: test_load_local_v3s8_align4
; GFX9-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 1)
@@ -7946,8 +7108,7 @@ body: |
; GFX9-UNALIGNED: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; GFX9-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX9-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-UNALIGNED: $vgpr0 = COPY [[OR2]](s32)
; GFX10-LABEL: name: test_load_local_v3s8_align4
; GFX10: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 1)
@@ -7976,8 +7137,7 @@ body: |
; GFX10: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX10: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX10: $vgpr0 = COPY [[OR2]](s32)
; GFX10-UNALIGNED-LABEL: name: test_load_local_v3s8_align4
; GFX10-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 1)
@@ -8006,8 +7166,7 @@ body: |
; GFX10-UNALIGNED: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX10-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX10-UNALIGNED: $vgpr0 = COPY [[OR2]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(<3 x s8>) = G_LOAD %0 :: (load (<3 x s8>), addrspace 1, align 4)
%2:_(s24) = G_BITCAST %1
@@ -8037,15 +7196,13 @@ body: |
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -8054,8 +7211,7 @@ body: |
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[OR2]](s32)
; CI-LABEL: name: test_load_local_v3s8_align1
; CI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
@@ -8072,15 +7228,13 @@ body: |
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -8089,8 +7243,7 @@ body: |
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI: $vgpr0 = COPY [[COPY4]](s32)
+ ; CI: $vgpr0 = COPY [[OR2]](s32)
; CI-DS128-LABEL: name: test_load_local_v3s8_align1
; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
@@ -8107,15 +7260,13 @@ body: |
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CI-DS128: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-DS128: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-DS128: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-DS128: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CI-DS128: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -8124,8 +7275,7 @@ body: |
; CI-DS128: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI-DS128: $vgpr0 = COPY [[COPY4]](s32)
+ ; CI-DS128: $vgpr0 = COPY [[OR2]](s32)
; VI-LABEL: name: test_load_local_v3s8_align1
; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
@@ -8155,8 +7305,7 @@ body: |
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[OR2]](s32)
; GFX9-LABEL: name: test_load_local_v3s8_align1
; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
@@ -8186,8 +7335,7 @@ body: |
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[OR2]](s32)
; GFX9-UNALIGNED-LABEL: name: test_load_local_v3s8_align1
; GFX9-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load (s16), align 1, addrspace 3)
@@ -8221,8 +7369,7 @@ body: |
; GFX9-UNALIGNED: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; GFX9-UNALIGNED: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX9-UNALIGNED: [[OR3:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL3]]
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
- ; GFX9-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9-UNALIGNED: $vgpr0 = COPY [[OR3]](s32)
; GFX10-LABEL: name: test_load_local_v3s8_align1
; GFX10: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
@@ -8252,8 +7399,7 @@ body: |
; GFX10: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX10: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX10: $vgpr0 = COPY [[OR2]](s32)
; GFX10-UNALIGNED-LABEL: name: test_load_local_v3s8_align1
; GFX10-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
@@ -8283,8 +7429,7 @@ body: |
; GFX10-UNALIGNED: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX10-UNALIGNED: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX10-UNALIGNED: $vgpr0 = COPY [[OR2]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(<3 x s8>) = G_LOAD %0 :: (load (<3 x s8>), align 1, addrspace 3)
%2:_(s24) = G_BITCAST %1
@@ -8308,18 +7453,14 @@ body: |
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; SI: $vgpr0 = COPY [[OR2]](s32)
@@ -8333,18 +7474,14 @@ body: |
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CI: $vgpr0 = COPY [[OR2]](s32)
@@ -8358,18 +7495,14 @@ body: |
; CI-DS128: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-DS128: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CI-DS128: $vgpr0 = COPY [[OR2]](s32)
@@ -8383,18 +7516,14 @@ body: |
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; VI: $vgpr0 = COPY [[OR2]](s32)
@@ -8408,18 +7537,14 @@ body: |
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; GFX9: $vgpr0 = COPY [[OR2]](s32)
@@ -8433,18 +7558,14 @@ body: |
; GFX9-UNALIGNED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9-UNALIGNED: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
; GFX9-UNALIGNED: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX9-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX9-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX9-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX9-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX9-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; GFX9-UNALIGNED: $vgpr0 = COPY [[OR2]](s32)
@@ -8458,18 +7579,14 @@ body: |
; GFX10: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
; GFX10: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; GFX10: $vgpr0 = COPY [[OR2]](s32)
@@ -8483,18 +7600,14 @@ body: |
; GFX10-UNALIGNED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10-UNALIGNED: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
; GFX10-UNALIGNED: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; GFX10-UNALIGNED: $vgpr0 = COPY [[OR2]](s32)
@@ -8524,32 +7637,24 @@ body: |
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -8568,32 +7673,24 @@ body: |
; CI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; CI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -8612,32 +7709,24 @@ body: |
; CI-DS128: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; CI-DS128: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; CI-DS128: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI-DS128: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-DS128: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; CI-DS128: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; CI-DS128: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-DS128: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; CI-DS128: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI-DS128: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -8656,32 +7745,24 @@ body: |
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -8700,32 +7781,24 @@ body: |
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -8744,32 +7817,24 @@ body: |
; GFX9-UNALIGNED: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; GFX9-UNALIGNED: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; GFX9-UNALIGNED: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX9-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX9-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX9-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX9-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX9-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX9-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; GFX9-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX9-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; GFX9-UNALIGNED: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX9-UNALIGNED: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9-UNALIGNED: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; GFX9-UNALIGNED: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; GFX9-UNALIGNED: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9-UNALIGNED: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; GFX9-UNALIGNED: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX9-UNALIGNED: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -8788,32 +7853,24 @@ body: |
; GFX10: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; GFX10: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; GFX10: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; GFX10: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX10: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; GFX10: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX10: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX10: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; GFX10: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; GFX10: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; GFX10: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX10: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -8832,32 +7889,24 @@ body: |
; GFX10-UNALIGNED: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; GFX10-UNALIGNED: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
; GFX10-UNALIGNED: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; GFX10-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; GFX10-UNALIGNED: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX10-UNALIGNED: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX10-UNALIGNED: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; GFX10-UNALIGNED: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; GFX10-UNALIGNED: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX10-UNALIGNED: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; GFX10-UNALIGNED: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX10-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -8913,62 +7962,46 @@ body: |
; SI: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; SI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C5]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C5]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C5]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C5]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C6]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C5]]
; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C7]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C5]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C5]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C5]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C5]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C5]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C6]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C5]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C5]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C7]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C5]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C5]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C5]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C5]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C5]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C5]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C6]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C5]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C5]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C7]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C5]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C5]]
+ ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C5]]
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C5]]
; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; SI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C5]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C5]]
; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C6]](s32)
; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C5]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C5]]
; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C7]](s32)
; SI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -9012,62 +8045,46 @@ body: |
; CI: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C5]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C5]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C5]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C5]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C6]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C5]]
; CI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C7]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C5]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C5]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C5]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C5]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C5]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C5]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C6]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C5]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C5]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C7]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C5]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C5]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C5]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C5]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C5]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C5]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C6]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C5]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C5]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C7]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C5]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C5]]
+ ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C5]]
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C5]]
; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C5]]
+ ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C5]]
; CI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C6]](s32)
; CI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C5]]
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C5]]
; CI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C7]](s32)
; CI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -9112,62 +8129,46 @@ body: |
; CI-DS128: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; CI-DS128: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
; CI-DS128: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C6]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C6]]
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C6]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C6]]
; CI-DS128: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C7]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C6]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C6]]
; CI-DS128: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C8]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C6]]
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C6]]
+ ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C6]]
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C6]]
; CI-DS128: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-DS128: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-DS128: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C6]]
+ ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C6]]
; CI-DS128: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C7]](s32)
; CI-DS128: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-DS128: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C6]]
+ ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C6]]
; CI-DS128: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI-DS128: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; CI-DS128: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI-DS128: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C6]]
- ; CI-DS128: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-DS128: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C6]]
+ ; CI-DS128: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C6]]
+ ; CI-DS128: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C6]]
; CI-DS128: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI-DS128: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI-DS128: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI-DS128: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C6]]
+ ; CI-DS128: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C6]]
; CI-DS128: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C7]](s32)
; CI-DS128: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI-DS128: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI-DS128: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C6]]
+ ; CI-DS128: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C6]]
; CI-DS128: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C8]](s32)
; CI-DS128: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; CI-DS128: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI-DS128: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C6]]
- ; CI-DS128: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI-DS128: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C6]]
+ ; CI-DS128: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C6]]
+ ; CI-DS128: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C6]]
; CI-DS128: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI-DS128: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI-DS128: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI-DS128: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C6]]
+ ; CI-DS128: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C6]]
; CI-DS128: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C7]](s32)
; CI-DS128: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI-DS128: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI-DS128: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C6]]
+ ; CI-DS128: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C6]]
; CI-DS128: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C8]](s32)
; CI-DS128: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -9212,62 +8213,46 @@ body: |
; VI: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; VI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C6]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C6]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C6]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C6]]
; VI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C7]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C6]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C6]]
; VI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C8]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C6]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C6]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C6]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C6]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C6]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C6]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C7]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C6]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C6]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C6]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C6]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C6]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C6]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C6]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C6]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C7]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C6]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C6]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C8]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C6]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C6]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C6]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C6]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C6]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C6]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C7]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C6]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C6]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C8]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -9312,62 +8297,46 @@ body: |
; GFX9: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX9: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C6]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C6]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C6]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C6]]
; GFX9: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C7]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C6]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C6]]
; GFX9: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C8]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C6]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C6]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C6]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C6]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C6]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C6]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C7]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C6]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C6]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C6]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C6]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C6]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C6]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C6]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C6]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C7]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C6]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C6]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C8]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C6]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C6]]
+ ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C6]]
+ ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C6]]
; GFX9: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX9: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C6]]
+ ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C6]]
; GFX9: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C7]](s32)
; GFX9: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C6]]
+ ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C6]]
; GFX9: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C8]](s32)
; GFX9: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -9392,60 +8361,44 @@ body: |
; GFX9-UNALIGNED: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; GFX9-UNALIGNED: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
; GFX9-UNALIGNED: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX9-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX9-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX9-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX9-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX9-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX9-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; GFX9-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX9-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; GFX9-UNALIGNED: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX9-UNALIGNED: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9-UNALIGNED: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; GFX9-UNALIGNED: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C1]](s32)
; GFX9-UNALIGNED: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9-UNALIGNED: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; GFX9-UNALIGNED: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX9-UNALIGNED: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; GFX9-UNALIGNED: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; GFX9-UNALIGNED: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9-UNALIGNED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9-UNALIGNED: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
; GFX9-UNALIGNED: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; GFX9-UNALIGNED: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9-UNALIGNED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX9-UNALIGNED: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C3]]
; GFX9-UNALIGNED: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s32)
; GFX9-UNALIGNED: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9-UNALIGNED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; GFX9-UNALIGNED: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C3]]
; GFX9-UNALIGNED: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; GFX9-UNALIGNED: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; GFX9-UNALIGNED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; GFX9-UNALIGNED: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9-UNALIGNED: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; GFX9-UNALIGNED: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND12:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
; GFX9-UNALIGNED: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C]](s32)
; GFX9-UNALIGNED: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9-UNALIGNED: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; GFX9-UNALIGNED: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C3]]
; GFX9-UNALIGNED: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C1]](s32)
; GFX9-UNALIGNED: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9-UNALIGNED: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; GFX9-UNALIGNED: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9-UNALIGNED: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C3]]
; GFX9-UNALIGNED: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C2]](s32)
; GFX9-UNALIGNED: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -9490,62 +8443,46 @@ body: |
; GFX10: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX10: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
; GFX10: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C6]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C6]]
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C6]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C6]]
; GFX10: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C7]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C6]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C6]]
; GFX10: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C8]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; GFX10: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C6]]
- ; GFX10: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C6]]
+ ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C6]]
+ ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C6]]
; GFX10: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX10: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX10: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C6]]
+ ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C6]]
; GFX10: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C7]](s32)
; GFX10: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C6]]
+ ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C6]]
; GFX10: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; GFX10: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX10: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C6]]
- ; GFX10: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX10: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C6]]
+ ; GFX10: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C6]]
+ ; GFX10: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C6]]
; GFX10: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX10: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX10: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C6]]
+ ; GFX10: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C6]]
; GFX10: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C7]](s32)
; GFX10: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX10: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C6]]
+ ; GFX10: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C6]]
; GFX10: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C8]](s32)
; GFX10: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX10: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C6]]
- ; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX10: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C6]]
+ ; GFX10: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C6]]
+ ; GFX10: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C6]]
; GFX10: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX10: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX10: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C6]]
+ ; GFX10: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C6]]
; GFX10: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C7]](s32)
; GFX10: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX10: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C6]]
+ ; GFX10: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C6]]
; GFX10: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C8]](s32)
; GFX10: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -9590,62 +8527,46 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
; GFX10-UNALIGNED: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C6]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C6]]
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C6]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C6]]
; GFX10-UNALIGNED: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C7]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C6]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C6]]
; GFX10-UNALIGNED: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C8]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; GFX10-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C6]]
- ; GFX10-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C6]]
+ ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C6]]
+ ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C6]]
; GFX10-UNALIGNED: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX10-UNALIGNED: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C6]]
+ ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C6]]
; GFX10-UNALIGNED: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C7]](s32)
; GFX10-UNALIGNED: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX10-UNALIGNED: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C6]]
+ ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C6]]
; GFX10-UNALIGNED: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; GFX10-UNALIGNED: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; GFX10-UNALIGNED: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX10-UNALIGNED: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C6]]
- ; GFX10-UNALIGNED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX10-UNALIGNED: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C6]]
+ ; GFX10-UNALIGNED: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C6]]
+ ; GFX10-UNALIGNED: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C6]]
; GFX10-UNALIGNED: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX10-UNALIGNED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX10-UNALIGNED: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C6]]
+ ; GFX10-UNALIGNED: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C6]]
; GFX10-UNALIGNED: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C7]](s32)
; GFX10-UNALIGNED: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX10-UNALIGNED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX10-UNALIGNED: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C6]]
+ ; GFX10-UNALIGNED: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C6]]
; GFX10-UNALIGNED: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C8]](s32)
; GFX10-UNALIGNED: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; GFX10-UNALIGNED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX10-UNALIGNED: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C6]]
- ; GFX10-UNALIGNED: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX10-UNALIGNED: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C6]]
+ ; GFX10-UNALIGNED: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C6]]
+ ; GFX10-UNALIGNED: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C6]]
; GFX10-UNALIGNED: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX10-UNALIGNED: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX10-UNALIGNED: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C6]]
+ ; GFX10-UNALIGNED: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C6]]
; GFX10-UNALIGNED: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C7]](s32)
; GFX10-UNALIGNED: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX10-UNALIGNED: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX10-UNALIGNED: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C6]]
+ ; GFX10-UNALIGNED: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C6]]
; GFX10-UNALIGNED: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C8]](s32)
; GFX10-UNALIGNED: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX10-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -9712,10 +8633,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -9728,10 +8647,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -9744,10 +8661,8 @@ body: |
; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI-DS128: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; CI-DS128: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI-DS128: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -9760,10 +8675,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -9775,9 +8688,7 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2s16_align2
; GFX9-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
@@ -9789,9 +8700,7 @@ body: |
; GFX10: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; GFX10: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX10: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
; GFX10: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2s16_align2
; GFX10-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
@@ -9799,9 +8708,7 @@ body: |
; GFX10-UNALIGNED: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; GFX10-UNALIGNED: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
; GFX10-UNALIGNED: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(p3) = COPY $vgpr0
%1:_(<2 x s16>) = G_LOAD %0 :: (load (<2 x s16>), align 2, addrspace 3)
@@ -9825,8 +8732,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -9837,10 +8743,9 @@ body: |
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -9861,8 +8766,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -9873,10 +8777,9 @@ body: |
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -9897,8 +8800,7 @@ body: |
; CI-DS128: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI-DS128: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-DS128: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -9909,10 +8811,9 @@ body: |
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI-DS128: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-DS128: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; CI-DS128: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-DS128: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -10073,24 +8974,18 @@ body: |
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -10113,24 +9008,18 @@ body: |
; CI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; CI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -10153,24 +9042,18 @@ body: |
; CI-DS128: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; CI-DS128: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CI-DS128: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-DS128: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-DS128: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-DS128: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -10193,24 +9076,18 @@ body: |
; VI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -10232,15 +9109,9 @@ body: |
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[BITCAST2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[BITCAST3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; GFX9-UNALIGNED-LABEL: name: test_load_local_v3s16_align8
@@ -10259,15 +9130,9 @@ body: |
; GFX9-UNALIGNED: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9-UNALIGNED: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX9-UNALIGNED: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-UNALIGNED: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9-UNALIGNED: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9-UNALIGNED: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9-UNALIGNED: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
+ ; GFX9-UNALIGNED: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[BITCAST2]](s32)
+ ; GFX9-UNALIGNED: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[BITCAST3]](s32)
; GFX9-UNALIGNED: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9-UNALIGNED: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; GFX10-LABEL: name: test_load_local_v3s16_align8
@@ -10286,15 +9151,9 @@ body: |
; GFX10: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX10: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX10: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX10: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX10: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[BITCAST2]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[BITCAST3]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX10: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; GFX10-UNALIGNED-LABEL: name: test_load_local_v3s16_align8
@@ -10313,15 +9172,9 @@ body: |
; GFX10-UNALIGNED: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX10-UNALIGNED: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX10-UNALIGNED: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX10-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX10-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
+ ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[BITCAST2]](s32)
+ ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[BITCAST3]](s32)
; GFX10-UNALIGNED: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX10-UNALIGNED: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(p3) = COPY $vgpr0
@@ -10357,24 +9210,18 @@ body: |
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -10400,24 +9247,18 @@ body: |
; CI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -10443,24 +9284,18 @@ body: |
; CI-DS128: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CI-DS128: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-DS128: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-DS128: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-DS128: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -10486,24 +9321,18 @@ body: |
; VI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -10528,15 +9357,9 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C2]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[BITCAST]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; GFX9-UNALIGNED-LABEL: name: test_load_local_v3s16_align2
@@ -10558,15 +9381,9 @@ body: |
; GFX9-UNALIGNED: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C2]](s32)
; GFX9-UNALIGNED: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9-UNALIGNED: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-UNALIGNED: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-UNALIGNED: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9-UNALIGNED: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9-UNALIGNED: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-UNALIGNED: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[BITCAST]](s32)
+ ; GFX9-UNALIGNED: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9-UNALIGNED: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9-UNALIGNED: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; GFX10-LABEL: name: test_load_local_v3s16_align2
@@ -10588,15 +9405,9 @@ body: |
; GFX10: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C2]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX10: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX10: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[BITCAST]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX10: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; GFX10-UNALIGNED-LABEL: name: test_load_local_v3s16_align2
@@ -10618,15 +9429,9 @@ body: |
; GFX10-UNALIGNED: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C2]](s32)
; GFX10-UNALIGNED: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX10-UNALIGNED: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX10-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[BITCAST]](s32)
+ ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX10-UNALIGNED: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX10-UNALIGNED: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(p3) = COPY $vgpr0
@@ -10653,8 +9458,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -10665,10 +9469,9 @@ body: |
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
@@ -10678,10 +9481,9 @@ body: |
; SI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s8) from unknown-address + 5, addrspace 3)
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; SI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; SI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
@@ -10701,15 +9503,12 @@ body: |
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C7]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C6]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; SI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C7]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C7]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL5]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
@@ -10726,8 +9525,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -10738,10 +9536,9 @@ body: |
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
@@ -10751,10 +9548,9 @@ body: |
; CI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s8) from unknown-address + 5, addrspace 3)
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
@@ -10774,15 +9570,12 @@ body: |
; CI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; CI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; CI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C7]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C6]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; CI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C7]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C7]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL5]]
; CI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
@@ -10799,8 +9592,7 @@ body: |
; CI-DS128: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI-DS128: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-DS128: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -10811,10 +9603,9 @@ body: |
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI-DS128: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-DS128: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; CI-DS128: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-DS128: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
@@ -10824,10 +9615,9 @@ body: |
; CI-DS128: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s8) from unknown-address + 5, addrspace 3)
; CI-DS128: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI-DS128: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; CI-DS128: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI-DS128: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
@@ -10847,15 +9637,12 @@ body: |
; CI-DS128: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; CI-DS128: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; CI-DS128: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
+ ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C7]]
; CI-DS128: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C6]](s32)
; CI-DS128: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; CI-DS128: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; CI-DS128: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; CI-DS128: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI-DS128: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
+ ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C7]]
+ ; CI-DS128: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C7]]
; CI-DS128: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C6]](s32)
; CI-DS128: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL5]]
; CI-DS128: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
@@ -10914,15 +9701,12 @@ body: |
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C6]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C6]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C6]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C6]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C5]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL5]]
; VI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
@@ -10978,11 +9762,8 @@ body: |
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[OR1]](s16)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX9: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[OR2]](s16)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[COPY1]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[BITCAST]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; GFX9-UNALIGNED-LABEL: name: test_load_local_v3s16_align1
@@ -11004,15 +9785,9 @@ body: |
; GFX9-UNALIGNED: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C2]](s32)
; GFX9-UNALIGNED: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9-UNALIGNED: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
- ; GFX9-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9-UNALIGNED: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9-UNALIGNED: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9-UNALIGNED: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9-UNALIGNED: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9-UNALIGNED: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[BITCAST]](s32)
+ ; GFX9-UNALIGNED: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9-UNALIGNED: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9-UNALIGNED: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; GFX10-LABEL: name: test_load_local_v3s16_align1
@@ -11065,11 +9840,8 @@ body: |
; GFX10: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[OR1]](s16)
; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX10: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[OR2]](s16)
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[COPY1]](s32)
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[BITCAST]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX10: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; GFX10-UNALIGNED-LABEL: name: test_load_local_v3s16_align1
@@ -11122,11 +9894,8 @@ body: |
; GFX10-UNALIGNED: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[OR1]](s16)
; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX10-UNALIGNED: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[OR2]](s16)
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[COPY1]](s32)
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[BITCAST]](s32)
+ ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX10-UNALIGNED: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX10-UNALIGNED: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(p3) = COPY $vgpr0
@@ -11239,18 +10008,14 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -11269,18 +10034,14 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -11299,18 +10060,14 @@ body: |
; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-DS128: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI-DS128: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-DS128: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -11329,18 +10086,14 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C4]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -11358,12 +10111,8 @@ body: |
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
; GFX9-UNALIGNED-LABEL: name: test_load_local_v4s16_align2
@@ -11382,12 +10131,8 @@ body: |
; GFX10: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
; GFX10: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX10: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
; GFX10-UNALIGNED-LABEL: name: test_load_local_v4s16_align2
@@ -11402,12 +10147,8 @@ body: |
; GFX10-UNALIGNED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
; GFX10-UNALIGNED: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX10-UNALIGNED: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
; GFX10-UNALIGNED: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX10-UNALIGNED: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
%0:_(p3) = COPY $vgpr0
@@ -11432,8 +10173,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -11444,10 +10184,9 @@ body: |
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -11463,10 +10202,9 @@ body: |
; SI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s8) from unknown-address + 5, addrspace 3)
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; SI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; SI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; SI: [[PTR_ADD5:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s32)
@@ -11475,10 +10213,9 @@ body: |
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; SI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY6]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
+ ; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY3]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; SI: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
@@ -11499,8 +10236,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -11511,10 +10247,9 @@ body: |
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -11530,10 +10265,9 @@ body: |
; CI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s8) from unknown-address + 5, addrspace 3)
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[PTR_ADD5:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s32)
@@ -11542,10 +10276,9 @@ body: |
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
; CI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C1]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY6]](s32)
+ ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
+ ; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY3]](s32)
; CI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; CI: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
; CI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
@@ -11566,8 +10299,7 @@ body: |
; CI-DS128: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI-DS128: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-DS128: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -11578,10 +10310,9 @@ body: |
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI-DS128: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-DS128: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; CI-DS128: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-DS128: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -11597,10 +10328,9 @@ body: |
; CI-DS128: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s8) from unknown-address + 5, addrspace 3)
; CI-DS128: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI-DS128: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-DS128: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; CI-DS128: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; CI-DS128: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI-DS128: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI-DS128: [[PTR_ADD5:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s32)
@@ -11609,10 +10339,9 @@ body: |
; CI-DS128: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
; CI-DS128: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI-DS128: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C1]]
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI-DS128: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; CI-DS128: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY6]](s32)
+ ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
+ ; CI-DS128: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY3]](s32)
; CI-DS128: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; CI-DS128: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
; CI-DS128: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
@@ -11951,10 +10680,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -11963,10 +10690,8 @@ body: |
; SI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -11978,10 +10703,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -11990,10 +10713,8 @@ body: |
; CI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; CI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -12005,10 +10726,8 @@ body: |
; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI-DS128: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; CI-DS128: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI-DS128: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -12017,10 +10736,8 @@ body: |
; CI-DS128: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -12032,10 +10749,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -12044,10 +10759,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -12059,10 +10772,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -12071,10 +10782,8 @@ body: |
; GFX9: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -12090,10 +10799,8 @@ body: |
; GFX10: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX10: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX10: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX10: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -12102,10 +10809,8 @@ body: |
; GFX10: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; GFX10: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX10: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -12117,10 +10822,8 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX10-UNALIGNED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX10-UNALIGNED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -12129,10 +10832,8 @@ body: |
; GFX10-UNALIGNED: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX10-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -12161,20 +10862,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -12187,18 +10884,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -12216,20 +10909,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -12242,18 +10931,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -12271,20 +10956,16 @@ body: |
; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-DS128: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI-DS128: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-DS128: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -12297,18 +10978,14 @@ body: |
; CI-DS128: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; CI-DS128: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI-DS128: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI-DS128: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-DS128: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-DS128: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI-DS128: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI-DS128: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-DS128: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI-DS128: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-DS128: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -12326,20 +11003,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -12352,18 +11025,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -12381,20 +11050,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -12407,18 +11072,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -12440,20 +11101,16 @@ body: |
; GFX10: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -12466,18 +11123,14 @@ body: |
; GFX10: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX10: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX10: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX10: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX10: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX10: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX10: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX10: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX10: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX10: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX10: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX10: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -12495,20 +11148,16 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10-UNALIGNED: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10-UNALIGNED: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10-UNALIGNED: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10-UNALIGNED: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -12521,18 +11170,14 @@ body: |
; GFX10-UNALIGNED: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX10-UNALIGNED: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX10-UNALIGNED: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX10-UNALIGNED: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX10-UNALIGNED: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX10-UNALIGNED: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX10-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -12561,20 +11206,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -12587,18 +11228,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -12609,18 +11246,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -12638,20 +11271,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -12664,18 +11293,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -12686,18 +11311,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -12715,20 +11336,16 @@ body: |
; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-DS128: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI-DS128: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-DS128: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -12741,18 +11358,14 @@ body: |
; CI-DS128: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; CI-DS128: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI-DS128: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI-DS128: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-DS128: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-DS128: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI-DS128: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI-DS128: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-DS128: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI-DS128: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-DS128: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI-DS128: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -12763,18 +11376,14 @@ body: |
; CI-DS128: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; CI-DS128: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI-DS128: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; CI-DS128: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI-DS128: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI-DS128: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-DS128: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI-DS128: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI-DS128: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI-DS128: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI-DS128: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI-DS128: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI-DS128: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI-DS128: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI-DS128: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI-DS128: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI-DS128: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI-DS128: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI-DS128: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI-DS128: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI-DS128: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -12792,20 +11401,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -12818,18 +11423,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -12840,18 +11441,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -12869,20 +11466,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -12895,18 +11488,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -12917,18 +11506,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -12950,20 +11535,16 @@ body: |
; GFX10: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -12976,18 +11557,14 @@ body: |
; GFX10: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX10: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX10: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX10: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX10: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX10: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX10: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX10: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX10: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX10: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX10: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX10: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX10: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -12998,18 +11575,14 @@ body: |
; GFX10: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX10: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX10: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX10: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX10: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX10: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX10: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX10: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX10: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX10: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX10: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX10: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX10: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX10: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX10: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX10: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX10: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX10: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -13027,20 +11600,16 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10-UNALIGNED: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10-UNALIGNED: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10-UNALIGNED: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10-UNALIGNED: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -13053,18 +11622,14 @@ body: |
; GFX10-UNALIGNED: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX10-UNALIGNED: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX10-UNALIGNED: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX10-UNALIGNED: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX10-UNALIGNED: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX10-UNALIGNED: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX10-UNALIGNED: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -13075,18 +11640,14 @@ body: |
; GFX10-UNALIGNED: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX10-UNALIGNED: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX10-UNALIGNED: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX10-UNALIGNED: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX10-UNALIGNED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX10-UNALIGNED: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX10-UNALIGNED: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX10-UNALIGNED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX10-UNALIGNED: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX10-UNALIGNED: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX10-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -13390,10 +11951,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -13402,10 +11961,8 @@ body: |
; SI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -13414,20 +11971,16 @@ body: |
; SI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; SI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[PTR_ADD5:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s32)
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR3]](s32)
@@ -13440,10 +11993,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -13452,10 +12003,8 @@ body: |
; CI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; CI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -13464,20 +12013,16 @@ body: |
; CI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; CI: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; CI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[PTR_ADD5:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s32)
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR3]](s32)
@@ -13490,10 +12035,8 @@ body: |
; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI-DS128: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; CI-DS128: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI-DS128: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -13502,10 +12045,8 @@ body: |
; CI-DS128: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -13514,20 +12055,16 @@ body: |
; CI-DS128: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; CI-DS128: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; CI-DS128: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-DS128: [[PTR_ADD5:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s32)
; CI-DS128: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; CI-DS128: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; CI-DS128: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; CI-DS128: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; CI-DS128: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; CI-DS128: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI-DS128: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI-DS128: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR3]](s32)
@@ -13540,10 +12077,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -13552,10 +12087,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -13564,20 +12097,16 @@ body: |
; VI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; VI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[PTR_ADD5:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s32)
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; VI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR3]](s32)
@@ -13590,10 +12119,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -13602,10 +12129,8 @@ body: |
; GFX9: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -13614,20 +12139,16 @@ body: |
; GFX9: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; GFX9: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; GFX9: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX9: [[PTR_ADD5:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s32)
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR3]](s32)
@@ -13644,10 +12165,8 @@ body: |
; GFX10: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX10: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX10: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX10: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -13656,10 +12175,8 @@ body: |
; GFX10: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; GFX10: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX10: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -13668,20 +12185,16 @@ body: |
; GFX10: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; GFX10: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; GFX10: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; GFX10: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX10: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX10: [[PTR_ADD5:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s32)
; GFX10: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; GFX10: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; GFX10: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; GFX10: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; GFX10: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX10: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX10: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR3]](s32)
@@ -13694,10 +12207,8 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX10-UNALIGNED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX10-UNALIGNED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -13706,10 +12217,8 @@ body: |
; GFX10-UNALIGNED: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX10-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -13718,20 +12227,16 @@ body: |
; GFX10-UNALIGNED: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX10-UNALIGNED: [[PTR_ADD5:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s32)
; GFX10-UNALIGNED: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; GFX10-UNALIGNED: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX10-UNALIGNED: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR3]](s32)
@@ -13761,20 +12266,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -13787,18 +12288,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -13810,18 +12307,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[PTR_ADD11:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C7]](s32)
@@ -13832,18 +12325,14 @@ body: |
; SI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; SI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; SI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; SI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR8]](s32), [[OR11]](s32)
@@ -13862,20 +12351,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -13888,18 +12373,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -13911,18 +12392,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[PTR_ADD11:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C7]](s32)
@@ -13933,18 +12410,14 @@ body: |
; CI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; CI: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR8]](s32), [[OR11]](s32)
@@ -13963,20 +12436,16 @@ body: |
; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-DS128: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI-DS128: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-DS128: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -13989,18 +12458,14 @@ body: |
; CI-DS128: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; CI-DS128: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI-DS128: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI-DS128: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-DS128: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-DS128: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI-DS128: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI-DS128: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-DS128: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI-DS128: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-DS128: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI-DS128: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -14011,18 +12476,14 @@ body: |
; CI-DS128: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; CI-DS128: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI-DS128: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; CI-DS128: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI-DS128: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI-DS128: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-DS128: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI-DS128: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI-DS128: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI-DS128: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI-DS128: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI-DS128: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI-DS128: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI-DS128: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI-DS128: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI-DS128: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI-DS128: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI-DS128: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI-DS128: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI-DS128: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI-DS128: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI-DS128: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -14034,18 +12495,14 @@ body: |
; CI-DS128: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; CI-DS128: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; CI-DS128: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; CI-DS128: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI-DS128: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI-DS128: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI-DS128: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI-DS128: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI-DS128: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI-DS128: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI-DS128: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI-DS128: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI-DS128: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI-DS128: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI-DS128: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI-DS128: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI-DS128: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI-DS128: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI-DS128: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI-DS128: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI-DS128: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -14063,20 +12520,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -14089,18 +12542,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -14111,18 +12560,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -14134,18 +12579,14 @@ body: |
; VI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; VI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -14163,20 +12604,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -14189,18 +12626,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -14211,18 +12644,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -14234,18 +12663,14 @@ body: |
; GFX9: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; GFX9: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX9: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX9: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX9: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX9: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX9: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX9: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX9: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -14267,20 +12692,16 @@ body: |
; GFX10: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -14293,18 +12714,14 @@ body: |
; GFX10: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX10: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX10: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX10: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX10: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX10: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX10: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX10: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX10: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX10: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX10: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX10: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX10: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -14315,18 +12732,14 @@ body: |
; GFX10: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX10: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX10: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX10: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX10: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX10: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX10: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX10: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX10: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX10: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX10: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX10: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX10: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX10: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX10: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX10: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX10: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX10: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX10: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -14338,18 +12751,14 @@ body: |
; GFX10: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; GFX10: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX10: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX10: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX10: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX10: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX10: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX10: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX10: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX10: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX10: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX10: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX10: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX10: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX10: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX10: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX10: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -14367,20 +12776,16 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10-UNALIGNED: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10-UNALIGNED: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10-UNALIGNED: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10-UNALIGNED: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -14393,18 +12798,14 @@ body: |
; GFX10-UNALIGNED: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX10-UNALIGNED: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX10-UNALIGNED: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX10-UNALIGNED: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX10-UNALIGNED: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX10-UNALIGNED: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX10-UNALIGNED: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -14415,18 +12816,14 @@ body: |
; GFX10-UNALIGNED: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX10-UNALIGNED: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX10-UNALIGNED: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX10-UNALIGNED: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX10-UNALIGNED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX10-UNALIGNED: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX10-UNALIGNED: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX10-UNALIGNED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX10-UNALIGNED: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX10-UNALIGNED: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX10-UNALIGNED: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -14438,18 +12835,14 @@ body: |
; GFX10-UNALIGNED: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX10-UNALIGNED: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX10-UNALIGNED: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX10-UNALIGNED: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX10-UNALIGNED: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX10-UNALIGNED: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX10-UNALIGNED: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX10-UNALIGNED: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX10-UNALIGNED: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX10-UNALIGNED: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX10-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -14800,33 +13193,29 @@ body: |
; SI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; SI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; SI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; SI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C9]]
- ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY7]](s32)
+ ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
+ ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY4]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; SI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -14857,34 +13246,30 @@ body: |
; SI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
; SI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD8]](s32)
; SI: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C7]]
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C9]]
- ; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY9]](s32)
+ ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C9]]
+ ; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY5]](s32)
; SI: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; SI: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
; SI: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD10]](s32)
; SI: [[AND10:%[0-9]+]]:_(s16) = G_AND [[TRUNC10]], [[C7]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C9]]
- ; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY11]](s32)
+ ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C9]]
+ ; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY6]](s32)
; SI: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL7]](s32)
; SI: [[OR7:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC11]]
; SI: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD12]](s32)
; SI: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC12]], [[C7]]
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C9]]
- ; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY13]](s32)
+ ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C9]]
+ ; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY7]](s32)
; SI: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
; SI: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[TRUNC13]]
; SI: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD14]](s32)
; SI: [[AND14:%[0-9]+]]:_(s16) = G_AND [[TRUNC14]], [[C7]]
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C9]]
- ; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY15]](s32)
+ ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C9]]
+ ; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY8]](s32)
; SI: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[SHL9]](s32)
; SI: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[TRUNC15]]
; SI: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
@@ -14928,33 +13313,29 @@ body: |
; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C9]]
- ; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY7]](s32)
+ ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
+ ; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY4]](s32)
; CI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
; CI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -14985,34 +13366,30 @@ body: |
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
; CI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD8]](s32)
; CI: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C7]]
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C9]]
- ; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY9]](s32)
+ ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C9]]
+ ; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY5]](s32)
; CI: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; CI: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
; CI: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD10]](s32)
; CI: [[AND10:%[0-9]+]]:_(s16) = G_AND [[TRUNC10]], [[C7]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C9]]
- ; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY11]](s32)
+ ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C9]]
+ ; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY6]](s32)
; CI: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL7]](s32)
; CI: [[OR7:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC11]]
; CI: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD12]](s32)
; CI: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC12]], [[C7]]
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C9]]
- ; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY13]](s32)
+ ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C9]]
+ ; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY7]](s32)
; CI: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
; CI: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[TRUNC13]]
; CI: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD14]](s32)
; CI: [[AND14:%[0-9]+]]:_(s16) = G_AND [[TRUNC14]], [[C7]]
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C9]]
- ; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY15]](s32)
+ ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C9]]
+ ; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY8]](s32)
; CI: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[SHL9]](s32)
; CI: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[TRUNC15]]
; CI: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
@@ -15056,33 +13433,29 @@ body: |
; CI-DS128: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; CI-DS128: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C9]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C9]]
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI-DS128: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI-DS128: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI-DS128: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C7]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C9]]
- ; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C9]]
+ ; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI-DS128: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI-DS128: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI-DS128: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C7]]
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C9]]
- ; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY5]](s32)
+ ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C9]]
+ ; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY3]](s32)
; CI-DS128: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI-DS128: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI-DS128: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C7]]
- ; CI-DS128: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-DS128: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C9]]
- ; CI-DS128: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY7]](s32)
+ ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C9]]
+ ; CI-DS128: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY4]](s32)
; CI-DS128: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI-DS128: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
; CI-DS128: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -15113,34 +13486,30 @@ body: |
; CI-DS128: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
; CI-DS128: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD8]](s32)
; CI-DS128: [[AND8:%[0-9]+]]:_(s16) = G_AND [[TRUNC8]], [[C7]]
- ; CI-DS128: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-DS128: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-DS128: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C9]]
- ; CI-DS128: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY9]](s32)
+ ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-DS128: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C9]]
+ ; CI-DS128: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY5]](s32)
; CI-DS128: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; CI-DS128: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC9]]
; CI-DS128: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD10]](s32)
; CI-DS128: [[AND10:%[0-9]+]]:_(s16) = G_AND [[TRUNC10]], [[C7]]
- ; CI-DS128: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-DS128: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI-DS128: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C9]]
- ; CI-DS128: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY11]](s32)
+ ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-DS128: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C9]]
+ ; CI-DS128: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY6]](s32)
; CI-DS128: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL7]](s32)
; CI-DS128: [[OR7:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC11]]
; CI-DS128: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD12]](s32)
; CI-DS128: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC12]], [[C7]]
- ; CI-DS128: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-DS128: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI-DS128: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C9]]
- ; CI-DS128: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY13]](s32)
+ ; CI-DS128: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-DS128: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C9]]
+ ; CI-DS128: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[COPY7]](s32)
; CI-DS128: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
; CI-DS128: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[TRUNC13]]
; CI-DS128: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD14]](s32)
; CI-DS128: [[AND14:%[0-9]+]]:_(s16) = G_AND [[TRUNC14]], [[C7]]
- ; CI-DS128: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CI-DS128: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI-DS128: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C9]]
- ; CI-DS128: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY15]](s32)
+ ; CI-DS128: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CI-DS128: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C9]]
+ ; CI-DS128: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[COPY8]](s32)
; CI-DS128: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[SHL9]](s32)
; CI-DS128: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[TRUNC15]]
; CI-DS128: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
@@ -16606,20 +14975,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -16632,18 +14997,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -16654,18 +15015,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -16679,18 +15036,14 @@ body: |
; SI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; SI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; SI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; SI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; SI: [[PTR_ADD15:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C7]](s32)
@@ -16701,18 +15054,14 @@ body: |
; SI: [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD17]](p3) :: (load (s8) from unknown-address + 18, addrspace 3)
; SI: [[PTR_ADD18:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD15]], [[C2]](s32)
; SI: [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD18]](p3) :: (load (s8) from unknown-address + 19, addrspace 3)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD16]](s32)
- ; SI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; SI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; SI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LOAD16]], [[C3]]
+ ; SI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C3]]
; SI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; SI: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD18]](s32)
- ; SI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; SI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LOAD18]], [[C3]]
; SI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C5]](s32)
; SI: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; SI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; SI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C3]]
; SI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C6]](s32)
; SI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; SI: [[PTR_ADD19:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s32)
@@ -16723,26 +15072,22 @@ body: |
; SI: [[LOAD22:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD21]](p3) :: (load (s8) from unknown-address + 22, addrspace 3)
; SI: [[PTR_ADD22:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD19]], [[C2]](s32)
; SI: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p3) :: (load (s8) from unknown-address + 23, addrspace 3)
- ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD20]](s32)
- ; SI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; SI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; SI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; SI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD20]], [[C3]]
+ ; SI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C3]]
; SI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C4]](s32)
; SI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; SI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD22]](s32)
- ; SI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; SI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD22]], [[C3]]
; SI: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C5]](s32)
; SI: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; SI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; SI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; SI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C3]]
; SI: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C6]](s32)
; SI: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR11]](s32), [[OR14]](s32), [[OR17]](s32)
; SI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; SI: [[COPY25:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; SI: [[COPY26:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; SI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY25]](s96)
- ; SI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY26]](s96)
+ ; SI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; SI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; SI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; SI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; CI-LABEL: name: test_load_local_v2s96_align1
; CI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
@@ -16756,20 +15101,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -16782,18 +15123,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -16804,18 +15141,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -16829,18 +15162,14 @@ body: |
; CI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; CI: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI: [[PTR_ADD15:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C7]](s32)
@@ -16851,18 +15180,14 @@ body: |
; CI: [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD17]](p3) :: (load (s8) from unknown-address + 18, addrspace 3)
; CI: [[PTR_ADD18:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD15]], [[C2]](s32)
; CI: [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD18]](p3) :: (load (s8) from unknown-address + 19, addrspace 3)
- ; CI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD16]](s32)
- ; CI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; CI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; CI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; CI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LOAD16]], [[C3]]
+ ; CI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C3]]
; CI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; CI: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; CI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD18]](s32)
- ; CI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; CI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LOAD18]], [[C3]]
; CI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C5]](s32)
; CI: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; CI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; CI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; CI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C3]]
; CI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C6]](s32)
; CI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; CI: [[PTR_ADD19:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s32)
@@ -16873,26 +15198,22 @@ body: |
; CI: [[LOAD22:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD21]](p3) :: (load (s8) from unknown-address + 22, addrspace 3)
; CI: [[PTR_ADD22:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD19]], [[C2]](s32)
; CI: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p3) :: (load (s8) from unknown-address + 23, addrspace 3)
- ; CI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD20]](s32)
- ; CI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; CI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; CI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; CI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD20]], [[C3]]
+ ; CI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C3]]
; CI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C4]](s32)
; CI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; CI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD22]](s32)
- ; CI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; CI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD22]], [[C3]]
; CI: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C5]](s32)
; CI: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; CI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; CI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; CI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C3]]
; CI: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C6]](s32)
; CI: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; CI: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR11]](s32), [[OR14]](s32), [[OR17]](s32)
; CI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; CI: [[COPY25:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; CI: [[COPY26:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; CI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY25]](s96)
- ; CI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY26]](s96)
+ ; CI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; CI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; CI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; CI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; CI-DS128-LABEL: name: test_load_local_v2s96_align1
; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
@@ -16906,20 +15227,16 @@ body: |
; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; CI-DS128: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI-DS128: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI-DS128: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI-DS128: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -16932,18 +15249,14 @@ body: |
; CI-DS128: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; CI-DS128: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI-DS128: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI-DS128: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI-DS128: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI-DS128: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI-DS128: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI-DS128: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI-DS128: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI-DS128: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI-DS128: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI-DS128: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -16954,18 +15267,14 @@ body: |
; CI-DS128: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; CI-DS128: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI-DS128: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; CI-DS128: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI-DS128: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI-DS128: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-DS128: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI-DS128: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI-DS128: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI-DS128: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI-DS128: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI-DS128: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI-DS128: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI-DS128: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI-DS128: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI-DS128: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI-DS128: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI-DS128: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI-DS128: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI-DS128: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI-DS128: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -16979,18 +15288,14 @@ body: |
; CI-DS128: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; CI-DS128: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; CI-DS128: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; CI-DS128: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI-DS128: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI-DS128: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI-DS128: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI-DS128: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI-DS128: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI-DS128: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI-DS128: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI-DS128: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI-DS128: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI-DS128: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI-DS128: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI-DS128: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI-DS128: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI-DS128: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI-DS128: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI-DS128: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI-DS128: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI-DS128: [[PTR_ADD15:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C7]](s32)
@@ -17001,18 +15306,14 @@ body: |
; CI-DS128: [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD17]](p3) :: (load (s8) from unknown-address + 18, addrspace 3)
; CI-DS128: [[PTR_ADD18:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD15]], [[C2]](s32)
; CI-DS128: [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD18]](p3) :: (load (s8) from unknown-address + 19, addrspace 3)
- ; CI-DS128: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD16]](s32)
- ; CI-DS128: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; CI-DS128: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; CI-DS128: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; CI-DS128: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LOAD16]], [[C3]]
+ ; CI-DS128: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C3]]
; CI-DS128: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; CI-DS128: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; CI-DS128: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD18]](s32)
- ; CI-DS128: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; CI-DS128: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LOAD18]], [[C3]]
; CI-DS128: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C5]](s32)
; CI-DS128: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; CI-DS128: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; CI-DS128: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; CI-DS128: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C3]]
; CI-DS128: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C6]](s32)
; CI-DS128: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; CI-DS128: [[PTR_ADD19:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s32)
@@ -17023,26 +15324,22 @@ body: |
; CI-DS128: [[LOAD22:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD21]](p3) :: (load (s8) from unknown-address + 22, addrspace 3)
; CI-DS128: [[PTR_ADD22:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD19]], [[C2]](s32)
; CI-DS128: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p3) :: (load (s8) from unknown-address + 23, addrspace 3)
- ; CI-DS128: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD20]](s32)
- ; CI-DS128: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; CI-DS128: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; CI-DS128: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; CI-DS128: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD20]], [[C3]]
+ ; CI-DS128: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C3]]
; CI-DS128: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C4]](s32)
; CI-DS128: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; CI-DS128: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD22]](s32)
- ; CI-DS128: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; CI-DS128: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD22]], [[C3]]
; CI-DS128: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C5]](s32)
; CI-DS128: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; CI-DS128: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; CI-DS128: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; CI-DS128: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C3]]
; CI-DS128: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C6]](s32)
; CI-DS128: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; CI-DS128: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR11]](s32), [[OR14]](s32), [[OR17]](s32)
; CI-DS128: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; CI-DS128: [[COPY25:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; CI-DS128: [[COPY26:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; CI-DS128: $vgpr0_vgpr1_vgpr2 = COPY [[COPY25]](s96)
- ; CI-DS128: $vgpr3_vgpr4_vgpr5 = COPY [[COPY26]](s96)
+ ; CI-DS128: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; CI-DS128: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; CI-DS128: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; CI-DS128: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; VI-LABEL: name: test_load_local_v2s96_align1
; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
@@ -17056,20 +15353,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -17082,18 +15375,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -17104,18 +15393,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -17129,18 +15414,14 @@ body: |
; VI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; VI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[PTR_ADD15:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C7]](s32)
@@ -17151,18 +15432,14 @@ body: |
; VI: [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD17]](p3) :: (load (s8) from unknown-address + 18, addrspace 3)
; VI: [[PTR_ADD18:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD15]], [[C2]](s32)
; VI: [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD18]](p3) :: (load (s8) from unknown-address + 19, addrspace 3)
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD16]](s32)
- ; VI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; VI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; VI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; VI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LOAD16]], [[C3]]
+ ; VI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C3]]
; VI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; VI: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; VI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD18]](s32)
- ; VI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; VI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LOAD18]], [[C3]]
; VI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C5]](s32)
; VI: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; VI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; VI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; VI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C3]]
; VI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C6]](s32)
; VI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; VI: [[PTR_ADD19:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s32)
@@ -17173,26 +15450,22 @@ body: |
; VI: [[LOAD22:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD21]](p3) :: (load (s8) from unknown-address + 22, addrspace 3)
; VI: [[PTR_ADD22:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD19]], [[C2]](s32)
; VI: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p3) :: (load (s8) from unknown-address + 23, addrspace 3)
- ; VI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD20]](s32)
- ; VI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; VI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; VI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; VI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD20]], [[C3]]
+ ; VI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C3]]
; VI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C4]](s32)
; VI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; VI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD22]](s32)
- ; VI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; VI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD22]], [[C3]]
; VI: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C5]](s32)
; VI: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; VI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; VI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; VI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C3]]
; VI: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C6]](s32)
; VI: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; VI: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR11]](s32), [[OR14]](s32), [[OR17]](s32)
; VI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; VI: [[COPY25:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; VI: [[COPY26:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY25]](s96)
- ; VI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY26]](s96)
+ ; VI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; VI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; VI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; GFX9-LABEL: name: test_load_local_v2s96_align1
; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
@@ -17206,20 +15479,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -17232,18 +15501,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -17254,18 +15519,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -17279,18 +15540,14 @@ body: |
; GFX9: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; GFX9: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX9: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX9: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX9: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX9: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX9: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX9: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX9: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9: [[PTR_ADD15:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C7]](s32)
@@ -17301,18 +15558,14 @@ body: |
; GFX9: [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD17]](p3) :: (load (s8) from unknown-address + 18, addrspace 3)
; GFX9: [[PTR_ADD18:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD15]], [[C2]](s32)
; GFX9: [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD18]](p3) :: (load (s8) from unknown-address + 19, addrspace 3)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD16]](s32)
- ; GFX9: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; GFX9: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; GFX9: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LOAD16]], [[C3]]
+ ; GFX9: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C3]]
; GFX9: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; GFX9: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD18]](s32)
- ; GFX9: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; GFX9: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LOAD18]], [[C3]]
; GFX9: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C5]](s32)
; GFX9: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; GFX9: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; GFX9: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C3]]
; GFX9: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C6]](s32)
; GFX9: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; GFX9: [[PTR_ADD19:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s32)
@@ -17323,26 +15576,22 @@ body: |
; GFX9: [[LOAD22:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD21]](p3) :: (load (s8) from unknown-address + 22, addrspace 3)
; GFX9: [[PTR_ADD22:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD19]], [[C2]](s32)
; GFX9: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p3) :: (load (s8) from unknown-address + 23, addrspace 3)
- ; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD20]](s32)
- ; GFX9: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; GFX9: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; GFX9: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD20]], [[C3]]
+ ; GFX9: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C3]]
; GFX9: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C4]](s32)
; GFX9: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD22]](s32)
- ; GFX9: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; GFX9: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD22]], [[C3]]
; GFX9: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C5]](s32)
; GFX9: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; GFX9: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; GFX9: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; GFX9: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C3]]
; GFX9: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C6]](s32)
; GFX9: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR11]](s32), [[OR14]](s32), [[OR17]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; GFX9: [[COPY25:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; GFX9: [[COPY26:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[COPY25]](s96)
- ; GFX9: $vgpr3_vgpr4_vgpr5 = COPY [[COPY26]](s96)
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; GFX9: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2s96_align1
; GFX9-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load (<3 x s32>), align 1, addrspace 3)
@@ -17368,20 +15617,16 @@ body: |
; GFX10: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -17394,18 +15639,14 @@ body: |
; GFX10: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX10: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX10: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX10: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX10: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX10: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX10: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX10: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX10: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX10: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX10: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX10: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX10: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -17416,18 +15657,14 @@ body: |
; GFX10: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX10: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX10: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX10: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX10: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX10: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX10: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX10: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX10: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX10: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX10: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX10: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX10: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX10: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX10: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX10: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX10: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX10: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -17441,18 +15678,14 @@ body: |
; GFX10: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; GFX10: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX10: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; GFX10: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX10: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX10: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX10: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX10: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX10: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX10: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX10: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX10: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX10: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX10: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX10: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX10: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX10: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX10: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX10: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX10: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX10: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX10: [[PTR_ADD15:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C7]](s32)
@@ -17463,18 +15696,14 @@ body: |
; GFX10: [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD17]](p3) :: (load (s8) from unknown-address + 18, addrspace 3)
; GFX10: [[PTR_ADD18:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD15]], [[C2]](s32)
; GFX10: [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD18]](p3) :: (load (s8) from unknown-address + 19, addrspace 3)
- ; GFX10: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD16]](s32)
- ; GFX10: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; GFX10: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; GFX10: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; GFX10: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LOAD16]], [[C3]]
+ ; GFX10: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C3]]
; GFX10: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; GFX10: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; GFX10: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD18]](s32)
- ; GFX10: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; GFX10: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LOAD18]], [[C3]]
; GFX10: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C5]](s32)
; GFX10: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; GFX10: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; GFX10: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; GFX10: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C3]]
; GFX10: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C6]](s32)
; GFX10: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; GFX10: [[PTR_ADD19:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s32)
@@ -17485,26 +15714,22 @@ body: |
; GFX10: [[LOAD22:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD21]](p3) :: (load (s8) from unknown-address + 22, addrspace 3)
; GFX10: [[PTR_ADD22:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD19]], [[C2]](s32)
; GFX10: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p3) :: (load (s8) from unknown-address + 23, addrspace 3)
- ; GFX10: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD20]](s32)
- ; GFX10: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; GFX10: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; GFX10: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; GFX10: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD20]], [[C3]]
+ ; GFX10: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C3]]
; GFX10: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C4]](s32)
; GFX10: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; GFX10: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD22]](s32)
- ; GFX10: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; GFX10: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD22]], [[C3]]
; GFX10: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C5]](s32)
; GFX10: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; GFX10: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; GFX10: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; GFX10: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C3]]
; GFX10: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C6]](s32)
; GFX10: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; GFX10: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR11]](s32), [[OR14]](s32), [[OR17]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; GFX10: [[COPY25:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; GFX10: [[COPY26:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; GFX10: $vgpr0_vgpr1_vgpr2 = COPY [[COPY25]](s96)
- ; GFX10: $vgpr3_vgpr4_vgpr5 = COPY [[COPY26]](s96)
+ ; GFX10: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; GFX10: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; GFX10: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; GFX10: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2s96_align1
; GFX10-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s8), addrspace 3)
@@ -17518,20 +15743,16 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s8) from unknown-address + 3, addrspace 3)
; GFX10-UNALIGNED: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX10-UNALIGNED: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX10-UNALIGNED: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX10-UNALIGNED: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -17544,18 +15765,14 @@ body: |
; GFX10-UNALIGNED: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s8) from unknown-address + 6, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s8) from unknown-address + 7, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX10-UNALIGNED: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX10-UNALIGNED: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX10-UNALIGNED: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX10-UNALIGNED: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX10-UNALIGNED: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX10-UNALIGNED: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -17566,18 +15783,14 @@ body: |
; GFX10-UNALIGNED: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s8) from unknown-address + 10, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s8) from unknown-address + 11, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX10-UNALIGNED: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX10-UNALIGNED: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX10-UNALIGNED: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX10-UNALIGNED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX10-UNALIGNED: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX10-UNALIGNED: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX10-UNALIGNED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX10-UNALIGNED: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX10-UNALIGNED: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX10-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -17591,18 +15804,14 @@ body: |
; GFX10-UNALIGNED: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p3) :: (load (s8) from unknown-address + 14, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD14:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p3) :: (load (s8) from unknown-address + 15, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX10-UNALIGNED: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX10-UNALIGNED: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX10-UNALIGNED: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX10-UNALIGNED: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX10-UNALIGNED: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX10-UNALIGNED: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX10-UNALIGNED: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX10-UNALIGNED: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX10-UNALIGNED: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX10-UNALIGNED: [[PTR_ADD15:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C7]](s32)
@@ -17613,18 +15822,14 @@ body: |
; GFX10-UNALIGNED: [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD17]](p3) :: (load (s8) from unknown-address + 18, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD18:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD15]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD18]](p3) :: (load (s8) from unknown-address + 19, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD16]](s32)
- ; GFX10-UNALIGNED: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; GFX10-UNALIGNED: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LOAD16]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C3]]
; GFX10-UNALIGNED: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; GFX10-UNALIGNED: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD18]](s32)
- ; GFX10-UNALIGNED: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LOAD18]], [[C3]]
; GFX10-UNALIGNED: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; GFX10-UNALIGNED: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; GFX10-UNALIGNED: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C3]]
; GFX10-UNALIGNED: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; GFX10-UNALIGNED: [[PTR_ADD19:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s32)
@@ -17635,26 +15840,22 @@ body: |
; GFX10-UNALIGNED: [[LOAD22:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD21]](p3) :: (load (s8) from unknown-address + 22, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD22:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD19]], [[C2]](s32)
; GFX10-UNALIGNED: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p3) :: (load (s8) from unknown-address + 23, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD20]](s32)
- ; GFX10-UNALIGNED: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; GFX10-UNALIGNED: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; GFX10-UNALIGNED: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD20]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C3]]
; GFX10-UNALIGNED: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C4]](s32)
; GFX10-UNALIGNED: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; GFX10-UNALIGNED: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD22]](s32)
- ; GFX10-UNALIGNED: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD22]], [[C3]]
; GFX10-UNALIGNED: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C5]](s32)
; GFX10-UNALIGNED: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; GFX10-UNALIGNED: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; GFX10-UNALIGNED: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; GFX10-UNALIGNED: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C3]]
; GFX10-UNALIGNED: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C6]](s32)
; GFX10-UNALIGNED: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; GFX10-UNALIGNED: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR11]](s32), [[OR14]](s32), [[OR17]](s32)
; GFX10-UNALIGNED: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; GFX10-UNALIGNED: [[COPY25:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; GFX10-UNALIGNED: [[COPY26:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; GFX10-UNALIGNED: $vgpr0_vgpr1_vgpr2 = COPY [[COPY25]](s96)
- ; GFX10-UNALIGNED: $vgpr3_vgpr4_vgpr5 = COPY [[COPY26]](s96)
+ ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; GFX10-UNALIGNED: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; GFX10-UNALIGNED: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
%0:_(p3) = COPY $vgpr0
%1:_(<2 x s96>) = G_LOAD %0 :: (load (<2 x s96>), align 1, addrspace 3)
%2:_(s96) = G_EXTRACT %1, 0
@@ -17676,10 +15877,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -17688,10 +15887,8 @@ body: |
; SI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -17699,10 +15896,8 @@ body: |
; SI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; SI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -17712,38 +15907,32 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; SI: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s32)
; SI: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD7]](p3) :: (load (s16) from unknown-address + 16, addrspace 3)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C]](s32)
; SI: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p3) :: (load (s16) from unknown-address + 18, addrspace 3)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C1]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C1]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; SI: [[PTR_ADD9:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C4]](s32)
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s16) from unknown-address + 20, addrspace 3)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD9]], [[C]](s32)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s16) from unknown-address + 22, addrspace 3)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C1]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C1]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR3]](s32), [[OR4]](s32), [[OR5]](s32)
; SI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; SI: [[COPY13:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; SI: [[COPY14:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; SI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY13]](s96)
- ; SI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY14]](s96)
+ ; SI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; SI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; SI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; SI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; CI-LABEL: name: test_load_local_v2s96_align2
; CI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
@@ -17751,10 +15940,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -17763,10 +15950,8 @@ body: |
; CI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; CI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -17774,10 +15959,8 @@ body: |
; CI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; CI: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; CI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -17787,38 +15970,32 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s32)
; CI: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD7]](p3) :: (load (s16) from unknown-address + 16, addrspace 3)
; CI: [[PTR_ADD8:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C]](s32)
; CI: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p3) :: (load (s16) from unknown-address + 18, addrspace 3)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C1]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C1]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; CI: [[PTR_ADD9:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C4]](s32)
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s16) from unknown-address + 20, addrspace 3)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD9]], [[C]](s32)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s16) from unknown-address + 22, addrspace 3)
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C1]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C1]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; CI: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR3]](s32), [[OR4]](s32), [[OR5]](s32)
; CI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; CI: [[COPY13:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; CI: [[COPY14:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; CI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY13]](s96)
- ; CI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY14]](s96)
+ ; CI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; CI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; CI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; CI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; CI-DS128-LABEL: name: test_load_local_v2s96_align2
; CI-DS128: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CI-DS128: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
@@ -17826,10 +16003,8 @@ body: |
; CI-DS128: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI-DS128: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; CI-DS128: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI-DS128: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI-DS128: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI-DS128: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI-DS128: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI-DS128: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI-DS128: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI-DS128: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -17838,10 +16013,8 @@ body: |
; CI-DS128: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; CI-DS128: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; CI-DS128: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; CI-DS128: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI-DS128: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI-DS128: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI-DS128: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI-DS128: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI-DS128: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI-DS128: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -17849,10 +16022,8 @@ body: |
; CI-DS128: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; CI-DS128: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; CI-DS128: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; CI-DS128: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI-DS128: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI-DS128: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; CI-DS128: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; CI-DS128: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI-DS128: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI-DS128: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -17862,38 +16033,32 @@ body: |
; CI-DS128: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; CI-DS128: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; CI-DS128: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; CI-DS128: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; CI-DS128: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; CI-DS128: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; CI-DS128: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; CI-DS128: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI-DS128: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI-DS128: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s32)
; CI-DS128: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD7]](p3) :: (load (s16) from unknown-address + 16, addrspace 3)
; CI-DS128: [[PTR_ADD8:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C]](s32)
; CI-DS128: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p3) :: (load (s16) from unknown-address + 18, addrspace 3)
- ; CI-DS128: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI-DS128: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; CI-DS128: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI-DS128: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; CI-DS128: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C1]]
+ ; CI-DS128: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C1]]
; CI-DS128: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
; CI-DS128: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; CI-DS128: [[PTR_ADD9:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C4]](s32)
; CI-DS128: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s16) from unknown-address + 20, addrspace 3)
; CI-DS128: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD9]], [[C]](s32)
; CI-DS128: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s16) from unknown-address + 22, addrspace 3)
- ; CI-DS128: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI-DS128: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; CI-DS128: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI-DS128: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; CI-DS128: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C1]]
+ ; CI-DS128: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C1]]
; CI-DS128: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; CI-DS128: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; CI-DS128: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR3]](s32), [[OR4]](s32), [[OR5]](s32)
; CI-DS128: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; CI-DS128: [[COPY13:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; CI-DS128: [[COPY14:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; CI-DS128: $vgpr0_vgpr1_vgpr2 = COPY [[COPY13]](s96)
- ; CI-DS128: $vgpr3_vgpr4_vgpr5 = COPY [[COPY14]](s96)
+ ; CI-DS128: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; CI-DS128: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; CI-DS128: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; CI-DS128: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; VI-LABEL: name: test_load_local_v2s96_align2
; VI: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
@@ -17901,10 +16066,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -17913,10 +16076,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -17924,10 +16085,8 @@ body: |
; VI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; VI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -17937,38 +16096,32 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; VI: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s32)
; VI: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD7]](p3) :: (load (s16) from unknown-address + 16, addrspace 3)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C]](s32)
; VI: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p3) :: (load (s16) from unknown-address + 18, addrspace 3)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C1]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C1]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; VI: [[PTR_ADD9:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C4]](s32)
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s16) from unknown-address + 20, addrspace 3)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD9]], [[C]](s32)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s16) from unknown-address + 22, addrspace 3)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C1]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C1]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; VI: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR3]](s32), [[OR4]](s32), [[OR5]](s32)
; VI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; VI: [[COPY13:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; VI: [[COPY14:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY13]](s96)
- ; VI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY14]](s96)
+ ; VI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; VI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; VI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; GFX9-LABEL: name: test_load_local_v2s96_align2
; GFX9: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
@@ -17976,10 +16129,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -17988,10 +16139,8 @@ body: |
; GFX9: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -17999,10 +16148,8 @@ body: |
; GFX9: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; GFX9: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; GFX9: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -18012,38 +16159,32 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX9: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s32)
; GFX9: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD7]](p3) :: (load (s16) from unknown-address + 16, addrspace 3)
; GFX9: [[PTR_ADD8:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C]](s32)
; GFX9: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p3) :: (load (s16) from unknown-address + 18, addrspace 3)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C1]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C1]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; GFX9: [[PTR_ADD9:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C4]](s32)
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s16) from unknown-address + 20, addrspace 3)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD9]], [[C]](s32)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s16) from unknown-address + 22, addrspace 3)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C1]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C1]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR3]](s32), [[OR4]](s32), [[OR5]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[COPY13]](s96)
- ; GFX9: $vgpr3_vgpr4_vgpr5 = COPY [[COPY14]](s96)
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; GFX9: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; GFX9-UNALIGNED-LABEL: name: test_load_local_v2s96_align2
; GFX9-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX9-UNALIGNED: [[LOAD:%[0-9]+]]:_(<3 x s32>) = G_LOAD [[COPY]](p3) :: (load (<3 x s32>), align 2, addrspace 3)
@@ -18063,10 +16204,8 @@ body: |
; GFX10: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX10: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX10: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX10: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX10: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX10: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX10: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX10: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX10: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -18075,10 +16214,8 @@ body: |
; GFX10: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; GFX10: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX10: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; GFX10: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX10: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX10: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX10: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX10: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX10: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX10: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -18086,10 +16223,8 @@ body: |
; GFX10: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; GFX10: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; GFX10: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; GFX10: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX10: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX10: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX10: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX10: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX10: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX10: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -18099,38 +16234,32 @@ body: |
; GFX10: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; GFX10: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; GFX10: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; GFX10: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; GFX10: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; GFX10: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; GFX10: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; GFX10: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX10: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX10: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s32)
; GFX10: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD7]](p3) :: (load (s16) from unknown-address + 16, addrspace 3)
; GFX10: [[PTR_ADD8:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C]](s32)
; GFX10: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p3) :: (load (s16) from unknown-address + 18, addrspace 3)
- ; GFX10: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX10: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; GFX10: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX10: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; GFX10: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C1]]
+ ; GFX10: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C1]]
; GFX10: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
; GFX10: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; GFX10: [[PTR_ADD9:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C4]](s32)
; GFX10: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s16) from unknown-address + 20, addrspace 3)
; GFX10: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD9]], [[C]](s32)
; GFX10: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s16) from unknown-address + 22, addrspace 3)
- ; GFX10: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX10: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; GFX10: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX10: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; GFX10: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C1]]
+ ; GFX10: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C1]]
; GFX10: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; GFX10: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; GFX10: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR3]](s32), [[OR4]](s32), [[OR5]](s32)
; GFX10: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; GFX10: [[COPY13:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; GFX10: [[COPY14:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; GFX10: $vgpr0_vgpr1_vgpr2 = COPY [[COPY13]](s96)
- ; GFX10: $vgpr3_vgpr4_vgpr5 = COPY [[COPY14]](s96)
+ ; GFX10: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; GFX10: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; GFX10: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; GFX10: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; GFX10-UNALIGNED-LABEL: name: test_load_local_v2s96_align2
; GFX10-UNALIGNED: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; GFX10-UNALIGNED: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s16), addrspace 3)
@@ -18138,10 +16267,8 @@ body: |
; GFX10-UNALIGNED: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p3) :: (load (s16) from unknown-address + 2, addrspace 3)
; GFX10-UNALIGNED: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX10-UNALIGNED: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX10-UNALIGNED: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -18150,10 +16277,8 @@ body: |
; GFX10-UNALIGNED: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p3) :: (load (s16) from unknown-address + 4, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD2:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p3) :: (load (s16) from unknown-address + 6, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX10-UNALIGNED: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX10-UNALIGNED: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -18161,10 +16286,8 @@ body: |
; GFX10-UNALIGNED: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p3) :: (load (s16) from unknown-address + 8, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD4:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p3) :: (load (s16) from unknown-address + 10, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX10-UNALIGNED: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX10-UNALIGNED: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -18174,38 +16297,32 @@ body: |
; GFX10-UNALIGNED: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p3) :: (load (s16) from unknown-address + 12, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD6:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p3) :: (load (s16) from unknown-address + 14, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; GFX10-UNALIGNED: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX10-UNALIGNED: [[PTR_ADD7:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s32)
; GFX10-UNALIGNED: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD7]](p3) :: (load (s16) from unknown-address + 16, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD8:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD7]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p3) :: (load (s16) from unknown-address + 18, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX10-UNALIGNED: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX10-UNALIGNED: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C1]]
; GFX10-UNALIGNED: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; GFX10-UNALIGNED: [[PTR_ADD9:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD5]], [[C4]](s32)
; GFX10-UNALIGNED: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p3) :: (load (s16) from unknown-address + 20, addrspace 3)
; GFX10-UNALIGNED: [[PTR_ADD10:%[0-9]+]]:_(p3) = G_PTR_ADD [[PTR_ADD9]], [[C]](s32)
; GFX10-UNALIGNED: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p3) :: (load (s16) from unknown-address + 22, addrspace 3)
- ; GFX10-UNALIGNED: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX10-UNALIGNED: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; GFX10-UNALIGNED: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX10-UNALIGNED: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C1]]
+ ; GFX10-UNALIGNED: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C1]]
; GFX10-UNALIGNED: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; GFX10-UNALIGNED: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; GFX10-UNALIGNED: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR3]](s32), [[OR4]](s32), [[OR5]](s32)
; GFX10-UNALIGNED: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; GFX10-UNALIGNED: [[COPY13:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; GFX10-UNALIGNED: [[COPY14:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; GFX10-UNALIGNED: $vgpr0_vgpr1_vgpr2 = COPY [[COPY13]](s96)
- ; GFX10-UNALIGNED: $vgpr3_vgpr4_vgpr5 = COPY [[COPY14]](s96)
+ ; GFX10-UNALIGNED: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; GFX10-UNALIGNED: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; GFX10-UNALIGNED: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; GFX10-UNALIGNED: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
%0:_(p3) = COPY $vgpr0
%1:_(<2 x s96>) = G_LOAD %0 :: (load (<2 x s96>), align 2, addrspace 3)
%2:_(s96) = G_EXTRACT %1, 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir
index 52d0cafc06340..05cf3e08c56b3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir
@@ -43,8 +43,7 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), !tbaa !1, addrspace 1)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; SI: $vgpr0 = COPY [[AND]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s24) = G_LOAD %0 :: (load (s24), align 4, addrspace 1, !range !0, !tbaa !1)
@@ -77,8 +76,7 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), !tbaa !1, addrspace 1)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; SI: $vgpr0 = COPY [[AND]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s24) = G_LOAD %0 :: (load (s24), align 4, addrspace 1, !tbaa !1)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
index 226aa1bd3893b..aee201a4b234c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
@@ -15,29 +15,25 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; SI: $vgpr0 = COPY [[AND]](s32)
; CI-LABEL: name: test_load_private_s1_align1
; CI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI: $vgpr0 = COPY [[AND]](s32)
; VI-LABEL: name: test_load_private_s1_align1
; VI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; VI: $vgpr0 = COPY [[AND]](s32)
; GFX9-LABEL: name: test_load_private_s1_align1
; GFX9: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9: $vgpr0 = COPY [[AND]](s32)
%0:_(p5) = COPY $vgpr0
%1:_(s1) = G_LOAD %0 :: (load (s1), align 1, addrspace 5)
@@ -55,29 +51,25 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; SI: $vgpr0 = COPY [[AND]](s32)
; CI-LABEL: name: test_load_private_s2_align1
; CI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; CI: $vgpr0 = COPY [[AND]](s32)
; VI-LABEL: name: test_load_private_s2_align1
; VI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; VI: $vgpr0 = COPY [[AND]](s32)
; GFX9-LABEL: name: test_load_private_s2_align1
; GFX9: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; GFX9: $vgpr0 = COPY [[AND]](s32)
%0:_(p5) = COPY $vgpr0
%1:_(s2) = G_LOAD %0 :: (load (s2), align 1, addrspace 5)
@@ -94,23 +86,19 @@ body: |
; SI-LABEL: name: test_load_private_s8_align4
; SI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[LOAD]](s32)
; CI-LABEL: name: test_load_private_s8_align4
; CI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_private_s8_align4
; VI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_private_s8_align4
; GFX9: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), align 4, addrspace 5)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p5) = COPY $vgpr0
%1:_(s8) = G_LOAD %0 :: (load (s8), align 4, addrspace 5)
%2:_(s32) = G_ANYEXT %1
@@ -126,23 +114,19 @@ body: |
; SI-LABEL: name: test_load_private_s8_align1
; SI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[LOAD]](s32)
; CI-LABEL: name: test_load_private_s8_align1
; CI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_private_s8_align1
; VI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_private_s8_align1
; GFX9: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p5) = COPY $vgpr0
%1:_(s8) = G_LOAD %0 :: (load (s8), align 1, addrspace 5)
%2:_(s32) = G_ANYEXT %1
@@ -158,23 +142,19 @@ body: |
; SI-LABEL: name: test_load_private_s16_align4
; SI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[LOAD]](s32)
; CI-LABEL: name: test_load_private_s16_align4
; CI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_private_s16_align4
; VI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_private_s16_align4
; GFX9: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), align 4, addrspace 5)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p5) = COPY $vgpr0
%1:_(s16) = G_LOAD %0 :: (load (s16), align 4, addrspace 5)
%2:_(s32) = G_ANYEXT %1
@@ -190,23 +170,19 @@ body: |
; SI-LABEL: name: test_load_private_s16_align2
; SI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), addrspace 5)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[LOAD]](s32)
; CI-LABEL: name: test_load_private_s16_align2
; CI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), addrspace 5)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_private_s16_align2
; VI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), addrspace 5)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_private_s16_align2
; GFX9: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), addrspace 5)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p5) = COPY $vgpr0
%1:_(s16) = G_LOAD %0 :: (load (s16), align 2, addrspace 5)
%2:_(s32) = G_ANYEXT %1
@@ -230,8 +206,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -248,8 +223,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -333,10 +307,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -348,10 +320,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -363,10 +333,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -378,10 +346,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -410,20 +376,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -441,20 +403,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -472,20 +430,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -503,20 +457,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -535,23 +485,19 @@ body: |
; SI-LABEL: name: test_load_private_s24_align8
; SI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), align 8, addrspace 5)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[LOAD]](s32)
; CI-LABEL: name: test_load_private_s24_align8
; CI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), align 8, addrspace 5)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_private_s24_align8
; VI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), align 8, addrspace 5)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_private_s24_align8
; GFX9: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), align 8, addrspace 5)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p5) = COPY $vgpr0
%1:_(s24) = G_LOAD %0 :: (load (s24), align 8, addrspace 5)
%2:_(s32) = G_ANYEXT %1
@@ -567,23 +513,19 @@ body: |
; SI-LABEL: name: test_load_private_s24_align4
; SI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[LOAD]](s32)
; CI-LABEL: name: test_load_private_s24_align4
; CI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: $vgpr0 = COPY [[COPY1]](s32)
+ ; CI: $vgpr0 = COPY [[LOAD]](s32)
; VI-LABEL: name: test_load_private_s24_align4
; VI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[LOAD]](s32)
; GFX9-LABEL: name: test_load_private_s24_align4
; GFX9: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p5) = COPY $vgpr0
%1:_(s24) = G_LOAD %0 :: (load (s24), align 4, addrspace 5)
%2:_(s32) = G_ANYEXT %1
@@ -614,25 +556,22 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD1]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C5]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; SI: $vgpr0 = COPY [[COPY5]](s32)
+ ; SI: $vgpr0 = COPY [[OR2]](s32)
; CI-LABEL: name: test_load_private_s24_align2
; CI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), addrspace 5)
@@ -651,25 +590,22 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C5]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C5]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD1]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C4]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C5]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI: $vgpr0 = COPY [[COPY5]](s32)
+ ; CI: $vgpr0 = COPY [[OR2]](s32)
; VI-LABEL: name: test_load_private_s24_align2
; VI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), addrspace 5)
@@ -701,8 +637,7 @@ body: |
; VI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[OR2]](s32)
; GFX9-LABEL: name: test_load_private_s24_align2
; GFX9: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), addrspace 5)
@@ -734,8 +669,7 @@ body: |
; GFX9: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[OR2]](s32)
%0:_(p5) = COPY $vgpr0
%1:_(s24) = G_LOAD %0 :: (load (s24), align 2, addrspace 5)
%2:_(s32) = G_ANYEXT %1
@@ -764,15 +698,13 @@ body: |
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -781,8 +713,7 @@ body: |
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[OR2]](s32)
; CI-LABEL: name: test_load_private_s24_align1
; CI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
@@ -799,15 +730,13 @@ body: |
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -816,8 +745,7 @@ body: |
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI: $vgpr0 = COPY [[COPY4]](s32)
+ ; CI: $vgpr0 = COPY [[OR2]](s32)
; VI-LABEL: name: test_load_private_s24_align1
; VI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
@@ -847,8 +775,7 @@ body: |
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[OR2]](s32)
; GFX9-LABEL: name: test_load_private_s24_align1
; GFX9: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
@@ -878,8 +805,7 @@ body: |
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[OR2]](s32)
%0:_(p5) = COPY $vgpr0
%1:_(s24) = G_LOAD %0 :: (load (s24), align 1, addrspace 5)
%2:_(s32) = G_ANYEXT %1
@@ -901,20 +827,16 @@ body: |
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C2]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
- ; SI: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; SI: $vgpr0_vgpr1 = COPY [[MV]](s64)
; CI-LABEL: name: test_load_private_s48_align8
; CI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), align 8, addrspace 5)
@@ -924,20 +846,16 @@ body: |
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C2]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
- ; CI: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; CI: $vgpr0_vgpr1 = COPY [[MV]](s64)
; VI-LABEL: name: test_load_private_s48_align8
; VI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), align 8, addrspace 5)
@@ -947,20 +865,16 @@ body: |
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C2]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C1]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
- ; VI: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; VI: $vgpr0_vgpr1 = COPY [[MV]](s64)
; GFX9-LABEL: name: test_load_private_s48_align8
; GFX9: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), align 8, addrspace 5)
@@ -970,20 +884,16 @@ body: |
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C2]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C1]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
- ; GFX9: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; GFX9: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(p5) = COPY $vgpr0
%1:_(s48) = G_LOAD %0 :: (load (s48), align 8, addrspace 5)
%2:_(s64) = G_ANYEXT %1
@@ -1005,20 +915,16 @@ body: |
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C2]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
- ; SI: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; SI: $vgpr0_vgpr1 = COPY [[MV]](s64)
; CI-LABEL: name: test_load_private_s64_align8
; CI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), align 8, addrspace 5)
@@ -1028,20 +934,16 @@ body: |
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C2]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
- ; CI: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; CI: $vgpr0_vgpr1 = COPY [[MV]](s64)
; VI-LABEL: name: test_load_private_s64_align8
; VI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), align 8, addrspace 5)
@@ -1051,20 +953,16 @@ body: |
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C2]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C1]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
- ; VI: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; VI: $vgpr0_vgpr1 = COPY [[MV]](s64)
; GFX9-LABEL: name: test_load_private_s64_align8
; GFX9: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), align 8, addrspace 5)
@@ -1074,20 +972,16 @@ body: |
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C1]](s32)
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C2]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C1]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
- ; GFX9: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; GFX9: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(p5) = COPY $vgpr0
%1:_(s64) = G_LOAD %0 :: (load (s48), align 8, addrspace 5)
$vgpr0_vgpr1 = COPY %1
@@ -1149,10 +1043,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -1161,10 +1053,8 @@ body: |
; SI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -1176,10 +1066,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -1188,10 +1076,8 @@ body: |
; CI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -1203,10 +1089,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -1215,10 +1099,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -1230,10 +1112,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -1242,10 +1122,8 @@ body: |
; GFX9: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -1274,20 +1152,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1300,18 +1174,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
@@ -1329,20 +1199,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1355,18 +1221,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
@@ -1384,20 +1246,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1410,18 +1268,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
@@ -1439,20 +1293,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1465,18 +1315,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
@@ -1505,20 +1351,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1531,18 +1373,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -1553,18 +1391,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -1583,20 +1417,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1609,18 +1439,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -1631,18 +1457,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -1661,20 +1483,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1687,18 +1505,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -1709,18 +1523,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -1739,20 +1549,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1765,18 +1571,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -1787,18 +1589,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -1940,10 +1738,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -1952,10 +1748,8 @@ body: |
; SI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -1963,10 +1757,8 @@ body: |
; SI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p5) :: (load (s16) from unknown-address + 8, addrspace 5)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; SI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p5) :: (load (s16) from unknown-address + 10, addrspace 5)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -1979,10 +1771,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -1991,10 +1781,8 @@ body: |
; CI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -2002,10 +1790,8 @@ body: |
; CI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p5) :: (load (s16) from unknown-address + 8, addrspace 5)
; CI: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; CI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p5) :: (load (s16) from unknown-address + 10, addrspace 5)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -2018,10 +1804,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -2030,10 +1814,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -2041,10 +1823,8 @@ body: |
; VI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p5) :: (load (s16) from unknown-address + 8, addrspace 5)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; VI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p5) :: (load (s16) from unknown-address + 10, addrspace 5)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -2057,10 +1837,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -2069,10 +1847,8 @@ body: |
; GFX9: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -2080,10 +1856,8 @@ body: |
; GFX9: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p5) :: (load (s16) from unknown-address + 8, addrspace 5)
; GFX9: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; GFX9: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p5) :: (load (s16) from unknown-address + 10, addrspace 5)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -2113,20 +1887,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2139,18 +1909,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -2161,18 +1927,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -2191,20 +1953,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2217,18 +1975,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -2239,18 +1993,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -2269,20 +2019,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2295,18 +2041,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -2317,18 +2059,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -2347,20 +2085,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2373,18 +2107,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -2395,18 +2125,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -2436,20 +2162,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2462,18 +2184,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -2484,18 +2202,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -2507,18 +2221,14 @@ body: |
; SI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; SI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; SI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; SI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -2537,20 +2247,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2563,18 +2269,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -2585,18 +2287,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -2608,18 +2306,14 @@ body: |
; CI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; CI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -2638,20 +2332,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2664,18 +2354,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -2686,18 +2372,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -2709,18 +2391,14 @@ body: |
; VI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; VI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -2739,20 +2417,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -2765,18 +2439,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -2787,18 +2457,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -2810,18 +2476,14 @@ body: |
; GFX9: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; GFX9: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX9: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX9: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX9: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX9: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX9: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX9: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX9: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -2987,10 +2649,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -2999,10 +2659,8 @@ body: |
; SI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -3010,10 +2668,8 @@ body: |
; SI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p5) :: (load (s16) from unknown-address + 8, addrspace 5)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; SI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p5) :: (load (s16) from unknown-address + 10, addrspace 5)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -3021,10 +2677,8 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s16) from unknown-address + 12, addrspace 5)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s16) from unknown-address + 14, addrspace 5)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
@@ -3037,10 +2691,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -3049,10 +2701,8 @@ body: |
; CI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -3060,10 +2710,8 @@ body: |
; CI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p5) :: (load (s16) from unknown-address + 8, addrspace 5)
; CI: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; CI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p5) :: (load (s16) from unknown-address + 10, addrspace 5)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -3071,10 +2719,8 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s16) from unknown-address + 12, addrspace 5)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s16) from unknown-address + 14, addrspace 5)
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
@@ -3087,10 +2733,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -3099,10 +2743,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -3110,10 +2752,8 @@ body: |
; VI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p5) :: (load (s16) from unknown-address + 8, addrspace 5)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; VI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p5) :: (load (s16) from unknown-address + 10, addrspace 5)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -3121,10 +2761,8 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s16) from unknown-address + 12, addrspace 5)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s16) from unknown-address + 14, addrspace 5)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
@@ -3137,10 +2775,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -3149,10 +2785,8 @@ body: |
; GFX9: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -3160,10 +2794,8 @@ body: |
; GFX9: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p5) :: (load (s16) from unknown-address + 8, addrspace 5)
; GFX9: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; GFX9: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p5) :: (load (s16) from unknown-address + 10, addrspace 5)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -3171,10 +2803,8 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s16) from unknown-address + 12, addrspace 5)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s16) from unknown-address + 14, addrspace 5)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
@@ -3204,20 +2834,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3230,18 +2856,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -3252,18 +2874,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -3275,18 +2893,14 @@ body: |
; SI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; SI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; SI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; SI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -3305,20 +2919,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3331,18 +2941,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -3353,18 +2959,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -3376,18 +2978,14 @@ body: |
; CI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; CI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -3406,20 +3004,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3432,18 +3026,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -3454,18 +3044,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -3477,18 +3063,14 @@ body: |
; VI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; VI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -3507,20 +3089,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3533,18 +3111,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -3555,18 +3129,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -3578,18 +3148,14 @@ body: |
; GFX9: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; GFX9: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX9: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX9: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX9: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX9: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX9: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX9: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX9: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -3699,10 +3265,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -3711,10 +3275,8 @@ body: |
; SI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -3726,10 +3288,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -3738,10 +3298,8 @@ body: |
; CI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -3753,10 +3311,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -3765,10 +3321,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -3780,10 +3334,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -3792,10 +3344,8 @@ body: |
; GFX9: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -3824,20 +3374,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3850,18 +3396,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
@@ -3879,20 +3421,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3905,18 +3443,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
@@ -3934,20 +3468,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -3960,18 +3490,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
@@ -3989,20 +3515,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -4015,18 +3537,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
@@ -4076,10 +3594,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -4092,10 +3608,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -4108,10 +3622,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -4124,10 +3636,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -4157,20 +3667,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -4189,20 +3695,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -4221,20 +3723,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -4253,20 +3751,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -4317,10 +3811,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -4333,10 +3825,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -4349,10 +3839,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -4365,10 +3853,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -4398,20 +3884,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -4430,20 +3912,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -4462,20 +3940,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -4494,20 +3968,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -4538,8 +4008,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -4559,8 +4028,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -4623,11 +4091,7 @@ body: |
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s8) from unknown-address + 1, addrspace 5)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32)
+ ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; CI-LABEL: name: test_load_private_v2s8_align1
; CI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
@@ -4635,11 +4099,7 @@ body: |
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s8) from unknown-address + 1, addrspace 5)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32)
+ ; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; CI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; VI-LABEL: name: test_load_private_v2s8_align1
; VI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
@@ -4647,11 +4107,7 @@ body: |
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s8) from unknown-address + 1, addrspace 5)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32)
+ ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_load_private_v2s8_align1
; GFX9: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
@@ -4659,9 +4115,7 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s8) from unknown-address + 1, addrspace 5)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(p5) = COPY $vgpr0
%1:_(<2 x s8>) = G_LOAD %0 :: (load (<2 x s8>), align 1, addrspace 5)
@@ -4690,25 +4144,22 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; SI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; SI: $vgpr0 = COPY [[COPY5]](s32)
+ ; SI: $vgpr0 = COPY [[OR2]](s32)
; CI-LABEL: name: test_load_private_v3s8_align4
; CI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
@@ -4724,25 +4175,22 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY3]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI: $vgpr0 = COPY [[COPY5]](s32)
+ ; CI: $vgpr0 = COPY [[OR2]](s32)
; VI-LABEL: name: test_load_private_v3s8_align4
; VI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
@@ -4771,8 +4219,7 @@ body: |
; VI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[OR2]](s32)
; GFX9-LABEL: name: test_load_private_v3s8_align4
; GFX9: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
@@ -4801,8 +4248,7 @@ body: |
; GFX9: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[OR2]](s32)
%0:_(p5) = COPY $vgpr0
%1:_(<3 x s8>) = G_LOAD %0 :: (load (<3 x s8>), addrspace 5, align 4)
%2:_(s24) = G_BITCAST %1
@@ -4832,15 +4278,13 @@ body: |
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -4849,8 +4293,7 @@ body: |
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[OR2]](s32)
; CI-LABEL: name: test_load_private_v3s8_align1
; CI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
@@ -4867,15 +4310,13 @@ body: |
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY1]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C2]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -4884,8 +4325,7 @@ body: |
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C5]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CI: $vgpr0 = COPY [[COPY4]](s32)
+ ; CI: $vgpr0 = COPY [[OR2]](s32)
; VI-LABEL: name: test_load_private_v3s8_align1
; VI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
@@ -4915,8 +4355,7 @@ body: |
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[OR2]](s32)
; GFX9-LABEL: name: test_load_private_v3s8_align1
; GFX9: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
@@ -4946,8 +4385,7 @@ body: |
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C4]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[OR2]](s32)
%0:_(p5) = COPY $vgpr0
%1:_(<3 x s8>) = G_LOAD %0 :: (load (<3 x s8>), align 1, addrspace 5)
%2:_(s24) = G_BITCAST %1
@@ -4971,18 +4409,14 @@ body: |
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; SI: $vgpr0 = COPY [[OR2]](s32)
@@ -4996,18 +4430,14 @@ body: |
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CI: $vgpr0 = COPY [[OR2]](s32)
@@ -5021,18 +4451,14 @@ body: |
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; VI: $vgpr0 = COPY [[OR2]](s32)
@@ -5046,18 +4472,14 @@ body: |
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LOAD]], [[C2]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; GFX9: $vgpr0 = COPY [[OR2]](s32)
@@ -5089,32 +4511,24 @@ body: |
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C2]](s32)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C3]](s32)
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C4]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C4]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C4]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C4]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C4]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C2]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C4]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C3]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -5135,32 +4549,24 @@ body: |
; CI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C2]](s32)
; CI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C3]](s32)
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C4]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C4]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C4]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C4]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C4]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C2]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C4]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C3]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -5181,32 +4587,24 @@ body: |
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C2]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C3]](s32)
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C4]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C4]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C4]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C4]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C4]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C2]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C4]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C3]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -5227,32 +4625,24 @@ body: |
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C2]](s32)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[LOAD1]], [[C3]](s32)
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C4]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C4]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C4]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C4]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C4]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C4]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C4]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C4]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C2]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C4]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C3]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -5309,62 +4699,46 @@ body: |
; SI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; SI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C6]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C6]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C6]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C6]]
; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C7]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C6]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C6]]
; SI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C8]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C6]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C6]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C6]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C6]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C6]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C6]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C7]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C6]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C6]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C6]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C6]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C6]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C6]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C6]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C6]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C7]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C6]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C6]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C8]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C6]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C6]]
+ ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C6]]
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C6]]
; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; SI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C6]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C6]]
; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C7]](s32)
; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C6]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C6]]
; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C8]](s32)
; SI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -5409,62 +4783,46 @@ body: |
; CI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C6]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C6]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C6]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C6]]
; CI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C7]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C6]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C6]]
; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C8]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C6]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C6]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C6]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C6]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C6]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C6]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C7]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C6]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C6]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C6]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C6]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C6]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C6]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C6]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C6]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C7]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C6]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C6]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C8]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C6]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C6]]
+ ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C6]]
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C6]]
; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C6]]
+ ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C6]]
; CI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C7]](s32)
; CI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C6]]
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C6]]
; CI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C8]](s32)
; CI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -5509,62 +4867,46 @@ body: |
; VI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; VI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C6]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C6]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C6]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C6]]
; VI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C7]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C6]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C6]]
; VI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C8]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C6]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C6]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C6]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C6]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C6]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C6]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C7]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C6]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C6]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C6]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C6]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C6]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C6]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C6]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C6]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C7]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C6]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C6]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C8]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C6]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C6]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C6]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C6]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C6]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C6]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C7]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C6]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C6]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C8]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -5609,62 +4951,46 @@ body: |
; GFX9: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX9: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C6]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C6]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C6]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C6]]
; GFX9: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C7]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C6]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C6]]
; GFX9: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C8]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C6]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C6]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C6]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C6]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C6]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C6]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C7]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C6]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C6]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C8]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C6]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C6]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C6]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C6]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C6]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C6]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C7]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C6]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C6]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C8]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C6]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C6]]
+ ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C6]]
+ ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C6]]
; GFX9: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX9: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C6]]
+ ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C6]]
; GFX9: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C7]](s32)
; GFX9: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C6]]
+ ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C6]]
; GFX9: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C8]](s32)
; GFX9: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -5715,10 +5041,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -5731,10 +5055,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -5747,10 +5069,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -5762,9 +5082,7 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(p5) = COPY $vgpr0
%1:_(<2 x s16>) = G_LOAD %0 :: (load (<2 x s16>), align 2, addrspace 5)
@@ -5788,8 +5106,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -5800,10 +5117,9 @@ body: |
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -5824,8 +5140,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -5836,10 +5151,9 @@ body: |
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -5940,24 +5254,18 @@ body: |
; SI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -5982,24 +5290,18 @@ body: |
; CI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C1]](s32)
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -6024,24 +5326,18 @@ body: |
; VI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -6065,15 +5361,9 @@ body: |
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C1]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD1]](s32), [[BITCAST1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR1]](s32), [[BITCAST2]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(p5) = COPY $vgpr0
@@ -6109,24 +5399,18 @@ body: |
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -6152,24 +5436,18 @@ body: |
; CI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -6195,24 +5473,18 @@ body: |
; VI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -6237,15 +5509,9 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C2]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[BITCAST]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(p5) = COPY $vgpr0
@@ -6272,8 +5538,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -6284,10 +5549,9 @@ body: |
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
@@ -6297,10 +5561,9 @@ body: |
; SI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p5) :: (load (s8) from unknown-address + 5, addrspace 5)
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; SI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; SI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
@@ -6320,15 +5583,12 @@ body: |
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C7]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C6]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; SI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C7]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C7]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL5]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
@@ -6345,8 +5605,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -6357,10 +5616,9 @@ body: |
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
@@ -6370,10 +5628,9 @@ body: |
; CI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p5) :: (load (s8) from unknown-address + 5, addrspace 5)
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
@@ -6393,15 +5650,12 @@ body: |
; CI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; CI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; CI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C7]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C6]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; CI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C7]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C7]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C7]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL5]]
; CI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
@@ -6460,15 +5714,12 @@ body: |
; VI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C6]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; VI: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C6]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C6]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C6]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C5]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL5]]
; VI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR5]](s32)
@@ -6524,11 +5775,8 @@ body: |
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[OR1]](s16)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX9: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[OR2]](s16)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[COPY1]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[BITCAST]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(p5) = COPY $vgpr0
@@ -6635,10 +5883,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -6648,10 +5894,8 @@ body: |
; SI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -6664,10 +5908,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -6677,10 +5919,8 @@ body: |
; CI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -6693,10 +5933,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -6706,10 +5944,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -6721,17 +5957,13 @@ body: |
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD]](s32), [[LOAD1]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; GFX9: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C1]](s32)
; GFX9: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LOAD2]](s32), [[LOAD3]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
%0:_(p5) = COPY $vgpr0
@@ -6756,8 +5988,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -6768,10 +5999,9 @@ body: |
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -6787,10 +6017,9 @@ body: |
; SI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p5) :: (load (s8) from unknown-address + 5, addrspace 5)
; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; SI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; SI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; SI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; SI: [[PTR_ADD5:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s32)
@@ -6799,10 +6028,9 @@ body: |
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
; SI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; SI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY6]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
+ ; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY3]](s32)
; SI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; SI: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
; SI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
@@ -6823,8 +6051,7 @@ body: |
; CI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -6835,10 +6062,9 @@ body: |
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; CI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD2]](s32)
; CI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
+ ; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY1]](s32)
; CI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -6854,10 +6080,9 @@ body: |
; CI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p5) :: (load (s8) from unknown-address + 5, addrspace 5)
; CI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD4]](s32)
; CI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
+ ; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY2]](s32)
; CI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CI: [[PTR_ADD5:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s32)
@@ -6866,10 +6091,9 @@ body: |
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
; CI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LOAD6]](s32)
; CI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C1]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY6]](s32)
+ ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
+ ; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY3]](s32)
; CI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; CI: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
; CI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
@@ -7096,10 +6320,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -7108,10 +6330,8 @@ body: |
; SI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -7123,10 +6343,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -7135,10 +6353,8 @@ body: |
; CI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -7150,10 +6366,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -7162,10 +6376,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -7177,10 +6389,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -7189,10 +6399,8 @@ body: |
; GFX9: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32)
@@ -7221,20 +6429,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7247,18 +6451,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -7276,20 +6476,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7302,18 +6498,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -7331,20 +6523,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7357,18 +6545,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -7386,20 +6570,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7412,18 +6592,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32)
@@ -7452,20 +6628,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7478,18 +6650,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -7500,18 +6668,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -7529,20 +6693,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7555,18 +6715,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -7577,18 +6733,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -7606,20 +6758,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7632,18 +6780,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -7654,18 +6798,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -7683,20 +6823,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7709,18 +6845,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -7731,18 +6863,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -7826,20 +6954,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7852,18 +6976,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -7874,18 +6994,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -7897,18 +7013,14 @@ body: |
; SI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; SI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; SI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; SI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -7926,20 +7038,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -7952,18 +7060,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -7974,18 +7078,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -7997,18 +7097,14 @@ body: |
; CI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; CI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -8026,20 +7122,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -8052,18 +7144,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -8074,18 +7162,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -8097,18 +7181,14 @@ body: |
; VI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; VI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -8126,20 +7206,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -8152,18 +7228,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -8174,18 +7246,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -8197,18 +7265,14 @@ body: |
; GFX9: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; GFX9: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX9: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX9: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX9: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX9: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX9: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX9: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX9: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -8365,10 +7429,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -8377,10 +7439,8 @@ body: |
; SI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -8388,10 +7448,8 @@ body: |
; SI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p5) :: (load (s16) from unknown-address + 8, addrspace 5)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; SI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p5) :: (load (s16) from unknown-address + 10, addrspace 5)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -8399,10 +7457,8 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s16) from unknown-address + 12, addrspace 5)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s16) from unknown-address + 14, addrspace 5)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
@@ -8414,10 +7470,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -8426,10 +7480,8 @@ body: |
; CI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -8437,10 +7489,8 @@ body: |
; CI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p5) :: (load (s16) from unknown-address + 8, addrspace 5)
; CI: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; CI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p5) :: (load (s16) from unknown-address + 10, addrspace 5)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -8448,10 +7498,8 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s16) from unknown-address + 12, addrspace 5)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s16) from unknown-address + 14, addrspace 5)
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
@@ -8463,10 +7511,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -8475,10 +7521,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -8486,10 +7530,8 @@ body: |
; VI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p5) :: (load (s16) from unknown-address + 8, addrspace 5)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; VI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p5) :: (load (s16) from unknown-address + 10, addrspace 5)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -8497,10 +7539,8 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s16) from unknown-address + 12, addrspace 5)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s16) from unknown-address + 14, addrspace 5)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
@@ -8512,10 +7552,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -8524,10 +7562,8 @@ body: |
; GFX9: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -8535,10 +7571,8 @@ body: |
; GFX9: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p5) :: (load (s16) from unknown-address + 8, addrspace 5)
; GFX9: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; GFX9: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p5) :: (load (s16) from unknown-address + 10, addrspace 5)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -8546,10 +7580,8 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s16) from unknown-address + 12, addrspace 5)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s16) from unknown-address + 14, addrspace 5)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
@@ -8578,20 +7610,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -8604,18 +7632,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -8626,18 +7650,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -8649,18 +7669,14 @@ body: |
; SI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; SI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; SI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; SI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -8678,20 +7694,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -8704,18 +7716,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -8726,18 +7734,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -8749,18 +7753,14 @@ body: |
; CI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; CI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -8778,20 +7778,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -8804,18 +7800,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -8826,18 +7818,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -8849,18 +7837,14 @@ body: |
; VI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; VI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -8878,20 +7862,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -8904,18 +7884,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -8926,18 +7902,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
@@ -8949,18 +7921,14 @@ body: |
; GFX9: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; GFX9: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX9: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX9: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX9: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX9: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX9: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX9: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX9: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32), [[OR11]](s32)
@@ -9386,20 +8354,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -9412,18 +8376,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
@@ -9435,18 +8395,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[PTR_ADD11:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C7]](s32)
@@ -9457,18 +8413,14 @@ body: |
; SI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; SI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; SI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; SI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; SI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR8]](s32), [[OR11]](s32)
@@ -9487,20 +8439,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -9513,18 +8461,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
@@ -9536,18 +8480,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[PTR_ADD11:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C7]](s32)
@@ -9558,18 +8498,14 @@ body: |
; CI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; CI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR8]](s32), [[OR11]](s32)
@@ -9588,20 +8524,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -9614,18 +8546,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
@@ -9637,18 +8565,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[PTR_ADD11:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C7]](s32)
@@ -9659,18 +8583,14 @@ body: |
; VI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; VI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR8]](s32), [[OR11]](s32)
@@ -9689,20 +8609,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -9715,18 +8631,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR5]](s32)
@@ -9738,18 +8650,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[PTR_ADD11:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C7]](s32)
@@ -9760,18 +8668,14 @@ body: |
; GFX9: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; GFX9: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX9: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX9: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX9: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX9: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX9: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX9: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX9: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR8]](s32), [[OR11]](s32)
@@ -10646,20 +9550,16 @@ body: |
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; SI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -10672,18 +9572,14 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; SI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -10694,18 +9590,14 @@ body: |
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; SI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; SI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; SI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; SI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; SI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; SI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -10719,18 +9611,14 @@ body: |
; SI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; SI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; SI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; SI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; SI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; SI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; SI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; SI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; SI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; SI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; SI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; SI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; SI: [[PTR_ADD15:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C7]](s32)
@@ -10741,18 +9629,14 @@ body: |
; SI: [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD17]](p5) :: (load (s8) from unknown-address + 18, addrspace 5)
; SI: [[PTR_ADD18:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD15]], [[C2]](s32)
; SI: [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD18]](p5) :: (load (s8) from unknown-address + 19, addrspace 5)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD16]](s32)
- ; SI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; SI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; SI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LOAD16]], [[C3]]
+ ; SI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C3]]
; SI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; SI: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD18]](s32)
- ; SI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; SI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LOAD18]], [[C3]]
; SI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C5]](s32)
; SI: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; SI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; SI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C3]]
; SI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C6]](s32)
; SI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; SI: [[PTR_ADD19:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s32)
@@ -10763,26 +9647,22 @@ body: |
; SI: [[LOAD22:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD21]](p5) :: (load (s8) from unknown-address + 22, addrspace 5)
; SI: [[PTR_ADD22:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD19]], [[C2]](s32)
; SI: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p5) :: (load (s8) from unknown-address + 23, addrspace 5)
- ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD20]](s32)
- ; SI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; SI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; SI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; SI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD20]], [[C3]]
+ ; SI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C3]]
; SI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C4]](s32)
; SI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; SI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD22]](s32)
- ; SI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; SI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD22]], [[C3]]
; SI: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C5]](s32)
; SI: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; SI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; SI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; SI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C3]]
; SI: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C6]](s32)
; SI: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR11]](s32), [[OR14]](s32), [[OR17]](s32)
; SI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; SI: [[COPY25:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; SI: [[COPY26:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; SI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY25]](s96)
- ; SI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY26]](s96)
+ ; SI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; SI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; SI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; SI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; CI-LABEL: name: test_load_private_v2s96_align1
; CI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
@@ -10796,20 +9676,16 @@ body: |
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; CI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; CI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; CI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -10822,18 +9698,14 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -10844,18 +9716,14 @@ body: |
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; CI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; CI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; CI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; CI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; CI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; CI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -10869,18 +9737,14 @@ body: |
; CI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; CI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; CI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; CI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; CI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; CI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; CI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; CI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; CI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; CI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; CI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; CI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; CI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CI: [[PTR_ADD15:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C7]](s32)
@@ -10891,18 +9755,14 @@ body: |
; CI: [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD17]](p5) :: (load (s8) from unknown-address + 18, addrspace 5)
; CI: [[PTR_ADD18:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD15]], [[C2]](s32)
; CI: [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD18]](p5) :: (load (s8) from unknown-address + 19, addrspace 5)
- ; CI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD16]](s32)
- ; CI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; CI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; CI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; CI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LOAD16]], [[C3]]
+ ; CI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C3]]
; CI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; CI: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; CI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD18]](s32)
- ; CI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; CI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LOAD18]], [[C3]]
; CI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C5]](s32)
; CI: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; CI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; CI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; CI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C3]]
; CI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C6]](s32)
; CI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; CI: [[PTR_ADD19:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s32)
@@ -10913,26 +9773,22 @@ body: |
; CI: [[LOAD22:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD21]](p5) :: (load (s8) from unknown-address + 22, addrspace 5)
; CI: [[PTR_ADD22:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD19]], [[C2]](s32)
; CI: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p5) :: (load (s8) from unknown-address + 23, addrspace 5)
- ; CI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD20]](s32)
- ; CI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; CI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; CI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; CI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD20]], [[C3]]
+ ; CI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C3]]
; CI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C4]](s32)
; CI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; CI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD22]](s32)
- ; CI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; CI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD22]], [[C3]]
; CI: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C5]](s32)
; CI: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; CI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; CI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; CI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C3]]
; CI: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C6]](s32)
; CI: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; CI: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR11]](s32), [[OR14]](s32), [[OR17]](s32)
; CI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; CI: [[COPY25:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; CI: [[COPY26:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; CI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY25]](s96)
- ; CI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY26]](s96)
+ ; CI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; CI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; CI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; CI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; VI-LABEL: name: test_load_private_v2s96_align1
; VI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
@@ -10946,20 +9802,16 @@ body: |
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; VI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; VI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -10972,18 +9824,14 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; VI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -10994,18 +9842,14 @@ body: |
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; VI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; VI: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; VI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; VI: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; VI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; VI: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -11019,18 +9863,14 @@ body: |
; VI: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; VI: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; VI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; VI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; VI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; VI: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; VI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; VI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; VI: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; VI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; VI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; VI: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; VI: [[PTR_ADD15:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C7]](s32)
@@ -11041,18 +9881,14 @@ body: |
; VI: [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD17]](p5) :: (load (s8) from unknown-address + 18, addrspace 5)
; VI: [[PTR_ADD18:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD15]], [[C2]](s32)
; VI: [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD18]](p5) :: (load (s8) from unknown-address + 19, addrspace 5)
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD16]](s32)
- ; VI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; VI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; VI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; VI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LOAD16]], [[C3]]
+ ; VI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C3]]
; VI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; VI: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; VI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD18]](s32)
- ; VI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; VI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LOAD18]], [[C3]]
; VI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C5]](s32)
; VI: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; VI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; VI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; VI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C3]]
; VI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C6]](s32)
; VI: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; VI: [[PTR_ADD19:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s32)
@@ -11063,26 +9899,22 @@ body: |
; VI: [[LOAD22:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD21]](p5) :: (load (s8) from unknown-address + 22, addrspace 5)
; VI: [[PTR_ADD22:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD19]], [[C2]](s32)
; VI: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p5) :: (load (s8) from unknown-address + 23, addrspace 5)
- ; VI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD20]](s32)
- ; VI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; VI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; VI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; VI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD20]], [[C3]]
+ ; VI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C3]]
; VI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C4]](s32)
; VI: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; VI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD22]](s32)
- ; VI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; VI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD22]], [[C3]]
; VI: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C5]](s32)
; VI: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; VI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; VI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; VI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C3]]
; VI: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C6]](s32)
; VI: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; VI: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR11]](s32), [[OR14]](s32), [[OR17]](s32)
; VI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; VI: [[COPY25:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; VI: [[COPY26:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY25]](s96)
- ; VI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY26]](s96)
+ ; VI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; VI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; VI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; GFX9-LABEL: name: test_load_private_v2s96_align1
; GFX9: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s8), addrspace 5)
@@ -11096,20 +9928,16 @@ body: |
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C2]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s8) from unknown-address + 3, addrspace 5)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C3]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C3]]
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C5]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C3]]
; GFX9: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C6]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -11122,18 +9950,14 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s8) from unknown-address + 6, addrspace 5)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s8) from unknown-address + 7, addrspace 5)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C3]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C4]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C5]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C3]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; GFX9: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C4]](s32)
@@ -11144,18 +9968,14 @@ body: |
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s8) from unknown-address + 10, addrspace 5)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s32)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s8) from unknown-address + 11, addrspace 5)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C3]]
; GFX9: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C4]](s32)
; GFX9: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL6]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C3]]
; GFX9: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C5]](s32)
; GFX9: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C3]]
; GFX9: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C6]](s32)
; GFX9: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR2]](s32), [[OR5]](s32), [[OR8]](s32)
@@ -11169,18 +9989,14 @@ body: |
; GFX9: [[LOAD14:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD13]](p5) :: (load (s8) from unknown-address + 14, addrspace 5)
; GFX9: [[PTR_ADD14:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s32)
; GFX9: [[LOAD15:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD14]](p5) :: (load (s8) from unknown-address + 15, addrspace 5)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LOAD12]](s32)
- ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LOAD13]](s32)
- ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LOAD12]], [[C3]]
+ ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[LOAD13]], [[C3]]
; GFX9: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C4]](s32)
; GFX9: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL9]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LOAD14]](s32)
- ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LOAD14]], [[C3]]
; GFX9: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C5]](s32)
; GFX9: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LOAD15]](s32)
- ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[LOAD15]], [[C3]]
; GFX9: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C6]](s32)
; GFX9: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; GFX9: [[PTR_ADD15:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C7]](s32)
@@ -11191,18 +10007,14 @@ body: |
; GFX9: [[LOAD18:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD17]](p5) :: (load (s8) from unknown-address + 18, addrspace 5)
; GFX9: [[PTR_ADD18:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD15]], [[C2]](s32)
; GFX9: [[LOAD19:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD18]](p5) :: (load (s8) from unknown-address + 19, addrspace 5)
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LOAD16]](s32)
- ; GFX9: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LOAD17]](s32)
- ; GFX9: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; GFX9: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LOAD16]], [[C3]]
+ ; GFX9: [[AND17:%[0-9]+]]:_(s32) = G_AND [[LOAD17]], [[C3]]
; GFX9: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C4]](s32)
; GFX9: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND16]], [[SHL12]]
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LOAD18]](s32)
- ; GFX9: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; GFX9: [[AND18:%[0-9]+]]:_(s32) = G_AND [[LOAD18]], [[C3]]
; GFX9: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C5]](s32)
; GFX9: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
- ; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LOAD19]](s32)
- ; GFX9: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; GFX9: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LOAD19]], [[C3]]
; GFX9: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C6]](s32)
; GFX9: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; GFX9: [[PTR_ADD19:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s32)
@@ -11213,26 +10025,22 @@ body: |
; GFX9: [[LOAD22:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD21]](p5) :: (load (s8) from unknown-address + 22, addrspace 5)
; GFX9: [[PTR_ADD22:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD19]], [[C2]](s32)
; GFX9: [[LOAD23:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD22]](p5) :: (load (s8) from unknown-address + 23, addrspace 5)
- ; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LOAD20]](s32)
- ; GFX9: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LOAD21]](s32)
- ; GFX9: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; GFX9: [[AND20:%[0-9]+]]:_(s32) = G_AND [[LOAD20]], [[C3]]
+ ; GFX9: [[AND21:%[0-9]+]]:_(s32) = G_AND [[LOAD21]], [[C3]]
; GFX9: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C4]](s32)
; GFX9: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND20]], [[SHL15]]
- ; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LOAD22]](s32)
- ; GFX9: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; GFX9: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LOAD22]], [[C3]]
; GFX9: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C5]](s32)
; GFX9: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
- ; GFX9: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LOAD23]](s32)
- ; GFX9: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; GFX9: [[AND23:%[0-9]+]]:_(s32) = G_AND [[LOAD23]], [[C3]]
; GFX9: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C6]](s32)
; GFX9: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR11]](s32), [[OR14]](s32), [[OR17]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; GFX9: [[COPY25:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; GFX9: [[COPY26:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[COPY25]](s96)
- ; GFX9: $vgpr3_vgpr4_vgpr5 = COPY [[COPY26]](s96)
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; GFX9: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
%0:_(p5) = COPY $vgpr0
%1:_(<2 x s96>) = G_LOAD %0 :: (load (<2 x s96>), align 1, addrspace 5)
%2:_(s96) = G_EXTRACT %1, 0
@@ -11254,10 +10062,8 @@ body: |
; SI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; SI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -11266,10 +10072,8 @@ body: |
; SI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; SI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -11277,10 +10081,8 @@ body: |
; SI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p5) :: (load (s16) from unknown-address + 8, addrspace 5)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; SI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p5) :: (load (s16) from unknown-address + 10, addrspace 5)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -11290,38 +10092,32 @@ body: |
; SI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s16) from unknown-address + 12, addrspace 5)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; SI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s16) from unknown-address + 14, addrspace 5)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; SI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; SI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s32)
; SI: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD7]](p5) :: (load (s16) from unknown-address + 16, addrspace 5)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C]](s32)
; SI: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p5) :: (load (s16) from unknown-address + 18, addrspace 5)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C1]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C1]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
; SI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; SI: [[PTR_ADD9:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD5]], [[C4]](s32)
; SI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s16) from unknown-address + 20, addrspace 5)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD9]], [[C]](s32)
; SI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s16) from unknown-address + 22, addrspace 5)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C1]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C1]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; SI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; SI: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR3]](s32), [[OR4]](s32), [[OR5]](s32)
; SI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; SI: [[COPY13:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; SI: [[COPY14:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; SI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY13]](s96)
- ; SI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY14]](s96)
+ ; SI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; SI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; SI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; SI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; CI-LABEL: name: test_load_private_v2s96_align2
; CI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), addrspace 5)
@@ -11329,10 +10125,8 @@ body: |
; CI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; CI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; CI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; CI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -11341,10 +10135,8 @@ body: |
; CI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; CI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; CI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; CI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; CI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -11352,10 +10144,8 @@ body: |
; CI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p5) :: (load (s16) from unknown-address + 8, addrspace 5)
; CI: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; CI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p5) :: (load (s16) from unknown-address + 10, addrspace 5)
- ; CI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; CI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; CI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -11365,38 +10155,32 @@ body: |
; CI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s16) from unknown-address + 12, addrspace 5)
; CI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; CI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s16) from unknown-address + 14, addrspace 5)
- ; CI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; CI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; CI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; CI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; CI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; CI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s32)
; CI: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD7]](p5) :: (load (s16) from unknown-address + 16, addrspace 5)
; CI: [[PTR_ADD8:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C]](s32)
; CI: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p5) :: (load (s16) from unknown-address + 18, addrspace 5)
- ; CI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; CI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; CI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C1]]
+ ; CI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C1]]
; CI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
; CI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; CI: [[PTR_ADD9:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD5]], [[C4]](s32)
; CI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s16) from unknown-address + 20, addrspace 5)
; CI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD9]], [[C]](s32)
; CI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s16) from unknown-address + 22, addrspace 5)
- ; CI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; CI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; CI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C1]]
+ ; CI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C1]]
; CI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; CI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; CI: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR3]](s32), [[OR4]](s32), [[OR5]](s32)
; CI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; CI: [[COPY13:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; CI: [[COPY14:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; CI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY13]](s96)
- ; CI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY14]](s96)
+ ; CI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; CI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; CI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; CI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; VI-LABEL: name: test_load_private_v2s96_align2
; VI: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), addrspace 5)
@@ -11404,10 +10188,8 @@ body: |
; VI: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; VI: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -11416,10 +10198,8 @@ body: |
; VI: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; VI: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; VI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -11427,10 +10207,8 @@ body: |
; VI: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p5) :: (load (s16) from unknown-address + 8, addrspace 5)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; VI: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p5) :: (load (s16) from unknown-address + 10, addrspace 5)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; VI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; VI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -11440,38 +10218,32 @@ body: |
; VI: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s16) from unknown-address + 12, addrspace 5)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; VI: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s16) from unknown-address + 14, addrspace 5)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; VI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; VI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; VI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; VI: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; VI: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s32)
; VI: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD7]](p5) :: (load (s16) from unknown-address + 16, addrspace 5)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C]](s32)
; VI: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p5) :: (load (s16) from unknown-address + 18, addrspace 5)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; VI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C1]]
+ ; VI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C1]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
; VI: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; VI: [[PTR_ADD9:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD5]], [[C4]](s32)
; VI: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s16) from unknown-address + 20, addrspace 5)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD9]], [[C]](s32)
; VI: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s16) from unknown-address + 22, addrspace 5)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; VI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C1]]
+ ; VI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C1]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; VI: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; VI: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR3]](s32), [[OR4]](s32), [[OR5]](s32)
; VI: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; VI: [[COPY13:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; VI: [[COPY14:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY13]](s96)
- ; VI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY14]](s96)
+ ; VI: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; VI: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; VI: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; VI: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
; GFX9-LABEL: name: test_load_private_v2s96_align2
; GFX9: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; GFX9: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s16), addrspace 5)
@@ -11479,10 +10251,8 @@ body: |
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY]], [[C]](s32)
; GFX9: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p5) :: (load (s16) from unknown-address + 2, addrspace 5)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C1]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -11491,10 +10261,8 @@ body: |
; GFX9: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p5) :: (load (s16) from unknown-address + 4, addrspace 5)
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)
; GFX9: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p5) :: (load (s16) from unknown-address + 6, addrspace 5)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LOAD2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LOAD3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LOAD2]], [[C1]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LOAD3]], [[C1]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
@@ -11502,10 +10270,8 @@ body: |
; GFX9: [[LOAD4:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p5) :: (load (s16) from unknown-address + 8, addrspace 5)
; GFX9: [[PTR_ADD4:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)
; GFX9: [[LOAD5:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD4]](p5) :: (load (s16) from unknown-address + 10, addrspace 5)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LOAD4]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LOAD5]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LOAD4]], [[C1]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LOAD5]], [[C1]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32)
@@ -11515,38 +10281,32 @@ body: |
; GFX9: [[LOAD6:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD5]](p5) :: (load (s16) from unknown-address + 12, addrspace 5)
; GFX9: [[PTR_ADD6:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)
; GFX9: [[LOAD7:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD6]](p5) :: (load (s16) from unknown-address + 14, addrspace 5)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LOAD6]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LOAD7]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LOAD6]], [[C1]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LOAD7]], [[C1]]
; GFX9: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C2]](s32)
; GFX9: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; GFX9: [[PTR_ADD7:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s32)
; GFX9: [[LOAD8:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD7]](p5) :: (load (s16) from unknown-address + 16, addrspace 5)
; GFX9: [[PTR_ADD8:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD7]], [[C]](s32)
; GFX9: [[LOAD9:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD8]](p5) :: (load (s16) from unknown-address + 18, addrspace 5)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LOAD8]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LOAD9]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LOAD8]], [[C1]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LOAD9]], [[C1]]
; GFX9: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C2]](s32)
; GFX9: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL4]]
; GFX9: [[PTR_ADD9:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD5]], [[C4]](s32)
; GFX9: [[LOAD10:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD9]](p5) :: (load (s16) from unknown-address + 20, addrspace 5)
; GFX9: [[PTR_ADD10:%[0-9]+]]:_(p5) = G_PTR_ADD [[PTR_ADD9]], [[C]](s32)
; GFX9: [[LOAD11:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD10]](p5) :: (load (s16) from unknown-address + 22, addrspace 5)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LOAD10]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LOAD11]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LOAD10]], [[C1]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LOAD11]], [[C1]]
; GFX9: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; GFX9: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL5]]
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[OR3]](s32), [[OR4]](s32), [[OR5]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s96) = G_BITCAST [[BUILD_VECTOR1]](<3 x s32>)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
- ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[COPY13]](s96)
- ; GFX9: $vgpr3_vgpr4_vgpr5 = COPY [[COPY14]](s96)
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s96) = COPY [[BITCAST]](s96)
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s96) = COPY [[BITCAST1]](s96)
+ ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[COPY1]](s96)
+ ; GFX9: $vgpr3_vgpr4_vgpr5 = COPY [[COPY2]](s96)
%0:_(p5) = COPY $vgpr0
%1:_(<2 x s96>) = G_LOAD %0 :: (load (<2 x s96>), align 2, addrspace 5)
%2:_(s96) = G_EXTRACT %1, 0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
index 7ed97440ef699..b0b619e18a1d4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
@@ -95,24 +95,21 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s32)
; SI: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
; VI-LABEL: name: test_lshr_s64_s16
; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s32)
; VI: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
; GFX9-LABEL: name: test_lshr_s64_s16
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[AND]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
@@ -132,11 +129,9 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: $vgpr0 = COPY [[COPY3]](s32)
+ ; SI: $vgpr0 = COPY [[LSHR]](s32)
; VI-LABEL: name: test_lshr_s16_s32
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -171,13 +166,10 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[LSHR]](s32)
; VI-LABEL: name: test_lshr_s16_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -213,14 +205,11 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[LSHR]](s32)
; VI-LABEL: name: test_lshr_s16_i8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -260,19 +249,15 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[LSHR]](s32)
; VI-LABEL: name: test_lshr_i8_i8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
@@ -284,8 +269,7 @@ body: |
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C1]]
@@ -491,20 +475,14 @@ body: |
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -554,16 +532,12 @@ body: |
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[UV]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[UV1]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
; SI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -636,30 +610,21 @@ body: |
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[AND4]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL1]]
@@ -731,9 +696,7 @@ body: |
; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[LSHR]](<2 x s16>)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR2]](s32)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; GFX9: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[DEF1]](s32)
@@ -772,20 +735,14 @@ body: |
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[AND4]](s32)
; SI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; SI: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
@@ -796,24 +753,18 @@ body: |
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; SI: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL]]
; SI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL1]]
; SI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C1]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL2]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -858,15 +809,12 @@ body: |
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[LSHR6]](s16)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; VI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -899,15 +847,10 @@ body: |
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR2]](s32)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[COPY4]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[BITCAST1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR3]](s32), [[BITCAST2]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
@@ -941,37 +884,25 @@ body: |
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[AND4]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[AND6]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL1]]
; SI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
index e6391f6c6b293..c2c4edd1b7603 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
@@ -27,31 +27,27 @@ body: |
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C2]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY8]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C]]
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C2]]
- ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY10]](s32)
+ ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY9]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[COPY4]](s32)
; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C]]
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C2]]
- ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY12]](s32)
+ ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
+ ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY10]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC5]]
; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[COPY6]](s32)
; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C]]
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C2]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C1]](s32)
; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC7]]
@@ -97,10 +93,8 @@ body: |
; CHECK: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[C2]], [[C1]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C4]]
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C3]](s32)
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C3]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -126,24 +120,21 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY]](s32)
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
; CHECK: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
- ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[C5]], [[C1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
- ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[C5]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C4]]
+ ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C3]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
- ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC1]]
+ ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND1]], [[TRUNC1]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C6]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY3]](s32)
+ ; CHECK: $vgpr0 = COPY [[OR2]](s32)
%0:_(s8) = G_CONSTANT i8 0
%1:_(s8) = G_CONSTANT i8 1
%2:_(s8) = G_CONSTANT i8 2
@@ -161,23 +152,18 @@ body: |
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C4]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
- ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C5]](s32)
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+ ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C4]](s32)
+ ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[SHL]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
- ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C6]](s32)
+ ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C5]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
- ; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C7]](s32)
+ ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C6]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: $vgpr0 = COPY [[OR2]](s32)
%0:_(s8) = G_CONSTANT i8 0
@@ -215,17 +201,13 @@ body: |
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
@@ -261,40 +243,34 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C8]]
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY]](s32)
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C8]]
- ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[COPY2]](s32)
+ ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[COPY2]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[TRUNC1]]
; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C8]]
- ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY4]](s32)
+ ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[COPY4]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[TRUNC2]]
; CHECK: [[COPY6:%[0-9]+]]:_(s16) = COPY [[C7]](s16)
- ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C5]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C5]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C8]]
- ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY7]](s32)
+ ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[COPY7]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
- ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC3]]
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C8]]
- ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C9]](s32)
+ ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND1]], [[TRUNC3]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C8]]
+ ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C9]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[OR3]], [[TRUNC4]]
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C8]]
- ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C10]](s32)
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C8]]
+ ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C10]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[OR4]], [[TRUNC5]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
@@ -333,40 +309,34 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C9]]
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY]](s32)
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C9]]
- ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[COPY2]](s32)
+ ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[COPY2]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[TRUNC1]]
; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C9]]
- ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY4]](s32)
+ ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[COPY4]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[TRUNC2]]
; CHECK: [[COPY6:%[0-9]+]]:_(s16) = COPY [[C8]](s16)
- ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C6]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C6]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C9]]
- ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY7]](s32)
+ ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[COPY7]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
- ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC3]]
+ ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND1]], [[TRUNC3]]
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C9]]
- ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C10]](s32)
+ ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C10]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[OR3]], [[TRUNC4]]
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C9]]
- ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C11]](s32)
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C9]]
+ ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C11]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[OR4]], [[TRUNC5]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
@@ -400,42 +370,33 @@ body: |
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C8]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C8]]
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C4]](s32)
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C4]](s32)
+ ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[SHL]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C8]]
- ; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C9]](s32)
+ ; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C8]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C8]]
- ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C10]](s32)
+ ; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+ ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C9]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C8]]
- ; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C11]](s32)
+ ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C10]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C8]]
- ; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C12]](s32)
+ ; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
+ ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C11]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C8]]
- ; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C13]](s32)
+ ; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C12]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C8]]
- ; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
- ; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C14]](s32)
+ ; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
+ ; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C13]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
; CHECK: S_NOP 0, implicit [[OR6]](s32)
%0:_(s4) = G_CONSTANT i4 0
@@ -464,43 +425,38 @@ body: |
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[C5]], [[C4]]
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C7]]
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY]](s32)
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
- ; CHECK: [[C8:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
- ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[C8]], [[C4]]
+ ; CHECK: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+ ; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[C7]], [[C4]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C7]]
- ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[COPY2]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
- ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC1]]
- ; CHECK: [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
- ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[C9]], [[C4]]
+ ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND1]], [[TRUNC1]]
+ ; CHECK: [[C8:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
+ ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[C8]], [[C4]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C7]]
- ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[COPY4]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
- ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC2]]
- ; CHECK: [[C10:%[0-9]+]]:_(s16) = G_CONSTANT i16 6
- ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[C10]], [[C4]]
+ ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC2]]
+ ; CHECK: [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 6
+ ; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[C9]], [[C4]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C7]]
- ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C6]](s32)
+ ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C6]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
- ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC3]]
+ ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND3]], [[TRUNC3]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
- ; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C11]](s32)
+ ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C10]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL4]]
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
- ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C11]](s32)
+ ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C10]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL5]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR4]](s32), [[OR5]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
@@ -533,64 +489,57 @@ body: |
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[C8]], [[C7]]
; CHECK: [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C10]]
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY]](s32)
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
- ; CHECK: [[C11:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
- ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[C11]], [[C7]]
+ ; CHECK: [[C10:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
+ ; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[C10]], [[C7]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C10]]
- ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[COPY2]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
- ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC1]]
- ; CHECK: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
- ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[C12]], [[C7]]
+ ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND1]], [[TRUNC1]]
+ ; CHECK: [[C11:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
+ ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[C11]], [[C7]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C10]]
- ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[COPY4]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
- ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC2]]
- ; CHECK: [[C13:%[0-9]+]]:_(s16) = G_CONSTANT i16 6
- ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[C13]], [[C7]]
+ ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC2]]
+ ; CHECK: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 6
+ ; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[C12]], [[C7]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C10]]
- ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[COPY6]](s32)
+ ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[COPY6]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
- ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC3]]
+ ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND3]], [[TRUNC3]]
; CHECK: [[COPY8:%[0-9]+]]:_(s16) = COPY [[C9]](s16)
- ; CHECK: [[AND8:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C7]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C7]]
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C10]]
- ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[COPY9]](s32)
+ ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY10]], [[COPY9]](s32)
; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
- ; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[TRUNC4]]
- ; CHECK: [[C14:%[0-9]+]]:_(s16) = G_CONSTANT i16 10
- ; CHECK: [[AND10:%[0-9]+]]:_(s16) = G_AND [[C14]], [[C7]]
+ ; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC4]]
+ ; CHECK: [[C13:%[0-9]+]]:_(s16) = G_CONSTANT i16 10
+ ; CHECK: [[AND5:%[0-9]+]]:_(s16) = G_AND [[C13]], [[C7]]
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C10]]
- ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[COPY11]](s32)
+ ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY12]], [[COPY11]](s32)
; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
- ; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[TRUNC5]]
+ ; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[AND5]], [[TRUNC5]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
- ; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C15]](s32)
+ ; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C14]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL6]]
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
- ; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C15]](s32)
+ ; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C14]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL7]]
; CHECK: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR4]](s16)
; CHECK: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[OR5]](s16)
- ; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[ZEXT5]], [[C15]](s32)
+ ; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[ZEXT5]], [[C14]](s32)
; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[ZEXT4]], [[SHL8]]
; CHECK: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[OR6]](s32), [[OR7]](s32), [[OR8]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
@@ -657,33 +606,29 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY]](s32)
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[COPY]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC]]
; CHECK: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
- ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[C7]], [[C3]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[C7]], [[C3]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C6]]
- ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
+ ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[COPY2]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
- ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC1]]
+ ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND1]], [[TRUNC1]]
; CHECK: [[C8:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
- ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[C8]], [[C3]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[C8]], [[C3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C6]]
- ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY4]](s32)
+ ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[COPY4]](s32)
; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
- ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC2]]
+ ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC2]]
; CHECK: [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 6
- ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[C9]], [[C3]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C6]]
- ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C5]](s32)
+ ; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[C9]], [[C3]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C6]]
+ ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C5]](s32)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
- ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC3]]
+ ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND3]], [[TRUNC3]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
@@ -717,298 +662,230 @@ body: |
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C1]](s32)
+ ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[SHL]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
+ ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
+ ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C3]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
- ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
+ ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C4]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR2]], [[SHL3]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
- ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C5]](s32)
+ ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C5]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL4]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
- ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C6]](s32)
+ ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C6]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[SHL5]]
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
- ; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C7]](s32)
+ ; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C7]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[OR5]], [[SHL6]]
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C8]](s32)
+ ; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C8]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[OR6]], [[SHL7]]
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
- ; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C9]](s32)
+ ; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C9]](s32)
; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[OR7]], [[SHL8]]
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
- ; CHECK: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C10]](s32)
+ ; CHECK: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[COPY10]], [[C10]](s32)
; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[OR8]], [[SHL9]]
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
- ; CHECK: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C11]](s32)
+ ; CHECK: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[COPY11]], [[C11]](s32)
; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL10]]
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C12]](s32)
+ ; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[COPY12]], [[C12]](s32)
; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR10]], [[SHL11]]
; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
- ; CHECK: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C13]](s32)
+ ; CHECK: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[COPY13]], [[C13]](s32)
; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR11]], [[SHL12]]
; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C1]]
; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
- ; CHECK: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C14]](s32)
+ ; CHECK: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[COPY14]], [[C14]](s32)
; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[OR12]], [[SHL13]]
; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C1]]
; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C15]](s32)
+ ; CHECK: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[COPY15]], [[C15]](s32)
; CHECK: [[OR14:%[0-9]+]]:_(s32) = G_OR [[OR13]], [[SHL14]]
; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C1]]
; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND16]], [[C16]](s32)
+ ; CHECK: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[COPY16]], [[C16]](s32)
; CHECK: [[OR15:%[0-9]+]]:_(s32) = G_OR [[OR14]], [[SHL15]]
; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C1]]
; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
- ; CHECK: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[C17]](s32)
+ ; CHECK: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[COPY17]], [[C17]](s32)
; CHECK: [[OR16:%[0-9]+]]:_(s32) = G_OR [[OR15]], [[SHL16]]
; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C1]]
; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 18
- ; CHECK: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C18]](s32)
+ ; CHECK: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[COPY18]], [[C18]](s32)
; CHECK: [[OR17:%[0-9]+]]:_(s32) = G_OR [[OR16]], [[SHL17]]
; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C1]]
; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 19
- ; CHECK: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND19]], [[C19]](s32)
+ ; CHECK: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C19]](s32)
; CHECK: [[OR18:%[0-9]+]]:_(s32) = G_OR [[OR17]], [[SHL18]]
; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C1]]
; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
- ; CHECK: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND20]], [[C20]](s32)
+ ; CHECK: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C20]](s32)
; CHECK: [[OR19:%[0-9]+]]:_(s32) = G_OR [[OR18]], [[SHL19]]
; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C1]]
; CHECK: [[C21:%[0-9]+]]:_(s32) = G_CONSTANT i32 21
- ; CHECK: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND21]], [[C21]](s32)
+ ; CHECK: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[COPY21]], [[C21]](s32)
; CHECK: [[OR20:%[0-9]+]]:_(s32) = G_OR [[OR19]], [[SHL20]]
; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C1]]
; CHECK: [[C22:%[0-9]+]]:_(s32) = G_CONSTANT i32 22
- ; CHECK: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C22]](s32)
+ ; CHECK: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[COPY22]], [[C22]](s32)
; CHECK: [[OR21:%[0-9]+]]:_(s32) = G_OR [[OR20]], [[SHL21]]
; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C1]]
; CHECK: [[C23:%[0-9]+]]:_(s32) = G_CONSTANT i32 23
- ; CHECK: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND23]], [[C23]](s32)
+ ; CHECK: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[COPY23]], [[C23]](s32)
; CHECK: [[OR22:%[0-9]+]]:_(s32) = G_OR [[OR21]], [[SHL22]]
; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C1]]
; CHECK: [[C24:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C24]](s32)
+ ; CHECK: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[COPY24]], [[C24]](s32)
; CHECK: [[OR23:%[0-9]+]]:_(s32) = G_OR [[OR22]], [[SHL23]]
; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C1]]
; CHECK: [[C25:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
- ; CHECK: [[SHL24:%[0-9]+]]:_(s32) = G_SHL [[AND25]], [[C25]](s32)
+ ; CHECK: [[SHL24:%[0-9]+]]:_(s32) = G_SHL [[COPY25]], [[C25]](s32)
; CHECK: [[OR24:%[0-9]+]]:_(s32) = G_OR [[OR23]], [[SHL24]]
; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C1]]
; CHECK: [[C26:%[0-9]+]]:_(s32) = G_CONSTANT i32 26
- ; CHECK: [[SHL25:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C26]](s32)
+ ; CHECK: [[SHL25:%[0-9]+]]:_(s32) = G_SHL [[COPY26]], [[C26]](s32)
; CHECK: [[OR25:%[0-9]+]]:_(s32) = G_OR [[OR24]], [[SHL25]]
; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C1]]
; CHECK: [[C27:%[0-9]+]]:_(s32) = G_CONSTANT i32 27
- ; CHECK: [[SHL26:%[0-9]+]]:_(s32) = G_SHL [[AND27]], [[C27]](s32)
+ ; CHECK: [[SHL26:%[0-9]+]]:_(s32) = G_SHL [[COPY27]], [[C27]](s32)
; CHECK: [[OR26:%[0-9]+]]:_(s32) = G_OR [[OR25]], [[SHL26]]
; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C1]]
; CHECK: [[C28:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
- ; CHECK: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[AND28]], [[C28]](s32)
+ ; CHECK: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[COPY28]], [[C28]](s32)
; CHECK: [[OR27:%[0-9]+]]:_(s32) = G_OR [[OR26]], [[SHL27]]
; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C1]]
; CHECK: [[C29:%[0-9]+]]:_(s32) = G_CONSTANT i32 29
- ; CHECK: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[AND29]], [[C29]](s32)
+ ; CHECK: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[COPY29]], [[C29]](s32)
; CHECK: [[OR28:%[0-9]+]]:_(s32) = G_OR [[OR27]], [[SHL28]]
; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND30:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C1]]
; CHECK: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 30
- ; CHECK: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[AND30]], [[C30]](s32)
+ ; CHECK: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[COPY30]], [[C30]](s32)
; CHECK: [[OR29:%[0-9]+]]:_(s32) = G_OR [[OR28]], [[SHL29]]
; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C1]]
; CHECK: [[C31:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
- ; CHECK: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[C31]](s32)
+ ; CHECK: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[COPY31]], [[C31]](s32)
; CHECK: [[OR30:%[0-9]+]]:_(s32) = G_OR [[OR29]], [[SHL30]]
; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND32:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C1]]
; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND33:%[0-9]+]]:_(s32) = G_AND [[COPY33]], [[C1]]
- ; CHECK: [[SHL31:%[0-9]+]]:_(s32) = G_SHL [[AND33]], [[C1]](s32)
- ; CHECK: [[OR31:%[0-9]+]]:_(s32) = G_OR [[AND32]], [[SHL31]]
- ; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK: [[AND34:%[0-9]+]]:_(s32) = G_AND [[COPY34]], [[C1]]
- ; CHECK: [[SHL32:%[0-9]+]]:_(s32) = G_SHL [[AND34]], [[C2]](s32)
+ ; CHECK: [[SHL31:%[0-9]+]]:_(s32) = G_SHL [[COPY33]], [[C1]](s32)
+ ; CHECK: [[OR31:%[0-9]+]]:_(s32) = G_OR [[COPY32]], [[SHL31]]
+ ; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK: [[SHL32:%[0-9]+]]:_(s32) = G_SHL [[COPY34]], [[C2]](s32)
; CHECK: [[OR32:%[0-9]+]]:_(s32) = G_OR [[OR31]], [[SHL32]]
; CHECK: [[COPY35:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[AND35:%[0-9]+]]:_(s32) = G_AND [[COPY35]], [[C1]]
- ; CHECK: [[SHL33:%[0-9]+]]:_(s32) = G_SHL [[AND35]], [[C3]](s32)
+ ; CHECK: [[SHL33:%[0-9]+]]:_(s32) = G_SHL [[COPY35]], [[C3]](s32)
; CHECK: [[OR33:%[0-9]+]]:_(s32) = G_OR [[OR32]], [[SHL33]]
; CHECK: [[COPY36:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND36:%[0-9]+]]:_(s32) = G_AND [[COPY36]], [[C1]]
- ; CHECK: [[SHL34:%[0-9]+]]:_(s32) = G_SHL [[AND36]], [[C4]](s32)
+ ; CHECK: [[SHL34:%[0-9]+]]:_(s32) = G_SHL [[COPY36]], [[C4]](s32)
; CHECK: [[OR34:%[0-9]+]]:_(s32) = G_OR [[OR33]], [[SHL34]]
; CHECK: [[COPY37:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND37:%[0-9]+]]:_(s32) = G_AND [[COPY37]], [[C1]]
- ; CHECK: [[SHL35:%[0-9]+]]:_(s32) = G_SHL [[AND37]], [[C5]](s32)
+ ; CHECK: [[SHL35:%[0-9]+]]:_(s32) = G_SHL [[COPY37]], [[C5]](s32)
; CHECK: [[OR35:%[0-9]+]]:_(s32) = G_OR [[OR34]], [[SHL35]]
; CHECK: [[COPY38:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND38:%[0-9]+]]:_(s32) = G_AND [[COPY38]], [[C1]]
- ; CHECK: [[SHL36:%[0-9]+]]:_(s32) = G_SHL [[AND38]], [[C6]](s32)
+ ; CHECK: [[SHL36:%[0-9]+]]:_(s32) = G_SHL [[COPY38]], [[C6]](s32)
; CHECK: [[OR36:%[0-9]+]]:_(s32) = G_OR [[OR35]], [[SHL36]]
; CHECK: [[COPY39:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND39:%[0-9]+]]:_(s32) = G_AND [[COPY39]], [[C1]]
- ; CHECK: [[SHL37:%[0-9]+]]:_(s32) = G_SHL [[AND39]], [[C7]](s32)
+ ; CHECK: [[SHL37:%[0-9]+]]:_(s32) = G_SHL [[COPY39]], [[C7]](s32)
; CHECK: [[OR37:%[0-9]+]]:_(s32) = G_OR [[OR36]], [[SHL37]]
; CHECK: [[COPY40:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND40:%[0-9]+]]:_(s32) = G_AND [[COPY40]], [[C1]]
- ; CHECK: [[SHL38:%[0-9]+]]:_(s32) = G_SHL [[AND40]], [[C8]](s32)
+ ; CHECK: [[SHL38:%[0-9]+]]:_(s32) = G_SHL [[COPY40]], [[C8]](s32)
; CHECK: [[OR38:%[0-9]+]]:_(s32) = G_OR [[OR37]], [[SHL38]]
; CHECK: [[COPY41:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND41:%[0-9]+]]:_(s32) = G_AND [[COPY41]], [[C1]]
- ; CHECK: [[SHL39:%[0-9]+]]:_(s32) = G_SHL [[AND41]], [[C9]](s32)
+ ; CHECK: [[SHL39:%[0-9]+]]:_(s32) = G_SHL [[COPY41]], [[C9]](s32)
; CHECK: [[OR39:%[0-9]+]]:_(s32) = G_OR [[OR38]], [[SHL39]]
; CHECK: [[COPY42:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND42:%[0-9]+]]:_(s32) = G_AND [[COPY42]], [[C1]]
- ; CHECK: [[SHL40:%[0-9]+]]:_(s32) = G_SHL [[AND42]], [[C10]](s32)
+ ; CHECK: [[SHL40:%[0-9]+]]:_(s32) = G_SHL [[COPY42]], [[C10]](s32)
; CHECK: [[OR40:%[0-9]+]]:_(s32) = G_OR [[OR39]], [[SHL40]]
; CHECK: [[COPY43:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND43:%[0-9]+]]:_(s32) = G_AND [[COPY43]], [[C1]]
- ; CHECK: [[SHL41:%[0-9]+]]:_(s32) = G_SHL [[AND43]], [[C11]](s32)
+ ; CHECK: [[SHL41:%[0-9]+]]:_(s32) = G_SHL [[COPY43]], [[C11]](s32)
; CHECK: [[OR41:%[0-9]+]]:_(s32) = G_OR [[OR40]], [[SHL41]]
; CHECK: [[COPY44:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND44:%[0-9]+]]:_(s32) = G_AND [[COPY44]], [[C1]]
- ; CHECK: [[SHL42:%[0-9]+]]:_(s32) = G_SHL [[AND44]], [[C12]](s32)
+ ; CHECK: [[SHL42:%[0-9]+]]:_(s32) = G_SHL [[COPY44]], [[C12]](s32)
; CHECK: [[OR42:%[0-9]+]]:_(s32) = G_OR [[OR41]], [[SHL42]]
; CHECK: [[COPY45:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND45:%[0-9]+]]:_(s32) = G_AND [[COPY45]], [[C1]]
- ; CHECK: [[SHL43:%[0-9]+]]:_(s32) = G_SHL [[AND45]], [[C13]](s32)
+ ; CHECK: [[SHL43:%[0-9]+]]:_(s32) = G_SHL [[COPY45]], [[C13]](s32)
; CHECK: [[OR43:%[0-9]+]]:_(s32) = G_OR [[OR42]], [[SHL43]]
; CHECK: [[COPY46:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND46:%[0-9]+]]:_(s32) = G_AND [[COPY46]], [[C1]]
- ; CHECK: [[SHL44:%[0-9]+]]:_(s32) = G_SHL [[AND46]], [[C14]](s32)
+ ; CHECK: [[SHL44:%[0-9]+]]:_(s32) = G_SHL [[COPY46]], [[C14]](s32)
; CHECK: [[OR44:%[0-9]+]]:_(s32) = G_OR [[OR43]], [[SHL44]]
; CHECK: [[COPY47:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND47:%[0-9]+]]:_(s32) = G_AND [[COPY47]], [[C1]]
- ; CHECK: [[SHL45:%[0-9]+]]:_(s32) = G_SHL [[AND47]], [[C15]](s32)
+ ; CHECK: [[SHL45:%[0-9]+]]:_(s32) = G_SHL [[COPY47]], [[C15]](s32)
; CHECK: [[OR45:%[0-9]+]]:_(s32) = G_OR [[OR44]], [[SHL45]]
; CHECK: [[COPY48:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND48:%[0-9]+]]:_(s32) = G_AND [[COPY48]], [[C1]]
- ; CHECK: [[SHL46:%[0-9]+]]:_(s32) = G_SHL [[AND48]], [[C16]](s32)
+ ; CHECK: [[SHL46:%[0-9]+]]:_(s32) = G_SHL [[COPY48]], [[C16]](s32)
; CHECK: [[OR46:%[0-9]+]]:_(s32) = G_OR [[OR45]], [[SHL46]]
; CHECK: [[COPY49:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND49:%[0-9]+]]:_(s32) = G_AND [[COPY49]], [[C1]]
- ; CHECK: [[SHL47:%[0-9]+]]:_(s32) = G_SHL [[AND49]], [[C17]](s32)
+ ; CHECK: [[SHL47:%[0-9]+]]:_(s32) = G_SHL [[COPY49]], [[C17]](s32)
; CHECK: [[OR47:%[0-9]+]]:_(s32) = G_OR [[OR46]], [[SHL47]]
; CHECK: [[COPY50:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND50:%[0-9]+]]:_(s32) = G_AND [[COPY50]], [[C1]]
- ; CHECK: [[SHL48:%[0-9]+]]:_(s32) = G_SHL [[AND50]], [[C18]](s32)
+ ; CHECK: [[SHL48:%[0-9]+]]:_(s32) = G_SHL [[COPY50]], [[C18]](s32)
; CHECK: [[OR48:%[0-9]+]]:_(s32) = G_OR [[OR47]], [[SHL48]]
- ; CHECK: [[COPY51:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; CHECK: [[AND51:%[0-9]+]]:_(s32) = G_AND [[COPY51]], [[C1]]
- ; CHECK: [[SHL49:%[0-9]+]]:_(s32) = G_SHL [[AND51]], [[C19]](s32)
+ ; CHECK: [[COPY51:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK: [[SHL49:%[0-9]+]]:_(s32) = G_SHL [[COPY51]], [[C19]](s32)
; CHECK: [[OR49:%[0-9]+]]:_(s32) = G_OR [[OR48]], [[SHL49]]
; CHECK: [[COPY52:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[AND52:%[0-9]+]]:_(s32) = G_AND [[COPY52]], [[C1]]
- ; CHECK: [[SHL50:%[0-9]+]]:_(s32) = G_SHL [[AND52]], [[C20]](s32)
+ ; CHECK: [[SHL50:%[0-9]+]]:_(s32) = G_SHL [[COPY52]], [[C20]](s32)
; CHECK: [[OR50:%[0-9]+]]:_(s32) = G_OR [[OR49]], [[SHL50]]
; CHECK: [[COPY53:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND53:%[0-9]+]]:_(s32) = G_AND [[COPY53]], [[C1]]
- ; CHECK: [[SHL51:%[0-9]+]]:_(s32) = G_SHL [[AND53]], [[C21]](s32)
+ ; CHECK: [[SHL51:%[0-9]+]]:_(s32) = G_SHL [[COPY53]], [[C21]](s32)
; CHECK: [[OR51:%[0-9]+]]:_(s32) = G_OR [[OR50]], [[SHL51]]
; CHECK: [[COPY54:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND54:%[0-9]+]]:_(s32) = G_AND [[COPY54]], [[C1]]
- ; CHECK: [[SHL52:%[0-9]+]]:_(s32) = G_SHL [[AND54]], [[C22]](s32)
+ ; CHECK: [[SHL52:%[0-9]+]]:_(s32) = G_SHL [[COPY54]], [[C22]](s32)
; CHECK: [[OR52:%[0-9]+]]:_(s32) = G_OR [[OR51]], [[SHL52]]
; CHECK: [[COPY55:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND55:%[0-9]+]]:_(s32) = G_AND [[COPY55]], [[C1]]
- ; CHECK: [[SHL53:%[0-9]+]]:_(s32) = G_SHL [[AND55]], [[C23]](s32)
+ ; CHECK: [[SHL53:%[0-9]+]]:_(s32) = G_SHL [[COPY55]], [[C23]](s32)
; CHECK: [[OR53:%[0-9]+]]:_(s32) = G_OR [[OR52]], [[SHL53]]
; CHECK: [[COPY56:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND56:%[0-9]+]]:_(s32) = G_AND [[COPY56]], [[C1]]
- ; CHECK: [[SHL54:%[0-9]+]]:_(s32) = G_SHL [[AND56]], [[C24]](s32)
+ ; CHECK: [[SHL54:%[0-9]+]]:_(s32) = G_SHL [[COPY56]], [[C24]](s32)
; CHECK: [[OR54:%[0-9]+]]:_(s32) = G_OR [[OR53]], [[SHL54]]
; CHECK: [[COPY57:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND57:%[0-9]+]]:_(s32) = G_AND [[COPY57]], [[C1]]
- ; CHECK: [[SHL55:%[0-9]+]]:_(s32) = G_SHL [[AND57]], [[C25]](s32)
+ ; CHECK: [[SHL55:%[0-9]+]]:_(s32) = G_SHL [[COPY57]], [[C25]](s32)
; CHECK: [[OR55:%[0-9]+]]:_(s32) = G_OR [[OR54]], [[SHL55]]
; CHECK: [[COPY58:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND58:%[0-9]+]]:_(s32) = G_AND [[COPY58]], [[C1]]
- ; CHECK: [[SHL56:%[0-9]+]]:_(s32) = G_SHL [[AND58]], [[C26]](s32)
+ ; CHECK: [[SHL56:%[0-9]+]]:_(s32) = G_SHL [[COPY58]], [[C26]](s32)
; CHECK: [[OR56:%[0-9]+]]:_(s32) = G_OR [[OR55]], [[SHL56]]
; CHECK: [[COPY59:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND59:%[0-9]+]]:_(s32) = G_AND [[COPY59]], [[C1]]
- ; CHECK: [[SHL57:%[0-9]+]]:_(s32) = G_SHL [[AND59]], [[C27]](s32)
+ ; CHECK: [[SHL57:%[0-9]+]]:_(s32) = G_SHL [[COPY59]], [[C27]](s32)
; CHECK: [[OR57:%[0-9]+]]:_(s32) = G_OR [[OR56]], [[SHL57]]
; CHECK: [[COPY60:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND60:%[0-9]+]]:_(s32) = G_AND [[COPY60]], [[C1]]
- ; CHECK: [[SHL58:%[0-9]+]]:_(s32) = G_SHL [[AND60]], [[C28]](s32)
+ ; CHECK: [[SHL58:%[0-9]+]]:_(s32) = G_SHL [[COPY60]], [[C28]](s32)
; CHECK: [[OR58:%[0-9]+]]:_(s32) = G_OR [[OR57]], [[SHL58]]
; CHECK: [[COPY61:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND61:%[0-9]+]]:_(s32) = G_AND [[COPY61]], [[C1]]
- ; CHECK: [[SHL59:%[0-9]+]]:_(s32) = G_SHL [[AND61]], [[C29]](s32)
+ ; CHECK: [[SHL59:%[0-9]+]]:_(s32) = G_SHL [[COPY61]], [[C29]](s32)
; CHECK: [[OR59:%[0-9]+]]:_(s32) = G_OR [[OR58]], [[SHL59]]
; CHECK: [[COPY62:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND62:%[0-9]+]]:_(s32) = G_AND [[COPY62]], [[C1]]
- ; CHECK: [[SHL60:%[0-9]+]]:_(s32) = G_SHL [[AND62]], [[C30]](s32)
+ ; CHECK: [[SHL60:%[0-9]+]]:_(s32) = G_SHL [[COPY62]], [[C30]](s32)
; CHECK: [[OR60:%[0-9]+]]:_(s32) = G_OR [[OR59]], [[SHL60]]
; CHECK: [[COPY63:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND63:%[0-9]+]]:_(s32) = G_AND [[COPY63]], [[C1]]
- ; CHECK: [[SHL61:%[0-9]+]]:_(s32) = G_SHL [[AND63]], [[C31]](s32)
+ ; CHECK: [[SHL61:%[0-9]+]]:_(s32) = G_SHL [[COPY63]], [[C31]](s32)
; CHECK: [[OR61:%[0-9]+]]:_(s32) = G_OR [[OR60]], [[SHL61]]
; CHECK: [[COPY64:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND64:%[0-9]+]]:_(s32) = G_AND [[COPY64]], [[C1]]
; CHECK: [[COPY65:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND65:%[0-9]+]]:_(s32) = G_AND [[COPY65]], [[C1]]
- ; CHECK: [[SHL62:%[0-9]+]]:_(s32) = G_SHL [[AND65]], [[C1]](s32)
- ; CHECK: [[OR62:%[0-9]+]]:_(s32) = G_OR [[AND64]], [[SHL62]]
+ ; CHECK: [[SHL62:%[0-9]+]]:_(s32) = G_SHL [[COPY65]], [[C1]](s32)
+ ; CHECK: [[OR62:%[0-9]+]]:_(s32) = G_OR [[COPY64]], [[SHL62]]
; CHECK: [[COPY66:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND66:%[0-9]+]]:_(s32) = G_AND [[COPY66]], [[C1]]
- ; CHECK: [[SHL63:%[0-9]+]]:_(s32) = G_SHL [[AND66]], [[C2]](s32)
+ ; CHECK: [[SHL63:%[0-9]+]]:_(s32) = G_SHL [[COPY66]], [[C2]](s32)
; CHECK: [[OR63:%[0-9]+]]:_(s32) = G_OR [[OR62]], [[SHL63]]
; CHECK: [[COPY67:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND67:%[0-9]+]]:_(s32) = G_AND [[COPY67]], [[C1]]
- ; CHECK: [[SHL64:%[0-9]+]]:_(s32) = G_SHL [[AND67]], [[C3]](s32)
+ ; CHECK: [[SHL64:%[0-9]+]]:_(s32) = G_SHL [[COPY67]], [[C3]](s32)
; CHECK: [[OR64:%[0-9]+]]:_(s32) = G_OR [[OR63]], [[SHL64]]
; CHECK: [[COPY68:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SHL65:%[0-9]+]]:_(s32) = G_SHL [[COPY68]], [[C4]](s32)
@@ -1132,10 +1009,8 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -1159,21 +1034,17 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
- ; CHECK: $vgpr0_vgpr1 = COPY [[COPY6]](s64)
+ ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
index 9cd355c90e49d..1d41cba109dcc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
@@ -217,12 +217,9 @@ body: |
; GFX6-LABEL: name: test_mul_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
+ ; GFX6: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; GFX6: $vgpr0 = COPY [[AND]](s32)
; GFX8-LABEL: name: test_mul_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
@@ -263,17 +260,11 @@ body: |
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[COPY4]], [[COPY5]]
+ ; GFX6: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[BITCAST]], [[BITCAST1]]
+ ; GFX6: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[LSHR1]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[MUL1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C1]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C1]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -321,17 +312,11 @@ body: |
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX6: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY6]], [[COPY7]]
+ ; GFX6: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY3]]
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[MUL]](s32)
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; GFX6: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[COPY8]], [[COPY9]]
+ ; GFX6: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY4]]
; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[MUL1]](s32)
- ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; GFX6: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY10]], [[COPY11]]
+ ; GFX6: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY5]]
; GFX6: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[MUL2]](s32)
; GFX6: S_ENDPGM 0, implicit [[TRUNC]](s16), implicit [[TRUNC1]](s16), implicit [[TRUNC2]](s16)
; GFX8-LABEL: name: test_mul_v3s16
@@ -358,19 +343,13 @@ body: |
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
+ ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY6]](s32)
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[DEF]](s32)
; GFX9: [[MUL:%[0-9]+]]:_(<2 x s16>) = G_MUL [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]]
; GFX9: [[MUL1:%[0-9]+]]:_(<2 x s16>) = G_MUL [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]]
; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[MUL]](<2 x s16>)
@@ -421,30 +400,18 @@ body: |
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX6: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX6: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[COPY4]], [[COPY5]]
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX6: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY6]], [[COPY7]]
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[COPY8]], [[COPY9]]
+ ; GFX6: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[BITCAST]], [[BITCAST2]]
+ ; GFX6: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[LSHR]], [[LSHR2]]
+ ; GFX6: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[BITCAST1]], [[BITCAST3]]
+ ; GFX6: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[LSHR1]], [[LSHR3]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[MUL1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C1]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C1]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[MUL2]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[MUL3]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL2]], [[C1]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[MUL3]], [[C1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -512,27 +479,18 @@ body: |
; GFX6-LABEL: name: test_mul_s24
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
+ ; GFX6: $vgpr0 = COPY [[MUL]](s32)
; GFX8-LABEL: name: test_mul_s24
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX8: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX8: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
+ ; GFX8: $vgpr0 = COPY [[MUL]](s32)
; GFX9-LABEL: name: test_mul_s24
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
+ ; GFX9: $vgpr0 = COPY [[MUL]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s24) = G_TRUNC %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
index 87a6f7a2ce694..d690290e8503e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
@@ -60,9 +60,7 @@ body: |
; CHECK: [[OR1:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP3]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[OR1]](s1)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
@@ -100,10 +98,7 @@ body: |
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[OR1]](s1)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[OR2]](s1)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
@@ -186,11 +181,8 @@ body: |
; CHECK-LABEL: name: test_or_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
+ ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]]
+ ; CHECK: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s7) = G_TRUNC %0
@@ -209,11 +201,8 @@ body: |
; CHECK-LABEL: name: test_or_s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
+ ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]]
+ ; CHECK: $vgpr0 = COPY [[OR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s8) = G_TRUNC %0
@@ -278,11 +267,8 @@ body: |
; CHECK-LABEL: name: test_or_s48
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[OR]](s64)
- ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[COPY1]]
+ ; CHECK: $vgpr0_vgpr1 = COPY [[OR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s48) = G_TRUNC %0
@@ -457,24 +443,18 @@ body: |
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
@@ -544,24 +524,18 @@ body: |
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV19]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
@@ -630,27 +604,11 @@ body: |
; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<4 x s32>)
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[COPY4]], [[COPY5]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[COPY6]], [[COPY7]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[OR1]](s32)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[OR3]](s32)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
+ ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[UV4]]
+ ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[UV1]], [[UV5]]
+ ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[UV2]], [[UV6]]
+ ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[UV3]], [[UV7]]
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[OR]](s32), [[OR1]](s32), [[OR2]](s32), [[OR3]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
%0:_(<4 x s8>) = G_IMPLICIT_DEF
%1:_(<4 x s8>) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
index b000b2c2abf64..21b89ea614f9f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
@@ -69,17 +69,11 @@ body: |
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY5]]
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[BITCAST]], [[BITCAST1]]
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[LSHR1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C2]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -145,25 +139,16 @@ body: |
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C1]](s32)
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY5]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY6]], [[COPY7]]
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[BITCAST]], [[BITCAST2]]
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[LSHR2]]
+ ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[BITCAST1]], [[BITCAST3]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C2]]
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C2]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C2]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
@@ -189,24 +174,18 @@ body: |
; CHECK: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[UV9]](<2 x s16>)
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C4]](s32)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C5]]
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C5]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C5]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C5]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C4]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL2]]
; CHECK: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C5]]
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C5]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C5]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST8]], [[C5]]
; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C4]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL3]]
; CHECK: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C5]]
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C5]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C5]]
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST9]], [[C5]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C4]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL4]]
; CHECK: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
@@ -268,30 +247,18 @@ body: |
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C1]](s32)
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY5]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY6]], [[COPY7]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[COPY8]], [[COPY9]]
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[BITCAST]], [[BITCAST2]]
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[LSHR2]]
+ ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[BITCAST1]], [[BITCAST3]]
+ ; CHECK: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR1]], [[LSHR3]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C2]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C2]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C2]]
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[ADD3]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C2]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C2]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD3]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -1596,15 +1563,11 @@ body: |
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND]](s32), [[AND1]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND2]](s32), [[AND3]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]
; CHECK: G_BRCOND [[ICMP2]](s1), %bb.1
@@ -1617,15 +1580,11 @@ body: |
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY2]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C3]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C4]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C4]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C4]]
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND4]](s32), [[AND5]]
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C4]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C4]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C4]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C4]]
; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[AND6]](s32), [[AND7]]
; CHECK: G_BR %bb.2
; CHECK: bb.2:
@@ -1634,10 +1593,8 @@ body: |
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s1)
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C5]]
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C5]]
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C5]]
+ ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C5]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND8]](s32), [[AND9]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptr-add.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptr-add.mir
index e014376446a94..2a575611cdf8b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptr-add.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptr-add.mir
@@ -251,8 +251,7 @@ body: |
; CHECK-LABEL: name: test_gep_local_i16_idx
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[COPY]], [[SEXT_INREG]](s32)
; CHECK: $vgpr0 = COPY [[PTR_ADD]](p3)
%0:_(p3) = COPY $vgpr0
@@ -341,11 +340,9 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p3) = G_PTR_ADD [[UV]], [[SEXT_INREG]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p3) = G_PTR_ADD [[UV1]], [[SEXT_INREG1]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p3>) = G_BUILD_VECTOR [[PTR_ADD]](p3), [[PTR_ADD1]](p3)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x p3>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrmask.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrmask.mir
index 3cf5aeef84318..1e40953f2a782 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrmask.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrmask.mir
@@ -159,8 +159,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[PTRMASK:%[0-9]+]]:_(p3) = G_PTRMASK [[COPY]], [[AND]](s32)
; CHECK: $vgpr0 = COPY [[PTRMASK]](p3)
%0:_(p3) = COPY $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sadde.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sadde.mir
index 01d616d57d1fc..7bf1b20c06d53 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sadde.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sadde.mir
@@ -69,17 +69,13 @@ body: |
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY %13(s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %13, 16
; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[SEXT_INREG]], [[SEXT_INREG1]], [[ICMP]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UADDE]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UADDE]], 16
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UADDE]](s32), [[SEXT_INREG2]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UADDE]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP1]](s1)
- ; CHECK: $vgpr0 = COPY [[COPY6]](s32)
+ ; CHECK: $vgpr0 = COPY [[UADDE]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
index 28ac01356521d..c36dd46a39877 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
@@ -10,24 +10,17 @@ body: |
; CHECK-LABEL: name: test_saddo_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 7
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 7
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 7
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 7
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 7
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[SEXT_INREG3]]
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 7
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[COPY2]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C1]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[XOR]](s1)
; CHECK: $vgpr0 = COPY [[AND]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
@@ -51,22 +44,16 @@ body: |
; CHECK-LABEL: name: test_saddo_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 16
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 16
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[C]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[XOR]](s1)
- ; CHECK: $vgpr0 = COPY [[COPY7]](s32)
+ ; CHECK: $vgpr0 = COPY [[ADD]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -147,51 +134,37 @@ body: |
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY5]]
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[BITCAST]], [[BITCAST1]]
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[LSHR1]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 16
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 16
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 16
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST3]], 16
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY10]], 16
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY11]], 16
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD1]], 16
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 16
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[SEXT_INREG3]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY12]], 16
+ ; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST4]], 16
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG4]](s32), [[COPY13]]
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY14]], 16
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG4]](s32), [[COPY2]]
+ ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR3]], 16
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG5]](s32), [[C2]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP2]], [[ICMP]]
; CHECK: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP3]], [[ICMP1]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR1]](s1)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND2]](s32), [[AND3]](s32)
; CHECK: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
; CHECK: $vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<2 x s32>)
@@ -222,15 +195,9 @@ body: |
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY5]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY6]], [[COPY7]]
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[BITCAST]], [[BITCAST2]]
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[LSHR2]]
+ ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[BITCAST1]], [[BITCAST3]]
; CHECK: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; CHECK: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; CHECK: [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>), [[UV8:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
@@ -238,37 +205,28 @@ body: |
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; CHECK: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 16
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 16
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 16
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST4]], 16
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY10]], 16
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY11]], 16
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD1]], 16
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR4]], 16
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[SEXT_INREG3]]
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32)
- ; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY12]], 16
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY13]], 16
+ ; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD2]], 16
+ ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST5]], 16
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG4]](s32), [[SEXT_INREG5]]
; CHECK: [[UV9:%[0-9]+]]:_(<2 x s16>), [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<6 x s16>)
; CHECK: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[UV9]](<2 x s16>)
; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; CHECK: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV10]](<2 x s16>)
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY14]], 16
+ ; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST6]], 16
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG6]](s32), [[COPY15]]
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY16]], 16
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG7]](s32), [[COPY17]]
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY18]], 16
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG6]](s32), [[COPY2]]
+ ; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR6]], 16
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG7]](s32), [[COPY3]]
+ ; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST7]], 16
; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG8]](s32), [[C1]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP3]], [[ICMP]]
; CHECK: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP4]], [[ICMP1]]
@@ -284,35 +242,26 @@ body: |
; CHECK: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[UV13]](<2 x s16>)
; CHECK: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C2]]
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C2]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C2]]
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C2]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C2]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST8]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C2]]
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C2]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C2]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST9]], [[C2]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST10]](<2 x s16>), [[BITCAST11]](<2 x s16>), [[BITCAST12]](<2 x s16>)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C3]]
- ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C3]]
- ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C3]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C3]]
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND6]](s32), [[AND7]](s32), [[AND8]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
@@ -348,30 +297,18 @@ body: |
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY5]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY6]], [[COPY7]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[COPY8]], [[COPY9]]
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[BITCAST]], [[BITCAST2]]
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR]], [[LSHR2]]
+ ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[BITCAST1]], [[BITCAST3]]
+ ; CHECK: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR1]], [[LSHR3]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[ADD3]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD3]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -381,46 +318,34 @@ body: |
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; CHECK: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY14]], 16
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY15]], 16
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 16
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST6]], 16
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[ADD1]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY16]], 16
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY17]], 16
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD1]], 16
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR4]], 16
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[SEXT_INREG3]]
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32)
- ; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY18]], 16
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY19]], 16
+ ; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD2]], 16
+ ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST7]], 16
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG4]](s32), [[SEXT_INREG5]]
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[ADD3]](s32)
- ; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY20]], 16
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY21]], 16
+ ; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD3]], 16
+ ; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR5]], 16
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG6]](s32), [[SEXT_INREG7]]
; CHECK: [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
; CHECK: [[BITCAST8:%[0-9]+]]:_(s32) = G_BITCAST [[UV6]](<2 x s16>)
; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST8]], [[C]](s32)
; CHECK: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C]](s32)
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
- ; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY22]], 16
+ ; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST8]], 16
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG8]](s32), [[COPY23]]
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY24]], 16
- ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG9]](s32), [[COPY25]]
- ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
- ; CHECK: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY26]], 16
- ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG10]](s32), [[COPY27]]
- ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CHECK: [[SEXT_INREG11:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY28]], 16
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG8]](s32), [[COPY2]]
+ ; CHECK: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR6]], 16
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG9]](s32), [[COPY3]]
+ ; CHECK: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST9]], 16
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG10]](s32), [[COPY4]]
+ ; CHECK: [[SEXT_INREG11:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR7]], 16
; CHECK: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG11]](s32), [[C2]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP4]], [[ICMP]]
; CHECK: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP5]], [[ICMP1]]
@@ -431,14 +356,10 @@ body: |
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR2]](s1)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR3]](s1)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C3]]
- ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C3]]
- ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C3]]
- ; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C3]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C3]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C3]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND4]](s32), [[AND5]](s32), [[AND6]](s32), [[AND7]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
; CHECK: $vgpr2_vgpr3_vgpr4_vgpr5 = COPY [[BUILD_VECTOR]](<4 x s32>)
@@ -476,10 +397,8 @@ body: |
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR1]](s1)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; CHECK: $vgpr2_vgpr3 = COPY [[BUILD_VECTOR1]](<2 x s32>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
index 16c94a78232cc..e0535f0f64601 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
@@ -13,11 +13,9 @@ body: |
; GFX6-LABEL: name: saddsat_s7
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -29,8 +27,7 @@ body: |
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ADD]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[ASHR]](s32)
; GFX8-LABEL: name: saddsat_s7
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -82,11 +79,9 @@ body: |
; GFX6-LABEL: name: saddsat_s8
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -98,8 +93,7 @@ body: |
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ADD]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[ASHR]](s32)
; GFX8-LABEL: name: saddsat_s8
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -160,10 +154,8 @@ body: |
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C2]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C2]](s32)
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; GFX6: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -175,10 +167,8 @@ body: |
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ADD]], [[C2]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]](s32)
- ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C2]](s32)
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C2]](s32)
+ ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR3]], [[C2]](s32)
; GFX6: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SHL2]], [[C5]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SMAX2]]
; GFX6: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SHL2]], [[C5]]
@@ -190,11 +180,10 @@ body: |
; GFX6: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C6]]
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY6]](s32)
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C7]]
+ ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY2]](s32)
; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -240,10 +229,8 @@ body: |
; GFX8: [[ADD1:%[0-9]+]]:_(s16) = G_ADD [[SHL2]], [[SMIN3]]
; GFX8: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ADD1]], [[C3]](s16)
; GFX8: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX8: [[COPY2:%[0-9]+]]:_(s16) = COPY [[ASHR]](s16)
- ; GFX8: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C7]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
- ; GFX8: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C7]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s16) = G_AND [[ASHR]], [[C7]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s16) = G_AND [[ASHR1]], [[C7]]
; GFX8: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16)
; GFX8: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -260,15 +247,11 @@ body: |
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[LSHR]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[LSHR3]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY6]](s32)
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY2]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[SHL1:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[SADDSAT:%[0-9]+]]:_(<2 x s16>) = G_SADDSAT [[SHL]], [[SHL1]]
@@ -278,10 +261,8 @@ body: |
; GFX9: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR6]](s32)
; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX9: [[COPY7:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
- ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
- ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C4]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C4]]
; GFX9: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16)
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL2]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -307,11 +288,9 @@ body: |
; GFX6-LABEL: name: saddsat_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -323,8 +302,7 @@ body: |
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ADD]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[ASHR]](s32)
; GFX8-LABEL: name: saddsat_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -373,10 +351,8 @@ body: |
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -388,10 +364,8 @@ body: |
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ADD]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
- ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
; GFX6: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SHL2]], [[C3]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX2]]
; GFX6: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SHL2]], [[C3]]
@@ -401,10 +375,8 @@ body: |
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SHL2]], [[SMIN3]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ADD1]], [[C]](s32)
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C4]]
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C4]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C4]]
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL4]]
; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -474,10 +446,8 @@ body: |
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -489,10 +459,8 @@ body: |
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ADD]], [[C]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
- ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[BITCAST3]], [[C]](s32)
; GFX6: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SHL2]], [[C3]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX2]]
; GFX6: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SHL2]], [[C3]]
@@ -501,10 +469,8 @@ body: |
; GFX6: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB2]]
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SHL2]], [[SMIN3]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ADD1]], [[C]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)
- ; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32)
+ ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[C]](s32)
+ ; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[LSHR3]], [[C]](s32)
; GFX6: [[SMAX4:%[0-9]+]]:_(s32) = G_SMAX [[SHL4]], [[C3]]
; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX4]]
; GFX6: [[SMIN4:%[0-9]+]]:_(s32) = G_SMIN [[SHL4]], [[C3]]
@@ -523,24 +489,18 @@ body: |
; GFX6: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C4]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C4]]
; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL6]]
; GFX6: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[ASHR2]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C4]]
- ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C4]]
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ASHR2]], [[C4]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C4]]
; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL7]]
; GFX6: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C4]]
- ; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C4]]
+ ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C4]]
+ ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C4]]
; GFX6: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX6: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL8]]
; GFX6: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -605,15 +565,12 @@ body: |
; GFX8: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ADD2]](s16)
; GFX8: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C4]]
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; GFX8: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C4]]
+ ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C4]]
; GFX8: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; GFX8: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; GFX8: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -627,23 +584,17 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[DEF]](s32)
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[BITCAST3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR3]](s32), [[DEF]](s32)
; GFX9: [[SADDSAT:%[0-9]+]]:_(<2 x s16>) = G_SADDSAT [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]]
; GFX9: [[SADDSAT1:%[0-9]+]]:_(<2 x s16>) = G_SADDSAT [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]]
; GFX9: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@@ -657,15 +608,9 @@ body: |
; GFX9: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; GFX9: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; GFX9: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST4]](s32), [[LSHR4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST5]](s32), [[BITCAST6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR6]](s32), [[BITCAST7]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC4]](<2 x s16>), [[BUILD_VECTOR_TRUNC5]](<2 x s16>), [[BUILD_VECTOR_TRUNC6]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
@@ -696,10 +641,8 @@ body: |
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[BITCAST2]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
@@ -711,10 +654,8 @@ body: |
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ADD]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
- ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[C]](s32)
; GFX6: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SHL2]], [[C3]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX2]]
; GFX6: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SHL2]], [[C3]]
@@ -723,10 +664,8 @@ body: |
; GFX6: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB2]]
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SHL2]], [[SMIN3]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ADD1]], [[C]](s32)
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32)
- ; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C]](s32)
+ ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[C]](s32)
+ ; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[BITCAST3]], [[C]](s32)
; GFX6: [[SMAX4:%[0-9]+]]:_(s32) = G_SMAX [[SHL4]], [[C3]]
; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX4]]
; GFX6: [[SMIN4:%[0-9]+]]:_(s32) = G_SMIN [[SHL4]], [[C3]]
@@ -735,10 +674,8 @@ body: |
; GFX6: [[SMIN5:%[0-9]+]]:_(s32) = G_SMIN [[SMAX5]], [[SUB4]]
; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SHL4]], [[SMIN5]]
; GFX6: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[ADD2]], [[C]](s32)
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C]](s32)
- ; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C]](s32)
+ ; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
+ ; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[LSHR3]], [[C]](s32)
; GFX6: [[SMAX6:%[0-9]+]]:_(s32) = G_SMAX [[SHL6]], [[C3]]
; GFX6: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX6]]
; GFX6: [[SMIN6:%[0-9]+]]:_(s32) = G_SMIN [[SHL6]], [[C3]]
@@ -748,17 +685,13 @@ body: |
; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[SHL6]], [[SMIN7]]
; GFX6: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[ADD3]], [[C]](s32)
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C4]]
- ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C4]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C4]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C4]]
; GFX6: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL8]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[ASHR2]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C4]]
- ; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[ASHR3]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C4]]
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ASHR2]], [[C4]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ASHR3]], [[C4]]
; GFX6: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL9]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
index dae44bac84503..660af6f3a023d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
@@ -1933,10 +1933,8 @@ body: |
; GFX6-LABEL: name: test_sdiv_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
+ ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -1969,15 +1967,12 @@ body: |
; GFX6: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX6: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT2]], [[XOR2]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[XOR3]], [[XOR2]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB3]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[SUB3]](s32)
; GFX8-LABEL: name: test_sdiv_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -2010,15 +2005,12 @@ body: |
; GFX8: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX8: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT2]], [[XOR2]]
; GFX8: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[XOR3]], [[XOR2]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB3]](s32)
- ; GFX8: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX8: $vgpr0 = COPY [[SUB3]](s32)
; GFX9-LABEL: name: test_sdiv_s16
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -2051,8 +2043,7 @@ body: |
; GFX9: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX9: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT2]], [[XOR2]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[XOR3]], [[XOR2]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB3]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX9: $vgpr0 = COPY [[SUB3]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0
@@ -2076,10 +2067,8 @@ body: |
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
+ ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C1]](s32)
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C1]](s32)
@@ -2112,10 +2101,8 @@ body: |
; GFX6: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX6: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT2]], [[XOR2]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[XOR3]], [[XOR2]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
+ ; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 16
; GFX6: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[C1]](s32)
; GFX6: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s32)
; GFX6: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG2]], [[ASHR2]]
@@ -2146,10 +2133,8 @@ body: |
; GFX6: [[XOR7:%[0-9]+]]:_(s32) = G_XOR [[SELECT5]], [[XOR6]]
; GFX6: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[XOR7]], [[XOR6]]
; GFX6: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB3]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C6]]
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SUB7]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C6]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB3]], [[C6]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB7]], [[C6]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -2162,10 +2147,8 @@ body: |
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C1]](s32)
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C1]](s32)
@@ -2198,10 +2181,8 @@ body: |
; GFX8: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX8: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT2]], [[XOR2]]
; GFX8: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[XOR3]], [[XOR2]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
- ; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; GFX8: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
+ ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 16
; GFX8: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[C1]](s32)
; GFX8: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s32)
; GFX8: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG2]], [[ASHR2]]
@@ -2232,10 +2213,8 @@ body: |
; GFX8: [[XOR7:%[0-9]+]]:_(s32) = G_XOR [[SELECT5]], [[XOR6]]
; GFX8: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[XOR7]], [[XOR6]]
; GFX8: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB3]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C6]]
- ; GFX8: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SUB7]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C6]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB3]], [[C6]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB7]], [[C6]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -2248,10 +2227,8 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C1]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C1]](s32)
@@ -2284,10 +2261,8 @@ body: |
; GFX9: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX9: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT2]], [[XOR2]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[XOR3]], [[XOR2]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
+ ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 16
; GFX9: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[C1]](s32)
; GFX9: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s32)
; GFX9: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG2]], [[ASHR2]]
@@ -2317,9 +2292,7 @@ body: |
; GFX9: [[XOR6:%[0-9]+]]:_(s32) = G_XOR [[ASHR2]], [[ASHR3]]
; GFX9: [[XOR7:%[0-9]+]]:_(s32) = G_XOR [[SELECT5]], [[XOR6]]
; GFX9: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[XOR7]], [[XOR6]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB3]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SUB7]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[SUB3]](s32), [[SUB7]](s32)
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
@@ -2336,10 +2309,8 @@ body: |
; GFX6-LABEL: name: test_sdiv_s7
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 7
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 7
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
+ ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 7
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -2372,15 +2343,12 @@ body: |
; GFX6: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX6: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT2]], [[XOR2]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[XOR3]], [[XOR2]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB3]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[SUB3]](s32)
; GFX8-LABEL: name: test_sdiv_s7
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 7
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 7
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 7
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -2413,15 +2381,12 @@ body: |
; GFX8: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX8: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT2]], [[XOR2]]
; GFX8: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[XOR3]], [[XOR2]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB3]](s32)
- ; GFX8: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX8: $vgpr0 = COPY [[SUB3]](s32)
; GFX9-LABEL: name: test_sdiv_s7
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 7
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 7
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 7
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -2454,8 +2419,7 @@ body: |
; GFX9: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX9: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT2]], [[XOR2]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[XOR3]], [[XOR2]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB3]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX9: $vgpr0 = COPY [[SUB3]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s7) = G_TRUNC %0
@@ -2474,10 +2438,8 @@ body: |
; GFX6-LABEL: name: test_sdiv_s17
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 17
+ ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 17
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -2510,15 +2472,12 @@ body: |
; GFX6: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX6: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT2]], [[XOR2]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[XOR3]], [[XOR2]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB3]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[SUB3]](s32)
; GFX8-LABEL: name: test_sdiv_s17
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 17
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 17
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -2551,15 +2510,12 @@ body: |
; GFX8: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX8: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT2]], [[XOR2]]
; GFX8: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[XOR3]], [[XOR2]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB3]](s32)
- ; GFX8: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX8: $vgpr0 = COPY [[SUB3]](s32)
; GFX9-LABEL: name: test_sdiv_s17
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 17
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 17
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -2592,8 +2548,7 @@ body: |
; GFX9: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[ASHR]], [[ASHR1]]
; GFX9: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SELECT2]], [[XOR2]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[XOR3]], [[XOR2]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB3]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX9: $vgpr0 = COPY [[SUB3]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s17) = G_TRUNC %0
@@ -2612,10 +2567,8 @@ body: |
; GFX6-LABEL: name: test_sdiv_s33
; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX6: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; GFX6: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 33
- ; GFX6: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY3]], 33
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 33
+ ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 33
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX6: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -2787,15 +2740,12 @@ body: |
; GFX6: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV26]], [[UV28]]
; GFX6: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV27]], [[UV29]], [[USUBO9]]
; GFX6: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO8]](s32), [[USUBE12]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s64) = COPY [[MV5]](s64)
- ; GFX6: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; GFX6: $vgpr0_vgpr1 = COPY [[MV5]](s64)
; GFX8-LABEL: name: test_sdiv_s33
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; GFX8: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 33
- ; GFX8: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY3]], 33
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 33
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 33
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX8: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -2967,15 +2917,12 @@ body: |
; GFX8: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV26]], [[UV28]]
; GFX8: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV27]], [[UV29]], [[USUBO9]]
; GFX8: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO8]](s32), [[USUBE12]](s32)
- ; GFX8: [[COPY4:%[0-9]+]]:_(s64) = COPY [[MV5]](s64)
- ; GFX8: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; GFX8: $vgpr0_vgpr1 = COPY [[MV5]](s64)
; GFX9-LABEL: name: test_sdiv_s33
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; GFX9: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 33
- ; GFX9: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY3]], 33
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 33
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 33
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -3147,8 +3094,7 @@ body: |
; GFX9: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV26]], [[UV28]]
; GFX9: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV27]], [[UV29]], [[USUBO9]]
; GFX9: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO8]](s32), [[USUBE12]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s64) = COPY [[MV5]](s64)
- ; GFX9: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; GFX9: $vgpr0_vgpr1 = COPY [[MV5]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s33) = G_TRUNC %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
index 1f9ef971aeb60..3e582f23bc965 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
@@ -60,11 +60,8 @@ body: |
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[C1]](s64)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[C2]](s64)
- ; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[SELECT]](s64)
- ; CHECK: $vgpr0_vgpr1 = COPY [[COPY3]](s64)
+ ; CHECK: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
+ ; CHECK: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
%0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = COPY $vgpr0
@@ -236,9 +233,7 @@ body: |
; CHECK: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[TRUNC2]], [[TRUNC3]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT1]](s16)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 0
@@ -338,11 +333,7 @@ body: |
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT1]](s16)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT2]](s16)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT3]](s16)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32), [[ANYEXT3]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 0
@@ -412,24 +403,18 @@ body: |
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C2]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C2]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C2]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C2]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C2]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -1251,10 +1236,7 @@ body: |
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT1]](s16)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT2]](s16)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
@@ -1320,15 +1302,12 @@ body: |
; CHECK: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[SELECT2]](s16)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; CHECK: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; CHECK: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -1413,10 +1392,8 @@ body: |
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT1]](s16)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT4]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT5]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
@@ -1471,12 +1448,9 @@ body: |
; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT1]](s16)
; CHECK: [[ANYEXT8:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT2]](s16)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT6]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT7]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ANYEXT8]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT6]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT7]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT8]], [[C]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
index 6d6e352cd78f0..6f55ff6e1e496 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
@@ -311,8 +311,7 @@ body: |
; GFX9-LABEL: name: test_sext_inreg_s16_1
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX9: S_ENDPGM 0, implicit [[TRUNC]](s16)
; GFX8-LABEL: name: test_sext_inreg_s16_1
@@ -324,8 +323,7 @@ body: |
; GFX8: S_ENDPGM 0, implicit [[ASHR]](s16)
; GFX6-LABEL: name: test_sext_inreg_s16_1
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX6: S_ENDPGM 0, implicit [[TRUNC]](s16)
%0:_(s32) = COPY $vgpr0
@@ -343,8 +341,7 @@ body: |
; GFX9-LABEL: name: test_sext_inreg_s16_15
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 15
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 15
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX9: S_ENDPGM 0, implicit [[TRUNC]](s16)
; GFX8-LABEL: name: test_sext_inreg_s16_15
@@ -356,8 +353,7 @@ body: |
; GFX8: S_ENDPGM 0, implicit [[ASHR]](s16)
; GFX6-LABEL: name: test_sext_inreg_s16_15
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 15
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 15
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
; GFX6: S_ENDPGM 0, implicit [[TRUNC]](s16)
%0:_(s32) = COPY $vgpr0
@@ -670,15 +666,11 @@ body: |
; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 1
+ ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 1
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG]], [[C1]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG1]], [[C1]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -701,26 +693,23 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[DEF]](s32)
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[C1]](s32)
+ ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[C1]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[ASHR:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[SHL]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
; GFX9: [[SHL1:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]](<2 x s16>)
; GFX9: [[ASHR1:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[SHL1]], [[BUILD_VECTOR_TRUNC3]](<2 x s16>)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
+ ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
; GFX9: [[SHL2:%[0-9]+]]:_(<2 x s16>) = G_SHL [[DEF1]], [[BUILD_VECTOR_TRUNC4]](<2 x s16>)
; GFX9: [[ASHR2:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[SHL2]], [[BUILD_VECTOR_TRUNC4]](<2 x s16>)
; GFX9: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@@ -734,15 +723,9 @@ body: |
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; GFX9: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY13]](s32), [[COPY14]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST2]](s32), [[LSHR2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST3]](s32), [[BITCAST4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC7:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR4]](s32), [[BITCAST5]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC5]](<2 x s16>), [[BUILD_VECTOR_TRUNC6]](<2 x s16>), [[BUILD_VECTOR_TRUNC7]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; GFX8-LABEL: name: test_sext_inreg_v3s16_1
@@ -779,15 +762,12 @@ body: |
; GFX8: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ASHR2]](s16)
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C2]]
; GFX8: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; GFX8: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C2]]
+ ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C2]]
; GFX8: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; GFX8: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL5]]
; GFX8: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -801,12 +781,9 @@ body: |
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 1
+ ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 1
+ ; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 1
; GFX6: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; GFX6: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX6: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@@ -817,24 +794,18 @@ body: |
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG]], [[C1]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG1]], [[C1]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG2]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG2]], [[C1]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
- ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
+ ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX6: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX6: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -983,26 +954,18 @@ body: |
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 1
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 1
+ ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 1
+ ; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 1
+ ; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 1
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG]], [[C1]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG1]], [[C1]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG2]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG3]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG2]], [[C1]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG3]], [[C1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX6: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -1094,37 +1057,25 @@ body: |
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX6: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 1
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX6: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 1
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 1
+ ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 1
+ ; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 1
+ ; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 1
+ ; GFX6: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST2]], 1
+ ; GFX6: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 1
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG]], [[C1]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG1]], [[C1]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG2]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
- ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG3]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG2]], [[C1]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG3]], [[C1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG4]](s32)
- ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG5]](s32)
- ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG4]], [[C1]]
+ ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SEXT_INREG5]], [[C1]]
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX6: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
index 11571ef490e63..0e668fec10ce4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
@@ -41,8 +41,7 @@ body: |
; CHECK-LABEL: name: test_sext_s16_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; CHECK: $vgpr0 = COPY [[SEXT_INREG]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
@@ -58,8 +57,7 @@ body: |
; CHECK-LABEL: name: test_sext_s24_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 24
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 24
; CHECK: $vgpr0 = COPY [[SEXT_INREG]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s24) = G_TRUNC %0
@@ -75,8 +73,7 @@ body: |
; CHECK-LABEL: name: test_sext_i1_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
; CHECK: $vgpr0 = COPY [[SEXT_INREG]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s1) = G_TRUNC %0
@@ -95,10 +92,8 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s16>) = COPY $vgpr0
@@ -123,12 +118,9 @@ body: |
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
@@ -151,14 +143,10 @@ body: |
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 16
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32), [[SEXT_INREG3]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
@@ -251,8 +239,7 @@ body: |
; CHECK-LABEL: name: test_sext_s8_to_s24
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; CHECK: [[TRUNC:%[0-9]+]]:_(s24) = G_TRUNC [[SEXT_INREG]](s32)
; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s24)
%0:_(s32) = COPY $vgpr0
@@ -269,8 +256,7 @@ body: |
; CHECK-LABEL: name: test_sext_s7_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 7
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
; CHECK: S_ENDPGM 0, implicit [[SEXT_INREG]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
@@ -286,8 +272,7 @@ body: |
; CHECK-LABEL: name: test_sext_s8_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; CHECK: S_ENDPGM 0, implicit [[SEXT_INREG]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
@@ -627,16 +612,12 @@ body: |
; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C5]]
; CHECK: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C3]](s16)
; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL2]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
- ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY1]], [[C5]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
- ; CHECK: [[AND5:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C5]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[ASHR1]], [[C5]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s16) = G_AND [[ASHR1]], [[C5]]
; CHECK: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C3]](s16)
; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL3]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
- ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C5]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
- ; CHECK: [[AND7:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C5]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[ASHR1]], [[C5]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s16) = G_AND [[ASHR1]], [[C5]]
; CHECK: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND7]], [[C3]](s16)
; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[SHL4]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
@@ -648,28 +629,20 @@ body: |
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C1]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL6]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR4]](s32), [[OR5]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
- ; CHECK: [[AND8:%[0-9]+]]:_(s16) = G_AND [[COPY5]], [[C5]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
- ; CHECK: [[AND9:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C5]]
+ ; CHECK: [[AND8:%[0-9]+]]:_(s16) = G_AND [[ASHR1]], [[C5]]
+ ; CHECK: [[AND9:%[0-9]+]]:_(s16) = G_AND [[ASHR1]], [[C5]]
; CHECK: [[SHL7:%[0-9]+]]:_(s16) = G_SHL [[AND9]], [[C3]](s16)
; CHECK: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[SHL7]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
- ; CHECK: [[AND10:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C5]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
- ; CHECK: [[AND11:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C5]]
+ ; CHECK: [[AND10:%[0-9]+]]:_(s16) = G_AND [[ASHR1]], [[C5]]
+ ; CHECK: [[AND11:%[0-9]+]]:_(s16) = G_AND [[ASHR1]], [[C5]]
; CHECK: [[SHL8:%[0-9]+]]:_(s16) = G_SHL [[AND11]], [[C3]](s16)
; CHECK: [[OR7:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[SHL8]]
- ; CHECK: [[COPY9:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
- ; CHECK: [[AND12:%[0-9]+]]:_(s16) = G_AND [[COPY9]], [[C5]]
- ; CHECK: [[COPY10:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
- ; CHECK: [[AND13:%[0-9]+]]:_(s16) = G_AND [[COPY10]], [[C5]]
+ ; CHECK: [[AND12:%[0-9]+]]:_(s16) = G_AND [[ASHR1]], [[C5]]
+ ; CHECK: [[AND13:%[0-9]+]]:_(s16) = G_AND [[ASHR1]], [[C5]]
; CHECK: [[SHL9:%[0-9]+]]:_(s16) = G_SHL [[AND13]], [[C3]](s16)
; CHECK: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[SHL9]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
- ; CHECK: [[AND14:%[0-9]+]]:_(s16) = G_AND [[COPY11]], [[C5]]
- ; CHECK: [[COPY12:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
- ; CHECK: [[AND15:%[0-9]+]]:_(s16) = G_AND [[COPY12]], [[C5]]
+ ; CHECK: [[AND14:%[0-9]+]]:_(s16) = G_AND [[ASHR1]], [[C5]]
+ ; CHECK: [[AND15:%[0-9]+]]:_(s16) = G_AND [[ASHR1]], [[C5]]
; CHECK: [[SHL10:%[0-9]+]]:_(s16) = G_SHL [[AND15]], [[C3]](s16)
; CHECK: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[SHL10]]
; CHECK: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
@@ -724,8 +697,7 @@ body: |
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-LABEL: name: test_sext_s112_to_s128
; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
- ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY [[COPY]](s128)
- ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](s128)
+ ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[UV1]], 48
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[UV]](s64), [[SEXT_INREG]](s64)
; CHECK: S_ENDPGM 0, implicit [[MV]](s128)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir
index 1d0bf3775c30d..bdde9078aaeff 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir
@@ -46,13 +46,11 @@ body: |
; SI-LABEL: name: test_sextload_flat_i31_i8
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SEXTLOAD]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[SEXTLOAD]](s32)
; VI-LABEL: name: test_sextload_flat_i31_i8
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SEXTLOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[SEXTLOAD]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s31) = G_SEXTLOAD %0 :: (load (s8), addrspace 0)
%2:_(s32) = G_ANYEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
index ab4e61a918468..1e0e13bd29018 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
@@ -174,13 +174,11 @@ body: |
; GFX8-LABEL: name: test_sextload_global_i31_i8
; GFX8: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX8: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SEXTLOAD]](s32)
- ; GFX8: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX8: $vgpr0 = COPY [[SEXTLOAD]](s32)
; GFX6-LABEL: name: test_sextload_global_i31_i8
; GFX6: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX6: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SEXTLOAD]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX6: $vgpr0 = COPY [[SEXTLOAD]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s31) = G_SEXTLOAD %0 :: (load (s8), addrspace 1)
%2:_(s32) = G_ANYEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-local.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-local.mir
index 41127b01ececd..54e6d68ce43ac 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-local.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-local.mir
@@ -38,8 +38,7 @@ body: |
; CHECK-LABEL: name: test_sextload_local_i31_i8
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load (s8), addrspace 3)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SEXTLOAD]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s31) = G_SEXTLOAD %0 :: (load (s8), addrspace 3)
%2:_(s32) = G_ANYEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-private.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-private.mir
index b1e275a94fd4a..8a71cfcf7d25b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-private.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-private.mir
@@ -40,8 +40,7 @@ body: |
; CHECK-LABEL: name: test_sextload_private_i31_i8
; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load (s8), addrspace 5)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SEXTLOAD]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
%0:_(p5) = COPY $vgpr0
%1:_(s31) = G_SEXTLOAD %0 :: (load (s8), addrspace 5)
%2:_(s32) = G_ANYEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
index 9120e992521b8..a4dcc71fde472 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
@@ -95,24 +95,21 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s32)
; SI: $vgpr0_vgpr1 = COPY [[SHL]](s64)
; VI-LABEL: name: test_shl_s64_s16
; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s32)
; VI: $vgpr0_vgpr1 = COPY [[SHL]](s64)
; GFX9-LABEL: name: test_shl_s64_s16
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[SHL]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
@@ -131,10 +128,8 @@ body: |
; SI-LABEL: name: test_shl_s16_s32
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[COPY1]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; SI: $vgpr0 = COPY [[COPY3]](s32)
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[SHL]](s32)
; VI-LABEL: name: test_shl_s16_s32
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -169,12 +164,9 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
+ ; SI: $vgpr0 = COPY [[SHL]](s32)
; VI-LABEL: name: test_shl_s16_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -210,12 +202,9 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
+ ; SI: $vgpr0 = COPY [[SHL]](s32)
; VI-LABEL: name: test_shl_s16_i8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -255,18 +244,14 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
+ ; SI: $vgpr0 = COPY [[SHL]](s32)
; VI-LABEL: name: test_shl_i8_i8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)
@@ -276,8 +261,7 @@ body: |
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)
@@ -482,18 +466,12 @@ body: |
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[AND1]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[AND]](s32)
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[AND1]](s32)
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL2]]
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -542,15 +520,11 @@ body: |
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[UV]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[UV1]](s32)
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[UV]](s32)
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[UV1]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C1]]
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL2]]
; SI: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -617,18 +591,12 @@ body: |
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[AND1]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[AND2]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[AND]](s32)
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[AND1]](s32)
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[AND2]](s32)
; SI: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; SI: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; SI: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@@ -638,24 +606,18 @@ body: |
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; SI: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C1]]
; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL3]]
; SI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SHL2]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C1]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL4]]
; SI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL5]]
; SI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -700,15 +662,12 @@ body: |
; VI: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; VI: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[SHL2]](s16)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; VI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; VI: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; VI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL5]]
; VI: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -741,15 +700,10 @@ body: |
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL1]](s16)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[COPY4]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[COPY6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[BITCAST1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR1]](s32), [[BITCAST2]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
@@ -784,33 +738,21 @@ body: |
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[AND1]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[AND2]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[AND3]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[AND]](s32)
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[AND1]](s32)
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[AND2]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; SI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[AND3]](s32)
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SHL]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SHL1]], [[C1]]
; SI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL4]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SHL2]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[SHL3]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SHL2]], [[C1]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[SHL3]], [[C1]]
; SI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL5]]
; SI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -879,18 +821,14 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[AND]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)
+ ; SI: $vgpr0 = COPY [[SHL]](s32)
; VI-LABEL: name: test_shl_s7_s7
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)
@@ -900,8 +838,7 @@ body: |
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)
@@ -925,24 +862,18 @@ body: |
; SI-LABEL: name: test_shl_i24_i32
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[COPY1]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; SI: $vgpr0 = COPY [[COPY3]](s32)
+ ; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[SHL]](s32)
; VI-LABEL: name: test_shl_i24_i32
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[COPY1]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; VI: $vgpr0 = COPY [[COPY3]](s32)
+ ; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[SHL]](s32)
; GFX9-LABEL: name: test_shl_i24_i32
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[COPY1]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY3]](s32)
+ ; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
+ ; GFX9: $vgpr0 = COPY [[SHL]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s24) = G_TRUNC %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
index 692078edbe65f..d0be30b266201 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
@@ -224,10 +224,8 @@ body: |
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -258,10 +256,8 @@ body: |
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -295,12 +291,9 @@ body: |
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; CHECK: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 64
; CHECK: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
@@ -309,12 +302,9 @@ body: |
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 16
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 16
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST2]], 16
+ ; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 16
+ ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST3]], 16
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG3]](s32), [[SEXT_INREG4]](s32), [[SEXT_INREG5]](s32)
; CHECK: [[EXTRACT3:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR1]](<3 x s32>), 32
; CHECK: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT1]](<3 x s16>), 0
@@ -323,12 +313,9 @@ body: |
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; CHECK: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 16
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 16
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY10]], 16
+ ; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST4]], 16
+ ; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR4]], 16
+ ; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST5]], 16
; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG6]](s32), [[SEXT_INREG7]](s32), [[SEXT_INREG8]](s32)
; CHECK: [[EXTRACT4:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR2]](<3 x s32>), 0
; CHECK: [[INSERT3:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
@@ -337,26 +324,19 @@ body: |
; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; CHECK: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; CHECK: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY11]], 16
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY12]], 16
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; CHECK: [[SEXT_INREG11:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY13]], 16
+ ; CHECK: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST6]], 16
+ ; CHECK: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR6]], 16
+ ; CHECK: [[SEXT_INREG11:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST7]], 16
; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG9]](s32), [[SEXT_INREG10]](s32), [[SEXT_INREG11]](s32)
; CHECK: [[EXTRACT5:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR3]](<3 x s32>), 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[EXTRACT2]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C1]]
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[EXTRACT3]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[EXTRACT2]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[EXTRACT3]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[EXTRACT4]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C1]]
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[EXTRACT5]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[EXTRACT4]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[EXTRACT5]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
index b2daf46b34b0c..81d78b0e78c01 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
@@ -50,11 +50,10 @@ body: |
; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C2]](s32)
+ ; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
@@ -88,8 +87,7 @@ body: |
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL]]
@@ -127,10 +125,8 @@ body: |
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -167,10 +163,8 @@ body: |
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -206,10 +200,8 @@ body: |
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -246,10 +238,8 @@ body: |
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -285,10 +275,8 @@ body: |
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -323,11 +311,10 @@ body: |
; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C2]](s32)
+ ; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
@@ -361,8 +348,7 @@ body: |
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[SHL]]
@@ -400,10 +386,8 @@ body: |
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -440,10 +424,8 @@ body: |
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -478,8 +460,7 @@ body: |
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[C1]], [[SHL]]
; GFX8: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -513,8 +494,7 @@ body: |
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -551,10 +531,8 @@ body: |
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -590,10 +568,8 @@ body: |
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -608,9 +584,7 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
@@ -637,10 +611,8 @@ body: |
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
@@ -678,10 +650,8 @@ body: |
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -696,9 +666,7 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
@@ -726,10 +694,8 @@ body: |
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -744,9 +710,7 @@ body: |
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
@@ -774,10 +738,8 @@ body: |
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -792,9 +754,7 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
@@ -822,10 +782,8 @@ body: |
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -840,9 +798,7 @@ body: |
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
@@ -873,12 +829,9 @@ body: |
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX8: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
+ ; GFX8: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; GFX8: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 64
; GFX8: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
@@ -887,28 +840,21 @@ body: |
; GFX8: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX8: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX8: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
- ; GFX8: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX8: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 16
- ; GFX8: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX8: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 16
+ ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST2]], 16
+ ; GFX8: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 16
+ ; GFX8: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST3]], 16
; GFX8: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG3]](s32), [[SEXT_INREG4]](s32), [[SEXT_INREG5]](s32)
; GFX8: [[EXTRACT3:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR1]](<3 x s32>), 32
; GFX8: [[EXTRACT4:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 0
; GFX8: [[EXTRACT5:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR1]](<3 x s32>), 0
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY8:%[0-9]+]]:_(s32) = COPY [[EXTRACT2]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
- ; GFX8: [[COPY9:%[0-9]+]]:_(s32) = COPY [[EXTRACT3]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[EXTRACT2]], [[C1]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[EXTRACT3]], [[C1]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX8: [[COPY10:%[0-9]+]]:_(s32) = COPY [[EXTRACT4]](s32)
- ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; GFX8: [[COPY11:%[0-9]+]]:_(s32) = COPY [[EXTRACT5]](s32)
- ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[EXTRACT4]], [[C1]]
+ ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[EXTRACT5]], [[C1]]
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX8: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -928,12 +874,9 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
+ ; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
; GFX9: [[EXTRACT2:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 64
; GFX9: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
@@ -942,22 +885,15 @@ body: |
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 16
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 16
+ ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST2]], 16
+ ; GFX9: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 16
+ ; GFX9: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST3]], 16
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG3]](s32), [[SEXT_INREG4]](s32), [[SEXT_INREG5]](s32)
; GFX9: [[EXTRACT3:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR1]](<3 x s32>), 32
; GFX9: [[EXTRACT4:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR]](<3 x s32>), 0
; GFX9: [[EXTRACT5:%[0-9]+]]:_(s32) = G_EXTRACT [[BUILD_VECTOR1]](<3 x s32>), 0
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[EXTRACT2]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[EXTRACT3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[EXTRACT4]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[EXTRACT5]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[EXTRACT2]](s32), [[EXTRACT3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[EXTRACT4]](s32), [[EXTRACT5]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>)
; GFX9: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
@@ -990,10 +926,8 @@ body: |
; GFX8: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[BITCAST1]](<2 x s32>), 0
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -1010,9 +944,7 @@ body: |
; GFX9: [[BITCAST1:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[COPY]](<4 x s16>)
; GFX9: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[BITCAST1]](<2 x s32>), 0
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<4 x s16>) = COPY $vgpr2_vgpr3
@@ -1041,10 +973,8 @@ body: |
; GFX8: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[BITCAST1]](<2 x s32>), 32
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -1060,9 +990,7 @@ body: |
; GFX9: [[BITCAST1:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[COPY]](<4 x s16>)
; GFX9: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[BITCAST1]](<2 x s32>), 32
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<4 x s16>) = COPY $vgpr2_vgpr3
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
index 4a0310c4b2291..c9b88d2d547ac 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir
@@ -178,8 +178,7 @@ body: |
; GFX6-LABEL: name: test_sitofp_s16_to_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; GFX6: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[SEXT_INREG]](s32)
; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SITOFP]](s16)
; GFX6: $vgpr0 = COPY [[ANYEXT]](s32)
@@ -204,14 +203,12 @@ body: |
; GFX6-LABEL: name: test_sitofp_s16_to_s32
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; GFX6: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[SEXT_INREG]](s32)
; GFX6: $vgpr0 = COPY [[SITOFP]](s32)
; GFX8-LABEL: name: test_sitofp_s16_to_s32
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; GFX8: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[SEXT_INREG]](s32)
; GFX8: $vgpr0 = COPY [[SITOFP]](s32)
%0:_(s32) = COPY $vgpr0
@@ -228,14 +225,12 @@ body: |
; GFX6-LABEL: name: test_sitofp_s16_to_s64
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; GFX6: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[SEXT_INREG]](s32)
; GFX6: $vgpr0_vgpr1 = COPY [[SITOFP]](s64)
; GFX8-LABEL: name: test_sitofp_s16_to_s64
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; GFX8: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[SEXT_INREG]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[SITOFP]](s64)
%0:_(s32) = COPY $vgpr0
@@ -252,15 +247,13 @@ body: |
; GFX6-LABEL: name: test_sitofp_s8_to_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX6: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[SEXT_INREG]](s32)
; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SITOFP]](s16)
; GFX6: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX8-LABEL: name: test_sitofp_s8_to_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX8: [[SITOFP:%[0-9]+]]:_(s16) = G_SITOFP [[SEXT_INREG]](s32)
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SITOFP]](s16)
; GFX8: $vgpr0 = COPY [[ANYEXT]](s32)
@@ -279,14 +272,12 @@ body: |
; GFX6-LABEL: name: test_sitofp_s8_to_s32
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX6: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[SEXT_INREG]](s32)
; GFX6: $vgpr0 = COPY [[SITOFP]](s32)
; GFX8-LABEL: name: test_sitofp_s8_to_s32
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX8: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[SEXT_INREG]](s32)
; GFX8: $vgpr0 = COPY [[SITOFP]](s32)
%0:_(s32) = COPY $vgpr0
@@ -303,14 +294,12 @@ body: |
; GFX6-LABEL: name: test_sitofp_s8_to_s64
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX6: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[SEXT_INREG]](s32)
; GFX6: $vgpr0_vgpr1 = COPY [[SITOFP]](s64)
; GFX8-LABEL: name: test_sitofp_s8_to_s64
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX8: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[SEXT_INREG]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[SITOFP]](s64)
%0:_(s32) = COPY $vgpr0
@@ -408,8 +397,7 @@ body: |
; GFX6-LABEL: name: test_sitofp_s33_to_s32
; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX6: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 33
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 33
; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXT_INREG]](s64)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@@ -430,8 +418,7 @@ body: |
; GFX6: $vgpr0 = COPY [[INT1]](s32)
; GFX8-LABEL: name: test_sitofp_s33_to_s32
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
- ; GFX8: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 33
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 33
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SEXT_INREG]](s64)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
index 9a271c7fa8ce0..90c37de97212d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
@@ -70,13 +70,10 @@ body: |
; SI-LABEL: name: test_smax_s16
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
+ ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; SI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMAX]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[SMAX]](s32)
; VI-LABEL: name: test_smax_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -111,13 +108,10 @@ body: |
; SI-LABEL: name: test_smax_s8
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
+ ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; SI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMAX]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[SMAX]](s32)
; VI-LABEL: name: test_smax_s8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -134,11 +128,9 @@ body: |
; GFX9-LABEL: name: test_smax_s8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG1]](s32)
; GFX9: [[SMAX:%[0-9]+]]:_(s16) = G_SMAX [[TRUNC]], [[TRUNC1]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMAX]](s16)
@@ -161,33 +153,24 @@ body: |
; SI-LABEL: name: test_smax_s17
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 17
+ ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 17
; SI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMAX]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[SMAX]](s32)
; VI-LABEL: name: test_smax_s17
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; VI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
+ ; VI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 17
+ ; VI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 17
; VI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMAX]](s32)
- ; VI: $vgpr0 = COPY [[COPY4]](s32)
+ ; VI: $vgpr0 = COPY [[SMAX]](s32)
; GFX9-LABEL: name: test_smax_s17
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 17
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 17
; GFX9: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMAX]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX9: $vgpr0 = COPY [[SMAX]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s17) = G_TRUNC %0
@@ -292,21 +275,15 @@ body: |
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
+ ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
; SI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
+ ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 16
; SI: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG2]], [[SEXT_INREG3]]
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SMAX]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SMAX1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[SMAX]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SMAX1]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -363,27 +340,18 @@ body: |
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
+ ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST2]], 16
; SI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
+ ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 16
; SI: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG2]], [[SEXT_INREG3]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; SI: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
+ ; SI: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST3]], 16
; SI: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG4]], [[SEXT_INREG5]]
; SI: [[DEF3:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; SI: [[DEF4:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SMAX]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SMAX1]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SMAX2]](s32)
- ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32)
+ ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SMAX]](s32), [[SMAX1]](s32), [[SMAX2]](s32)
; SI: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
; VI-LABEL: name: test_smax_v3s16
; VI: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@@ -435,10 +403,7 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[SMAX1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s16>) = G_IMPLICIT_DEF
%1:_(<3 x s16>) = G_IMPLICIT_DEF
@@ -467,38 +432,26 @@ body: |
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
+ ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST2]], 16
; SI: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
+ ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 16
; SI: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG2]], [[SEXT_INREG3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 16
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 16
+ ; SI: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
+ ; SI: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST3]], 16
; SI: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG4]], [[SEXT_INREG5]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 16
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 16
+ ; SI: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 16
+ ; SI: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR3]], 16
; SI: [[SMAX3:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG6]], [[SEXT_INREG7]]
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SMAX]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SMAX1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[SMAX]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SMAX1]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SMAX2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[SMAX3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SMAX2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SMAX3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
index a81535cbec0af..54da629605b8b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
@@ -70,13 +70,10 @@ body: |
; SI-LABEL: name: test_smin_s16
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
+ ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[SMIN]](s32)
; VI-LABEL: name: test_smin_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -111,13 +108,10 @@ body: |
; SI-LABEL: name: test_smin_s8
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
+ ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[SMIN]](s32)
; VI-LABEL: name: test_smin_s8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -134,11 +128,9 @@ body: |
; GFX9-LABEL: name: test_smin_s8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG1]](s32)
; GFX9: [[SMIN:%[0-9]+]]:_(s16) = G_SMIN [[TRUNC]], [[TRUNC1]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SMIN]](s16)
@@ -161,33 +153,24 @@ body: |
; SI-LABEL: name: test_smin_s17
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 17
+ ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 17
; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[SMIN]](s32)
; VI-LABEL: name: test_smin_s17
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; VI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
+ ; VI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 17
+ ; VI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 17
; VI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
- ; VI: $vgpr0 = COPY [[COPY4]](s32)
+ ; VI: $vgpr0 = COPY [[SMIN]](s32)
; GFX9-LABEL: name: test_smin_s17
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 17
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 17
; GFX9: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX9: $vgpr0 = COPY [[SMIN]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s17) = G_TRUNC %0
@@ -292,21 +275,15 @@ body: |
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
+ ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
+ ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 16
; SI: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG2]], [[SEXT_INREG3]]
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SMIN1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[SMIN]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SMIN1]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -363,27 +340,18 @@ body: |
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
+ ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST2]], 16
; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
+ ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 16
; SI: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG2]], [[SEXT_INREG3]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; SI: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
+ ; SI: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST3]], 16
; SI: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG4]], [[SEXT_INREG5]]
; SI: [[DEF3:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; SI: [[DEF4:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SMIN1]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SMIN2]](s32)
- ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32)
+ ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SMIN]](s32), [[SMIN1]](s32), [[SMIN2]](s32)
; SI: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
; VI-LABEL: name: test_smin_v3s16
; VI: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@@ -435,10 +403,7 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[SMIN1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s16>) = G_IMPLICIT_DEF
%1:_(<3 x s16>) = G_IMPLICIT_DEF
@@ -467,38 +432,26 @@ body: |
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; SI: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
+ ; SI: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST2]], 16
; SI: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; SI: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
+ ; SI: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 16
; SI: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG2]], [[SEXT_INREG3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 16
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 16
+ ; SI: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
+ ; SI: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST3]], 16
; SI: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG4]], [[SEXT_INREG5]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 16
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 16
+ ; SI: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 16
+ ; SI: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR3]], 16
; SI: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG6]], [[SEXT_INREG7]]
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SMIN1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[SMIN]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SMIN1]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SMIN2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[SMIN3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SMIN2]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SMIN3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; SI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir
index a3478c4c5488c..285c129147993 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir
@@ -63,28 +63,22 @@ body: |
; GFX8-LABEL: name: test_smulh_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; GFX8: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[MUL]], [[C]](s32)
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; GFX8: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
+ ; GFX8: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ASHR]], 16
; GFX8: $vgpr0 = COPY [[SEXT_INREG2]](s32)
; GFX9-LABEL: name: test_smulh_s16
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[MUL]], [[C]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
+ ; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ASHR]], 16
; GFX9: $vgpr0 = COPY [[SEXT_INREG2]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -119,11 +113,9 @@ body: |
; GFX9-LABEL: name: test_smulh_s8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SEXT_INREG1]](s32)
; GFX9: [[MUL:%[0-9]+]]:_(s16) = G_MUL [[TRUNC]], [[TRUNC1]]
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
@@ -150,33 +142,25 @@ body: |
; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX8: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16
; GFX8: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[MUL]], [[C]](s32)
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX8: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
- ; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; GFX8: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
+ ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV3]], 16
; GFX8: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG2]], [[SEXT_INREG3]]
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[MUL1]], [[C]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; GFX8: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C1]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST]](<2 x s16>)
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX8: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX8: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 16
- ; GFX8: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 16
+ ; GFX8: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
+ ; GFX8: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG4]](s32), [[SEXT_INREG5]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_smulh_v2s16
@@ -184,28 +168,20 @@ body: |
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16
; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[MUL]], [[C]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
+ ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV3]], 16
; GFX9: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG2]], [[SEXT_INREG3]]
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[MUL1]], [[C]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ASHR]](s32), [[ASHR1]](s32)
; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 16
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 16
+ ; GFX9: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
+ ; GFX9: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG4]](s32), [[SEXT_INREG5]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
@@ -245,10 +221,8 @@ body: |
; GFX8: [[MUL1:%[0-9]+]]:_(s16) = G_MUL [[ASHR3]], [[ASHR4]]
; GFX8: [[ASHR5:%[0-9]+]]:_(s16) = G_ASHR [[MUL1]], [[C]](s16)
; GFX8: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX8: [[COPY4:%[0-9]+]]:_(s16) = COPY [[ASHR2]](s16)
- ; GFX8: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C1]]
- ; GFX8: [[COPY5:%[0-9]+]]:_(s16) = COPY [[ASHR5]](s16)
- ; GFX8: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY5]], [[C1]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s16) = G_AND [[ASHR2]], [[C1]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s16) = G_AND [[ASHR5]], [[C1]]
; GFX8: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C]](s16)
; GFX8: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -258,25 +232,17 @@ body: |
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 8
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 8
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 8
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG2]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
+ ; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
+ ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[SEXT_INREG2]](s32), [[SEXT_INREG3]](s32)
; GFX9: [[MUL:%[0-9]+]]:_(<2 x s16>) = G_MUL [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC1]]
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[C1]](s32)
+ ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[C1]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[MUL]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[ASHR]](<2 x s16>)
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
@@ -284,10 +250,8 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C2]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX9: [[COPY13:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
- ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY13]], [[C3]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
- ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY14]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C]](s16)
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -388,61 +352,41 @@ body: |
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 8
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 8
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG2]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 8
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
+ ; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
+ ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR3]], 8
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[SEXT_INREG2]](s32), [[SEXT_INREG3]](s32)
; GFX9: [[MUL:%[0-9]+]]:_(<2 x s16>) = G_MUL [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC1]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
; GFX9: [[ASHR:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[MUL]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY12]], 8
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY13]], 8
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG4]](s32)
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG5]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY14]](s32), [[COPY15]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY16]], 8
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY17]], 8
- ; GFX9: [[COPY18:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG6]](s32)
- ; GFX9: [[COPY19:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG7]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY18]](s32), [[COPY19]](s32)
+ ; GFX9: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 8
+ ; GFX9: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 8
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[SEXT_INREG4]](s32), [[SEXT_INREG5]](s32)
+ ; GFX9: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR4]], 8
+ ; GFX9: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR5]], 8
+ ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[SEXT_INREG6]](s32), [[SEXT_INREG7]](s32)
; GFX9: [[MUL1:%[0-9]+]]:_(<2 x s16>) = G_MUL [[BUILD_VECTOR_TRUNC3]], [[BUILD_VECTOR_TRUNC4]]
- ; GFX9: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY20]](s32), [[COPY21]](s32)
+ ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(<2 x s16>) = G_ASHR [[MUL1]], [[BUILD_VECTOR_TRUNC5]](<2 x s16>)
; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[ASHR]](<2 x s16>)
; GFX9: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[ASHR1]](<2 x s16>)
; GFX9: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY22:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
- ; GFX9: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY24:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C3]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C3]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; GFX9: $vgpr0 = COPY [[OR2]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir
index 87b0c5bd57a7b..4c61d03bd3ce7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir
@@ -61,10 +61,8 @@ body: |
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[MUL]](s32), [[MUL1]](s32)
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 1
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 1
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; GFX8: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX8: $vgpr2_vgpr3 = COPY [[BUILD_VECTOR1]](<2 x s32>)
@@ -107,30 +105,24 @@ body: |
; GFX8-LABEL: name: test_smulo_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; GFX8: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX8: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL]], 16
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[SEXT_INREG2]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
+ ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL]], 16
; GFX8: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8: $vgpr0 = COPY [[SEXT_INREG3]](s32)
; GFX8: $vgpr1 = COPY [[SEXT]](s32)
; GFX9-LABEL: name: test_smulo_s16
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL]], 16
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[SEXT_INREG2]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
+ ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL]], 16
; GFX9: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9: $vgpr0 = COPY [[SEXT_INREG3]](s32)
; GFX9: $vgpr1 = COPY [[SEXT]](s32)
@@ -154,30 +146,24 @@ body: |
; GFX8-LABEL: name: test_smulo_s8
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; GFX8: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX8: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL]], 8
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[SEXT_INREG2]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
+ ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL]], 8
; GFX8: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX8: $vgpr0 = COPY [[SEXT_INREG3]](s32)
; GFX8: $vgpr1 = COPY [[SEXT]](s32)
; GFX9-LABEL: name: test_smulo_s8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL]], 8
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[SEXT_INREG2]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
+ ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL]], 8
; GFX9: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
; GFX9: $vgpr0 = COPY [[SEXT_INREG3]](s32)
; GFX9: $vgpr1 = COPY [[SEXT]](s32)
@@ -202,42 +188,32 @@ body: |
; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX8: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16
; GFX8: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX8: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL]], 16
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[SEXT_INREG2]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
- ; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; GFX8: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
+ ; GFX8: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV3]], 16
; GFX8: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG3]], [[SEXT_INREG4]]
; GFX8: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL1]], 16
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL1]](s32), [[SEXT_INREG5]]
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY6:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
- ; GFX8: [[COPY7:%[0-9]+]]:_(s32) = COPY [[MUL1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C]]
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
- ; GFX8: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX8: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 1
- ; GFX8: [[COPY9:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX8: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 1
+ ; GFX8: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
+ ; GFX8: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 1
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG6]](s32), [[SEXT_INREG7]](s32)
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST]](<2 x s16>)
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; GFX8: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX8: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY10]], 16
- ; GFX8: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY11]], 16
+ ; GFX8: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
+ ; GFX8: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
; GFX8: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG8]](s32), [[SEXT_INREG9]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR1]](<2 x s32>)
; GFX8: $vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s32>)
@@ -246,23 +222,17 @@ body: |
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV]], 16
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV2]], 16
; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL]], 16
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[SEXT_INREG2]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; GFX9: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV1]], 16
+ ; GFX9: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[UV3]], 16
; GFX9: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG3]], [[SEXT_INREG4]]
; GFX9: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL1]], 16
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL1]](s32), [[SEXT_INREG5]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[MUL1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[MUL]](s32), [[MUL1]](s32)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX9: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 1
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
@@ -271,10 +241,8 @@ body: |
; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 16
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 16
+ ; GFX9: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
+ ; GFX9: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG8]](s32), [[SEXT_INREG9]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR1]](<2 x s32>)
; GFX9: $vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s32>)
@@ -300,17 +268,13 @@ body: |
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
- ; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 8
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
; GFX8: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX8: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL]], 8
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[SEXT_INREG2]]
- ; GFX8: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 8
- ; GFX8: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX8: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 8
+ ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
+ ; GFX8: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; GFX8: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG3]], [[SEXT_INREG4]]
; GFX8: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL1]], 8
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL1]](s32), [[SEXT_INREG5]]
@@ -333,17 +297,13 @@ body: |
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 8
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL]], 8
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[SEXT_INREG2]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 8
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX9: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 8
+ ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
+ ; GFX9: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; GFX9: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG3]], [[SEXT_INREG4]]
; GFX9: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL1]], 8
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL1]](s32), [[SEXT_INREG5]]
@@ -401,47 +361,35 @@ body: |
; GFX8: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX8: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX8: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; GFX8: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX8: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL]], 8
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[SEXT_INREG2]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
- ; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX8: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 8
+ ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 8
+ ; GFX8: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR3]], 8
; GFX8: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG3]], [[SEXT_INREG4]]
; GFX8: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL1]], 8
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL1]](s32), [[SEXT_INREG5]]
- ; GFX8: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 8
- ; GFX8: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX8: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 8
+ ; GFX8: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 8
+ ; GFX8: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR4]], 8
; GFX8: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG6]], [[SEXT_INREG7]]
; GFX8: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL2]], 8
; GFX8: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL2]](s32), [[SEXT_INREG8]]
- ; GFX8: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX8: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 8
- ; GFX8: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX8: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 8
+ ; GFX8: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 8
+ ; GFX8: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR5]], 8
; GFX8: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG9]], [[SEXT_INREG10]]
; GFX8: [[SEXT_INREG11:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL3]], 8
; GFX8: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL3]](s32), [[SEXT_INREG11]]
; GFX8: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX8: [[COPY10:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
- ; GFX8: [[COPY11:%[0-9]+]]:_(s32) = COPY [[MUL1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C3]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C3]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX8: [[COPY12:%[0-9]+]]:_(s32) = COPY [[MUL2]](s32)
- ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL2]], [[C3]]
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX8: [[COPY13:%[0-9]+]]:_(s32) = COPY [[MUL3]](s32)
- ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
+ ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[MUL3]], [[C3]]
; GFX8: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX8: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
@@ -459,47 +407,35 @@ body: |
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL]], 8
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[SEXT_INREG2]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 8
+ ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 8
+ ; GFX9: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR3]], 8
; GFX9: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG3]], [[SEXT_INREG4]]
; GFX9: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL1]], 8
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL1]](s32), [[SEXT_INREG5]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 8
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 8
+ ; GFX9: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 8
+ ; GFX9: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR4]], 8
; GFX9: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG6]], [[SEXT_INREG7]]
; GFX9: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL2]], 8
; GFX9: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL2]](s32), [[SEXT_INREG8]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 8
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 8
+ ; GFX9: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 8
+ ; GFX9: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR5]], 8
; GFX9: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG9]], [[SEXT_INREG10]]
; GFX9: [[SEXT_INREG11:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL3]], 8
; GFX9: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL3]](s32), [[SEXT_INREG11]]
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[MUL1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C3]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[MUL2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL2]], [[C3]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C1]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[MUL3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[MUL3]], [[C3]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
@@ -528,10 +464,8 @@ body: |
; GFX8-LABEL: name: test_smulo_s24
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 24
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 24
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 24
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 24
; GFX8: [[SMULH:%[0-9]+]]:_(s32) = G_SMULH [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX8: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
@@ -540,18 +474,15 @@ body: |
; GFX8: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL]], 24
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[SEXT_INREG2]]
; GFX8: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP]], [[ICMP1]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 24
+ ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL]], 24
; GFX8: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[OR]](s1)
; GFX8: $vgpr0 = COPY [[SEXT_INREG3]](s32)
; GFX8: $vgpr1 = COPY [[SEXT]](s32)
; GFX9-LABEL: name: test_smulo_s24
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 24
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 24
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 24
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 24
; GFX9: [[SMULH:%[0-9]+]]:_(s32) = G_SMULH [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
@@ -560,8 +491,7 @@ body: |
; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL]], 24
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[SEXT_INREG2]]
; GFX9: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP]], [[ICMP1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 24
+ ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[MUL]], 24
; GFX9: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[OR]](s1)
; GFX9: $vgpr0 = COPY [[SEXT_INREG3]](s32)
; GFX9: $vgpr1 = COPY [[SEXT]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
index 7f06b6d65b1d3..fb5d21de322e7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir
@@ -1831,10 +1831,8 @@ body: |
; GFX6-LABEL: name: test_srem_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
+ ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -1864,16 +1862,13 @@ body: |
; GFX6: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[SELECT1]], [[ASHR]]
; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[XOR2]], [[ASHR]]
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C3]]
; GFX6: $vgpr0 = COPY [[AND]](s32)
; GFX8-LABEL: name: test_srem_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -1903,16 +1898,13 @@ body: |
; GFX8: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[SELECT1]], [[ASHR]]
; GFX8: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[XOR2]], [[ASHR]]
; GFX8: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C3]]
; GFX8: $vgpr0 = COPY [[AND]](s32)
; GFX9-LABEL: name: test_srem_s16
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -1942,8 +1934,7 @@ body: |
; GFX9: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[SELECT1]], [[ASHR]]
; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[XOR2]], [[ASHR]]
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C3]]
; GFX9: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -1968,10 +1959,8 @@ body: |
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
+ ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C1]](s32)
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C1]](s32)
@@ -2000,10 +1989,8 @@ body: |
; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX6: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[SELECT1]], [[ASHR]]
; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[XOR2]], [[ASHR]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
+ ; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 16
; GFX6: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[C1]](s32)
; GFX6: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s32)
; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG2]], [[ASHR2]]
@@ -2031,10 +2018,8 @@ body: |
; GFX6: [[XOR5:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[ASHR2]]
; GFX6: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[XOR5]], [[ASHR2]]
; GFX6: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C5]]
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SUB9]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C5]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C5]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB9]], [[C5]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -2047,10 +2032,8 @@ body: |
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C1]](s32)
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C1]](s32)
@@ -2079,10 +2062,8 @@ body: |
; GFX8: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX8: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[SELECT1]], [[ASHR]]
; GFX8: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[XOR2]], [[ASHR]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
- ; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; GFX8: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
+ ; GFX8: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 16
; GFX8: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[C1]](s32)
; GFX8: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s32)
; GFX8: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG2]], [[ASHR2]]
@@ -2110,10 +2091,8 @@ body: |
; GFX8: [[XOR5:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[ASHR2]]
; GFX8: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[XOR5]], [[ASHR2]]
; GFX8: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C5]]
- ; GFX8: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SUB9]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C5]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB4]], [[C5]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB9]], [[C5]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -2126,10 +2105,8 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST]], 16
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST1]], 16
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C1]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C1]](s32)
@@ -2158,10 +2135,8 @@ body: |
; GFX9: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX9: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[SELECT1]], [[ASHR]]
; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[XOR2]], [[ASHR]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; GFX9: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR]], 16
+ ; GFX9: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR1]], 16
; GFX9: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG2]], [[C1]](s32)
; GFX9: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG3]], [[C1]](s32)
; GFX9: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG2]], [[ASHR2]]
@@ -2188,9 +2163,7 @@ body: |
; GFX9: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[SUB8]], [[SELECT2]]
; GFX9: [[XOR5:%[0-9]+]]:_(s32) = G_XOR [[SELECT3]], [[ASHR2]]
; GFX9: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[XOR5]], [[ASHR2]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SUB9]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[SUB4]](s32), [[SUB9]](s32)
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
@@ -2207,10 +2180,8 @@ body: |
; GFX6-LABEL: name: test_srem_s7
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 7
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 7
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
+ ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 7
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -2239,15 +2210,12 @@ body: |
; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX6: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[SELECT1]], [[ASHR]]
; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[XOR2]], [[ASHR]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[SUB4]](s32)
; GFX8-LABEL: name: test_srem_s7
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 7
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 7
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 7
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -2276,15 +2244,12 @@ body: |
; GFX8: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX8: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[SELECT1]], [[ASHR]]
; GFX8: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[XOR2]], [[ASHR]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
- ; GFX8: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX8: $vgpr0 = COPY [[SUB4]](s32)
; GFX9-LABEL: name: test_srem_s7
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 7
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 7
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 7
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -2313,8 +2278,7 @@ body: |
; GFX9: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX9: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[SELECT1]], [[ASHR]]
; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[XOR2]], [[ASHR]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX9: $vgpr0 = COPY [[SUB4]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s7) = G_TRUNC %0
@@ -2333,10 +2297,8 @@ body: |
; GFX6-LABEL: name: test_srem_s17
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 17
+ ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 17
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -2365,15 +2327,12 @@ body: |
; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX6: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[SELECT1]], [[ASHR]]
; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[XOR2]], [[ASHR]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[SUB4]](s32)
; GFX8-LABEL: name: test_srem_s17
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 17
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 17
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX8: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX8: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -2402,15 +2361,12 @@ body: |
; GFX8: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX8: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[SELECT1]], [[ASHR]]
; GFX8: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[XOR2]], [[ASHR]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
- ; GFX8: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX8: $vgpr0 = COPY [[SUB4]](s32)
; GFX9-LABEL: name: test_srem_s17
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 17
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 17
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 17
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 17
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; GFX9: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -2439,8 +2395,7 @@ body: |
; GFX9: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
; GFX9: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[SELECT1]], [[ASHR]]
; GFX9: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[XOR2]], [[ASHR]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB4]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX9: $vgpr0 = COPY [[SUB4]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s17) = G_TRUNC %0
@@ -2459,10 +2414,8 @@ body: |
; GFX6-LABEL: name: test_srem_s33
; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX6: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; GFX6: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 33
- ; GFX6: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY3]], 33
+ ; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 33
+ ; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 33
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX6: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX6: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -2626,15 +2579,12 @@ body: |
; GFX6: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV22]], [[UV24]]
; GFX6: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV23]], [[UV25]], [[USUBO9]]
; GFX6: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO8]](s32), [[USUBE12]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s64) = COPY [[MV5]](s64)
- ; GFX6: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; GFX6: $vgpr0_vgpr1 = COPY [[MV5]](s64)
; GFX8-LABEL: name: test_srem_s33
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; GFX8: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 33
- ; GFX8: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY3]], 33
+ ; GFX8: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 33
+ ; GFX8: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 33
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX8: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX8: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -2798,15 +2748,12 @@ body: |
; GFX8: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV22]], [[UV24]]
; GFX8: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV23]], [[UV25]], [[USUBO9]]
; GFX8: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO8]](s32), [[USUBE12]](s32)
- ; GFX8: [[COPY4:%[0-9]+]]:_(s64) = COPY [[MV5]](s64)
- ; GFX8: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; GFX8: $vgpr0_vgpr1 = COPY [[MV5]](s64)
; GFX9-LABEL: name: test_srem_s33
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; GFX9: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY2]], 33
- ; GFX9: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY3]], 33
+ ; GFX9: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 33
+ ; GFX9: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 33
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX9: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[C]](s32)
; GFX9: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG1]], [[C]](s32)
@@ -2970,8 +2917,7 @@ body: |
; GFX9: [[USUBO8:%[0-9]+]]:_(s32), [[USUBO9:%[0-9]+]]:_(s1) = G_USUBO [[UV22]], [[UV24]]
; GFX9: [[USUBE12:%[0-9]+]]:_(s32), [[USUBE13:%[0-9]+]]:_(s1) = G_USUBE [[UV23]], [[UV25]], [[USUBO9]]
; GFX9: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO8]](s32), [[USUBE12]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s64) = COPY [[MV5]](s64)
- ; GFX9: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; GFX9: $vgpr0_vgpr1 = COPY [[MV5]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s33) = G_TRUNC %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
index 1ed7d6ff29f11..c82b0a22e348a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
@@ -13,12 +13,10 @@ body: |
; GFX6-LABEL: name: sshlsat_s7
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C1]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[AND]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
@@ -29,8 +27,7 @@ body: |
; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[ASHR]]
; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SELECT]], [[SHL1]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SELECT1]], [[C1]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[ASHR1]](s32)
; GFX8-LABEL: name: sshlsat_s7
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -91,12 +88,10 @@ body: |
; GFX6-LABEL: name: sshlsat_s8
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C1]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[AND]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
@@ -107,8 +102,7 @@ body: |
; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[ASHR]]
; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SELECT]], [[SHL1]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SELECT1]], [[C1]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[ASHR1]](s32)
; GFX8-LABEL: name: sshlsat_s8
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -178,11 +172,9 @@ body: |
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32)
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[AND]](s32)
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
@@ -193,10 +185,8 @@ body: |
; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[ASHR]]
; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SELECT]], [[SHL1]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SELECT1]], [[C2]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]](s32)
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C2]](s32)
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[AND1]](s32)
; GFX6: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[AND1]](s32)
; GFX6: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SHL2]](s32), [[C6]]
@@ -207,10 +197,9 @@ body: |
; GFX6: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR1]](s32)
; GFX6: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C7]]
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ASHR3]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY6]](s32)
+ ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ASHR3]], [[C3]]
+ ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC1]]
; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -254,10 +243,8 @@ body: |
; GFX8: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s16), [[ASHR2]]
; GFX8: [[SELECT3:%[0-9]+]]:_(s16) = G_SELECT [[ICMP3]](s1), [[SELECT2]], [[SHL3]]
; GFX8: [[ASHR3:%[0-9]+]]:_(s16) = G_ASHR [[SELECT3]], [[C4]](s16)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
- ; GFX8: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C3]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s16) = COPY [[ASHR3]](s16)
- ; GFX8: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C3]]
+ ; GFX8: [[AND2:%[0-9]+]]:_(s16) = G_AND [[ASHR1]], [[C3]]
+ ; GFX8: [[AND3:%[0-9]+]]:_(s16) = G_AND [[ASHR3]], [[C3]]
; GFX8: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C4]](s16)
; GFX8: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL4]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -301,10 +288,8 @@ body: |
; GFX9: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s16), [[ASHR2]]
; GFX9: [[SELECT3:%[0-9]+]]:_(s16) = G_SELECT [[ICMP3]](s1), [[SELECT2]], [[SHL3]]
; GFX9: [[ASHR3:%[0-9]+]]:_(s16) = G_ASHR [[SELECT3]], [[C4]](s16)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
- ; GFX9: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C3]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s16) = COPY [[ASHR3]](s16)
- ; GFX9: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s16) = G_AND [[ASHR1]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s16) = G_AND [[ASHR3]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C4]](s16)
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL4]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -330,12 +315,10 @@ body: |
; GFX6-LABEL: name: sshlsat_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C1]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[AND]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
@@ -346,8 +329,7 @@ body: |
; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[ASHR]]
; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SELECT]], [[SHL1]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SELECT1]], [[C1]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[ASHR1]](s32)
; GFX8-LABEL: name: sshlsat_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -403,11 +385,9 @@ body: |
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[AND]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
@@ -418,10 +398,8 @@ body: |
; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[ASHR]]
; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SELECT]], [[SHL1]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SELECT1]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[AND1]](s32)
; GFX6: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[AND1]](s32)
; GFX6: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SHL2]](s32), [[C4]]
@@ -429,10 +407,8 @@ body: |
; GFX6: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s32), [[ASHR2]]
; GFX6: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[SELECT2]], [[SHL3]]
; GFX6: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SELECT3]], [[C]](s32)
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ASHR3]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ASHR3]], [[C1]]
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -526,11 +502,9 @@ body: |
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[AND]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
@@ -541,10 +515,8 @@ body: |
; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[ASHR]]
; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SELECT]], [[SHL1]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SELECT1]], [[C]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[AND1]](s32)
; GFX6: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[AND1]](s32)
; GFX6: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SHL2]](s32), [[C4]]
@@ -552,10 +524,8 @@ body: |
; GFX6: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s32), [[ASHR2]]
; GFX6: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[SELECT2]], [[SHL3]]
; GFX6: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SELECT3]], [[C]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[C]](s32)
; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[SHL4]], [[AND2]](s32)
; GFX6: [[ASHR4:%[0-9]+]]:_(s32) = G_ASHR [[SHL5]], [[AND2]](s32)
; GFX6: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SHL4]](s32), [[C4]]
@@ -572,24 +542,18 @@ body: |
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; GFX6: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ASHR3]](s32)
- ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
+ ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ASHR3]], [[C1]]
; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL6]]
; GFX6: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[ASHR5]](s32)
- ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX6: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ASHR5]], [[C1]]
+ ; GFX6: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL7]]
; GFX6: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX6: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX6: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; GFX6: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; GFX6: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; GFX6: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
; GFX6: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL8]]
; GFX6: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -651,15 +615,12 @@ body: |
; GFX8: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[SELECT5]](s16)
; GFX8: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C4]]
; GFX8: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; GFX8: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C4]]
+ ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C4]]
; GFX8: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; GFX8: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL5]]
; GFX8: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -718,11 +679,8 @@ body: |
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT3]](s16)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX9: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT5]](s16)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[COPY1]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[BITCAST4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR4]](s32), [[BITCAST5]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
@@ -753,11 +711,9 @@ body: |
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND]](s32)
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[AND]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
@@ -768,10 +724,8 @@ body: |
; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[ASHR]]
; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SELECT]], [[SHL1]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SELECT1]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[AND1]](s32)
; GFX6: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL3]], [[AND1]](s32)
; GFX6: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SHL2]](s32), [[C4]]
@@ -779,10 +733,8 @@ body: |
; GFX6: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s32), [[ASHR2]]
; GFX6: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[SELECT2]], [[SHL3]]
; GFX6: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SELECT3]], [[C]](s32)
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32)
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[C]](s32)
; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[SHL4]], [[AND2]](s32)
; GFX6: [[ASHR4:%[0-9]+]]:_(s32) = G_ASHR [[SHL5]], [[AND2]](s32)
; GFX6: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SHL4]](s32), [[C4]]
@@ -790,10 +742,8 @@ body: |
; GFX6: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL4]](s32), [[ASHR4]]
; GFX6: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s1), [[SELECT4]], [[SHL5]]
; GFX6: [[ASHR5:%[0-9]+]]:_(s32) = G_ASHR [[SELECT5]], [[C]](s32)
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C]](s32)
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[SHL6]], [[AND3]](s32)
; GFX6: [[ASHR6:%[0-9]+]]:_(s32) = G_ASHR [[SHL7]], [[AND3]](s32)
; GFX6: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SHL6]](s32), [[C4]]
@@ -801,17 +751,13 @@ body: |
; GFX6: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL6]](s32), [[ASHR6]]
; GFX6: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s1), [[SELECT6]], [[SHL7]]
; GFX6: [[ASHR7:%[0-9]+]]:_(s32) = G_ASHR [[SELECT7]], [[C]](s32)
- ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[ASHR3]](s32)
- ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C1]]
+ ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ASHR3]], [[C1]]
; GFX6: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL8]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[ASHR5]](s32)
- ; GFX6: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[ASHR7]](s32)
- ; GFX6: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; GFX6: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ASHR5]], [[C1]]
+ ; GFX6: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ASHR7]], [[C1]]
; GFX6: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL9]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssube.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssube.mir
index d1f8a530c49fe..31126e0991996 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssube.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssube.mir
@@ -68,17 +68,13 @@ body: |
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY %13(s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %13, 16
; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[SEXT_INREG]], [[SEXT_INREG1]], [[ICMP]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[USUBE]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[USUBE]], 16
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[USUBE]](s32), [[SEXT_INREG2]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[USUBE]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP1]](s1)
- ; CHECK: $vgpr0 = COPY [[COPY6]](s32)
+ ; CHECK: $vgpr0 = COPY [[USUBE]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
index bce6a36f46869..b43b54ea91985 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
@@ -10,24 +10,17 @@ body: |
; CHECK-LABEL: name: test_ssubo_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
+ ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 7
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 7
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 7
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 7
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 7
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 7
- ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG2]](s32), [[SEXT_INREG3]]
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 7
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG2]](s32), [[COPY2]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[XOR]](s1)
; CHECK: $vgpr0 = COPY [[AND]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
@@ -51,22 +44,16 @@ body: |
; CHECK-LABEL: name: test_ssubo_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
+ ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 16
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 16
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG2]](s32), [[C]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[XOR]](s1)
- ; CHECK: $vgpr0 = COPY [[COPY7]](s32)
+ ; CHECK: $vgpr0 = COPY [[SUB]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -147,51 +134,37 @@ body: |
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY4]], [[COPY5]]
+ ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[BITCAST]], [[BITCAST1]]
+ ; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[LSHR]], [[LSHR1]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 16
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 16
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 16
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST3]], 16
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY10]], 16
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY11]], 16
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB1]], 16
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR2]], 16
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[SEXT_INREG3]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY12]], 16
+ ; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST4]], 16
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG4]](s32), [[COPY13]]
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY14]], 16
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG4]](s32), [[COPY2]]
+ ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR3]], 16
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG5]](s32), [[C2]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP2]], [[ICMP]]
; CHECK: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP3]], [[ICMP1]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR1]](s1)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND2]](s32), [[AND3]](s32)
; CHECK: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
; CHECK: $vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<2 x s32>)
@@ -222,15 +195,9 @@ body: |
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY4]], [[COPY5]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY6]], [[COPY7]]
+ ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[BITCAST]], [[BITCAST2]]
+ ; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[LSHR]], [[LSHR2]]
+ ; CHECK: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[BITCAST1]], [[BITCAST3]]
; CHECK: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; CHECK: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; CHECK: [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>), [[UV8:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
@@ -238,37 +205,28 @@ body: |
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; CHECK: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 16
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 16
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 16
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST4]], 16
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY10]], 16
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY11]], 16
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB1]], 16
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR4]], 16
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[SEXT_INREG3]]
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SUB2]](s32)
- ; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY12]], 16
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY13]], 16
+ ; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB2]], 16
+ ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST5]], 16
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG4]](s32), [[SEXT_INREG5]]
; CHECK: [[UV9:%[0-9]+]]:_(<2 x s16>), [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<6 x s16>)
; CHECK: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[UV9]](<2 x s16>)
; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; CHECK: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV10]](<2 x s16>)
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY14]], 16
+ ; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST6]], 16
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG6]](s32), [[COPY15]]
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY16]], 16
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG7]](s32), [[COPY17]]
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY18]], 16
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG6]](s32), [[COPY2]]
+ ; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR6]], 16
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG7]](s32), [[COPY3]]
+ ; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST7]], 16
; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG8]](s32), [[C1]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP3]], [[ICMP]]
; CHECK: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP4]], [[ICMP1]]
@@ -284,35 +242,26 @@ body: |
; CHECK: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[UV13]](<2 x s16>)
; CHECK: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C2]]
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C2]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C2]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[SUB2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C2]]
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C2]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB2]], [[C2]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST8]], [[C2]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C2]]
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C2]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C2]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST9]], [[C2]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST10]](<2 x s16>), [[BITCAST11]](<2 x s16>), [[BITCAST12]](<2 x s16>)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C3]]
- ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C3]]
- ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C3]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C3]]
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND6]](s32), [[AND7]](s32), [[AND8]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
@@ -348,30 +297,18 @@ body: |
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY4]], [[COPY5]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY6]], [[COPY7]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[COPY8]], [[COPY9]]
+ ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[BITCAST]], [[BITCAST2]]
+ ; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[LSHR]], [[LSHR2]]
+ ; CHECK: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[BITCAST1]], [[BITCAST3]]
+ ; CHECK: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[LSHR1]], [[LSHR3]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SUB2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[SUB3]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB2]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB3]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -381,46 +318,34 @@ body: |
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; CHECK: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY14]], 16
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY15]], 16
+ ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB]], 16
+ ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST6]], 16
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY16]], 16
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY17]], 16
+ ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB1]], 16
+ ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR4]], 16
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[SEXT_INREG3]]
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[SUB2]](s32)
- ; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY18]], 16
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY19]], 16
+ ; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB2]], 16
+ ; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST7]], 16
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG4]](s32), [[SEXT_INREG5]]
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[SUB3]](s32)
- ; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY20]], 16
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY21]], 16
+ ; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SUB3]], 16
+ ; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR5]], 16
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG6]](s32), [[SEXT_INREG7]]
; CHECK: [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
; CHECK: [[BITCAST8:%[0-9]+]]:_(s32) = G_BITCAST [[UV6]](<2 x s16>)
; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST8]], [[C]](s32)
; CHECK: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C]](s32)
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
- ; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY22]], 16
+ ; CHECK: [[SEXT_INREG8:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST8]], 16
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG8]](s32), [[COPY23]]
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY24]], 16
- ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG9]](s32), [[COPY25]]
- ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
- ; CHECK: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY26]], 16
- ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG10]](s32), [[COPY27]]
- ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CHECK: [[SEXT_INREG11:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY28]], 16
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG8]](s32), [[COPY2]]
+ ; CHECK: [[SEXT_INREG9:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR6]], 16
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG9]](s32), [[COPY3]]
+ ; CHECK: [[SEXT_INREG10:%[0-9]+]]:_(s32) = G_SEXT_INREG [[BITCAST9]], 16
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG10]](s32), [[COPY4]]
+ ; CHECK: [[SEXT_INREG11:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LSHR7]], 16
; CHECK: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG11]](s32), [[C2]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP4]], [[ICMP]]
; CHECK: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP5]], [[ICMP1]]
@@ -431,14 +356,10 @@ body: |
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR2]](s1)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR3]](s1)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C3]]
- ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C3]]
- ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C3]]
- ; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY32]], [[C3]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C3]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C3]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C3]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND4]](s32), [[AND5]](s32), [[AND6]](s32), [[AND7]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
; CHECK: $vgpr2_vgpr3_vgpr4_vgpr5 = COPY [[BUILD_VECTOR]](<4 x s32>)
@@ -476,10 +397,8 @@ body: |
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR1]](s1)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; CHECK: $vgpr2_vgpr3 = COPY [[BUILD_VECTOR1]](<2 x s32>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
index 745408cfc0c8a..2f36f898881a8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
@@ -13,11 +13,9 @@ body: |
; GFX6-LABEL: name: ssubsat_s7
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
@@ -29,8 +27,7 @@ body: |
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[ASHR]](s32)
; GFX8-LABEL: name: ssubsat_s7
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -82,11 +79,9 @@ body: |
; GFX6-LABEL: name: ssubsat_s8
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
@@ -98,8 +93,7 @@ body: |
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[ASHR]](s32)
; GFX8-LABEL: name: ssubsat_s8
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -160,10 +154,8 @@ body: |
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C2]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C2]](s32)
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; GFX6: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
@@ -175,10 +167,8 @@ body: |
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C2]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]](s32)
- ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C2]](s32)
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C2]](s32)
+ ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR3]], [[C2]](s32)
; GFX6: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SHL2]], [[C5]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SMAX2]], [[C3]]
; GFX6: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SHL2]], [[C5]]
@@ -190,11 +180,10 @@ body: |
; GFX6: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C6]]
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]
- ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY6]](s32)
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C7]]
+ ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY2]](s32)
; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -240,10 +229,8 @@ body: |
; GFX8: [[SUB5:%[0-9]+]]:_(s16) = G_SUB [[SHL2]], [[SMIN3]]
; GFX8: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[SUB5]], [[C3]](s16)
; GFX8: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX8: [[COPY2:%[0-9]+]]:_(s16) = COPY [[ASHR]](s16)
- ; GFX8: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C7]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
- ; GFX8: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C7]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s16) = G_AND [[ASHR]], [[C7]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s16) = G_AND [[ASHR1]], [[C7]]
; GFX8: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16)
; GFX8: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -260,15 +247,11 @@ body: |
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[LSHR]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[LSHR3]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY6]](s32)
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY2]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[SHL1:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[SSUBSAT:%[0-9]+]]:_(<2 x s16>) = G_SSUBSAT [[SHL]], [[SHL1]]
@@ -278,10 +261,8 @@ body: |
; GFX9: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR6]](s32)
; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX9: [[COPY7:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
- ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
- ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C4]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C4]]
; GFX9: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16)
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL2]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -307,11 +288,9 @@ body: |
; GFX6-LABEL: name: ssubsat_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
@@ -323,8 +302,7 @@ body: |
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[ASHR]](s32)
; GFX8-LABEL: name: ssubsat_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -373,10 +351,8 @@ body: |
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
@@ -388,10 +364,8 @@ body: |
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
- ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
; GFX6: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SHL2]], [[C3]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SMAX2]], [[C1]]
; GFX6: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SHL2]], [[C3]]
@@ -401,10 +375,8 @@ body: |
; GFX6: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SHL2]], [[SMIN3]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SUB5]], [[C]](s32)
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C4]]
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C4]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C4]]
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL4]]
; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -474,10 +446,8 @@ body: |
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
@@ -489,10 +459,8 @@ body: |
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
- ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[BITCAST3]], [[C]](s32)
; GFX6: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SHL2]], [[C3]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SMAX2]], [[C1]]
; GFX6: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SHL2]], [[C3]]
@@ -501,10 +469,8 @@ body: |
; GFX6: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB4]]
; GFX6: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SHL2]], [[SMIN3]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SUB5]], [[C]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)
- ; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32)
+ ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[C]](s32)
+ ; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[LSHR3]], [[C]](s32)
; GFX6: [[SMAX4:%[0-9]+]]:_(s32) = G_SMAX [[SHL4]], [[C3]]
; GFX6: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SMAX4]], [[C1]]
; GFX6: [[SMIN4:%[0-9]+]]:_(s32) = G_SMIN [[SHL4]], [[C3]]
@@ -523,24 +489,18 @@ body: |
; GFX6: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C4]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C4]]
; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL6]]
; GFX6: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[ASHR2]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C4]]
- ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C4]]
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ASHR2]], [[C4]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C4]]
; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL7]]
; GFX6: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C4]]
- ; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C4]]
+ ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C4]]
+ ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C4]]
; GFX6: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX6: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL8]]
; GFX6: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -605,15 +565,12 @@ body: |
; GFX8: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[SUB8]](s16)
; GFX8: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C4]]
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; GFX8: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C4]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C4]]
+ ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C4]]
; GFX8: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; GFX8: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; GFX8: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -627,23 +584,17 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[DEF]](s32)
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[BITCAST3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR3]](s32), [[DEF]](s32)
; GFX9: [[SSUBSAT:%[0-9]+]]:_(<2 x s16>) = G_SSUBSAT [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]]
; GFX9: [[SSUBSAT1:%[0-9]+]]:_(<2 x s16>) = G_SSUBSAT [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]]
; GFX9: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@@ -657,15 +608,9 @@ body: |
; GFX9: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; GFX9: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; GFX9: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST4]](s32), [[LSHR4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST5]](s32), [[BITCAST6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR6]](s32), [[BITCAST7]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC4]](<2 x s16>), [[BUILD_VECTOR_TRUNC5]](<2 x s16>), [[BUILD_VECTOR_TRUNC6]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
@@ -696,10 +641,8 @@ body: |
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[BITCAST2]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
@@ -711,10 +654,8 @@ body: |
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
- ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[C]](s32)
; GFX6: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SHL2]], [[C3]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SMAX2]], [[C1]]
; GFX6: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SHL2]], [[C3]]
@@ -723,10 +664,8 @@ body: |
; GFX6: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB4]]
; GFX6: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SHL2]], [[SMIN3]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SUB5]], [[C]](s32)
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32)
- ; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C]](s32)
+ ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[C]](s32)
+ ; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[BITCAST3]], [[C]](s32)
; GFX6: [[SMAX4:%[0-9]+]]:_(s32) = G_SMAX [[SHL4]], [[C3]]
; GFX6: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SMAX4]], [[C1]]
; GFX6: [[SMIN4:%[0-9]+]]:_(s32) = G_SMIN [[SHL4]], [[C3]]
@@ -735,10 +674,8 @@ body: |
; GFX6: [[SMIN5:%[0-9]+]]:_(s32) = G_SMIN [[SMAX5]], [[SUB7]]
; GFX6: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SHL4]], [[SMIN5]]
; GFX6: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SUB8]], [[C]](s32)
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C]](s32)
- ; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C]](s32)
+ ; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
+ ; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[LSHR3]], [[C]](s32)
; GFX6: [[SMAX6:%[0-9]+]]:_(s32) = G_SMAX [[SHL6]], [[C3]]
; GFX6: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[SMAX6]], [[C1]]
; GFX6: [[SMIN6:%[0-9]+]]:_(s32) = G_SMIN [[SHL6]], [[C3]]
@@ -748,17 +685,13 @@ body: |
; GFX6: [[SUB11:%[0-9]+]]:_(s32) = G_SUB [[SHL6]], [[SMIN7]]
; GFX6: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SUB11]], [[C]](s32)
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C4]]
- ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C4]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C4]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ASHR1]], [[C4]]
; GFX6: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL8]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[ASHR2]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C4]]
- ; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[ASHR3]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C4]]
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ASHR2]], [[C4]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ASHR3]], [[C4]]
; GFX6: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL9]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
index 535d613c2d955..0008df59be2fc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
@@ -22,32 +22,28 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
; SI: G_STORE [[AND1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; CI-LABEL: name: test_store_global_s1_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
; CI: G_STORE [[AND1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI-LABEL: name: test_store_global_s1_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
; VI: G_STORE [[AND1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; GFX9-LABEL: name: test_store_global_s1_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
; GFX9: G_STORE [[AND1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1
@@ -65,30 +61,26 @@ body: |
; SI-LABEL: name: test_store_global_s7_align1
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: G_STORE [[AND]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; CI-LABEL: name: test_store_global_s7_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CI: G_STORE [[AND]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI-LABEL: name: test_store_global_s7_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: G_STORE [[AND]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; GFX9-LABEL: name: test_store_global_s7_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: G_STORE [[AND]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
@@ -105,23 +97,19 @@ body: |
; SI-LABEL: name: test_store_global_s8_align1
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; CI-LABEL: name: test_store_global_s8_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; CI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI-LABEL: name: test_store_global_s8_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; GFX9-LABEL: name: test_store_global_s8_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; GFX9: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s8) = G_TRUNC %1
@@ -143,17 +131,14 @@ body: |
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; CI-LABEL: name: test_store_global_s16_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), align 1, addrspace 1)
+ ; CI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), align 1, addrspace 1)
; VI-LABEL: name: test_store_global_s16_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
@@ -163,17 +148,14 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; GFX9-LABEL: name: test_store_global_s16_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), align 1, addrspace 1)
+ ; GFX9: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), align 1, addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s16) = G_TRUNC %1
@@ -189,23 +171,19 @@ body: |
; SI-LABEL: name: test_store_global_s16_align2
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; CI-LABEL: name: test_store_global_s16_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; CI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI-LABEL: name: test_store_global_s16_align2
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; GFX9-LABEL: name: test_store_global_s16_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; GFX9: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s16) = G_TRUNC %1
@@ -221,23 +199,19 @@ body: |
; SI-LABEL: name: test_store_global_s16_align4
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
+ ; SI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
; CI-LABEL: name: test_store_global_s16_align4
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
+ ; CI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
; VI-LABEL: name: test_store_global_s16_align4
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
+ ; VI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
; GFX9-LABEL: name: test_store_global_s16_align4
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
+ ; GFX9: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s16) = G_TRUNC %1
@@ -254,45 +228,41 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C]](s32)
+ ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
+ ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
; CI-LABEL: name: test_store_global_s24_align4
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C]](s32)
+ ; CI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C]](s32)
; CI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CI: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
+ ; CI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
; CI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
; VI-LABEL: name: test_store_global_s24_align4
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C]](s32)
+ ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
+ ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
; GFX9-LABEL: name: test_store_global_s24_align4
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C]](s32)
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; GFX9: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
+ ; GFX9: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
; GFX9: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
@@ -309,58 +279,46 @@ body: |
; SI-LABEL: name: test_store_global_s24_align2
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
+ ; SI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
; CI-LABEL: name: test_store_global_s24_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C]](s32)
+ ; CI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C]](s32)
; CI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CI: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; CI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; CI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
; VI-LABEL: name: test_store_global_s24_align2
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
+ ; VI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
; GFX9-LABEL: name: test_store_global_s24_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C]](s32)
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; GFX9: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; GFX9: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; GFX9: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
@@ -377,74 +335,60 @@ body: |
; SI-LABEL: name: test_store_global_s24_align1
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C2]](s32)
+ ; SI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; CI-LABEL: name: test_store_global_s24_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C]](s32)
+ ; CI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C]](s32)
; CI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CI: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s16), align 1, addrspace 1)
+ ; CI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), align 1, addrspace 1)
; CI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI-LABEL: name: test_store_global_s24_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
+ ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
; VI: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; VI: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C2]](s16)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; VI: G_STORE [[ANYEXT]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; GFX9-LABEL: name: test_store_global_s24_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C]](s32)
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; GFX9: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s16), align 1, addrspace 1)
+ ; GFX9: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), align 1, addrspace 1)
; GFX9: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
@@ -461,30 +405,26 @@ body: |
; SI-LABEL: name: test_store_global_s25_align4
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33554431
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: G_STORE [[AND]](s32), [[COPY]](p1) :: (store (s32), addrspace 1)
; CI-LABEL: name: test_store_global_s25_align4
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33554431
- ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; CI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CI: G_STORE [[AND]](s32), [[COPY]](p1) :: (store (s32), addrspace 1)
; VI-LABEL: name: test_store_global_s25_align4
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33554431
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: G_STORE [[AND]](s32), [[COPY]](p1) :: (store (s32), addrspace 1)
; GFX9-LABEL: name: test_store_global_s25_align4
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 33554431
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: G_STORE [[AND]](s32), [[COPY]](p1) :: (store (s32), addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
@@ -531,20 +471,16 @@ body: |
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; CI-LABEL: name: test_store_global_s32_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
@@ -558,20 +494,16 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; GFX9-LABEL: name: test_store_global_s32_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
@@ -592,12 +524,10 @@ body: |
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; CI-LABEL: name: test_store_global_s32_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
@@ -607,12 +537,10 @@ body: |
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; GFX9-LABEL: name: test_store_global_s32_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
@@ -665,20 +593,16 @@ body: |
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C2]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[PTRTOINT]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[PTRTOINT]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; CI-LABEL: name: test_store_global_p3_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr2
@@ -693,20 +617,16 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C2]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[PTRTOINT]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[PTRTOINT]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; GFX9-LABEL: name: test_store_global_p3_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr2
@@ -728,12 +648,10 @@ body: |
; SI: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY1]](p3)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[PTRTOINT]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[PTRTOINT]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; CI-LABEL: name: test_store_global_p3_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr2
@@ -744,12 +662,10 @@ body: |
; VI: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY1]](p3)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[PTRTOINT]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[PTRTOINT]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; GFX9-LABEL: name: test_store_global_p3_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr2
@@ -795,80 +711,65 @@ body: |
; SI-LABEL: name: test_store_global_s48_align1
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; SI: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; SI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY2]](s64), 0
- ; SI: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; SI: [[EXTRACT1:%[0-9]+]]:_(s16) = G_EXTRACT [[COPY3]](s64), 32
+ ; SI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](s64), 0
+ ; SI: [[EXTRACT1:%[0-9]+]]:_(s16) = G_EXTRACT [[COPY1]](s64), 32
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT]], [[C2]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[EXTRACT]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[EXTRACT1]](s16)
- ; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT]], [[COPY8]](s32)
+ ; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT]], [[COPY2]](s32)
; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT1]](s16)
; SI: G_STORE [[ANYEXT]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; CI-LABEL: name: test_store_global_s48_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; CI: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; CI: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY2]](s64)
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY3]], [[C]](s32)
+ ; CI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C]](s32)
; CI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64)
+ ; CI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CI: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store (s32), align 1, addrspace 1)
; CI: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; CI: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, align 1, addrspace 1)
; VI-LABEL: name: test_store_global_s48_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; VI: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; VI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY2]](s64), 0
- ; VI: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; VI: [[EXTRACT1:%[0-9]+]]:_(s16) = G_EXTRACT [[COPY3]](s64), 32
+ ; VI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](s64), 0
+ ; VI: [[EXTRACT1:%[0-9]+]]:_(s16) = G_EXTRACT [[COPY1]](s64), 32
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT]], [[C2]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[EXTRACT]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; VI: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
@@ -881,13 +782,11 @@ body: |
; GFX9-LABEL: name: test_store_global_s48_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; GFX9: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY2]](s64)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY3]], [[C]](s32)
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64)
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; GFX9: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store (s32), align 1, addrspace 1)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; GFX9: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, align 1, addrspace 1)
@@ -906,18 +805,14 @@ body: |
; SI-LABEL: name: test_store_global_s48_align2
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; SI: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; SI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY2]](s64), 0
- ; SI: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; SI: [[EXTRACT1:%[0-9]+]]:_(s16) = G_EXTRACT [[COPY3]](s64), 32
+ ; SI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](s64), 0
+ ; SI: [[EXTRACT1:%[0-9]+]]:_(s16) = G_EXTRACT [[COPY1]](s64), 32
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT]], [[C]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[EXTRACT]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT1]](s16)
@@ -925,31 +820,25 @@ body: |
; CI-LABEL: name: test_store_global_s48_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; CI: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; CI: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY2]](s64)
; CI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; CI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY3]], [[C]](s32)
+ ; CI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C]](s32)
; CI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; CI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64)
+ ; CI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CI: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store (s32), align 2, addrspace 1)
; CI: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; CI: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI-LABEL: name: test_store_global_s48_align2
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; VI: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; VI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY2]](s64), 0
- ; VI: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; VI: [[EXTRACT1:%[0-9]+]]:_(s16) = G_EXTRACT [[COPY3]](s64), 32
+ ; VI: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](s64), 0
+ ; VI: [[EXTRACT1:%[0-9]+]]:_(s16) = G_EXTRACT [[COPY1]](s64), 32
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT]], [[C]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[EXTRACT]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[EXTRACT1]](s16)
@@ -957,13 +846,11 @@ body: |
; GFX9-LABEL: name: test_store_global_s48_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; GFX9: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY2]](s64)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
- ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY3]], [[C]](s32)
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; GFX9: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY3]](s64)
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; GFX9: G_STORE [[TRUNC]](s32), [[COPY]](p1) :: (store (s32), align 2, addrspace 1)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
; GFX9: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
@@ -1014,50 +901,38 @@ body: |
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
- ; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY4]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
- ; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY6]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C2]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
+ ; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY4]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C1]](s32)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY12]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY13]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY14]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY15]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C9]](s64)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY16]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; CI-LABEL: name: test_store_global_s64_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
@@ -1078,32 +953,28 @@ body: |
; VI: [[LSHR3:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; VI: [[LSHR4:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC2]], [[C1]](s16)
; VI: [[LSHR5:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC3]], [[C1]](s16)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
; VI: G_STORE [[ANYEXT]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; VI: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR3]](s16)
; VI: G_STORE [[ANYEXT1]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; VI: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR4]](s16)
; VI: G_STORE [[ANYEXT2]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; VI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; VI: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR5]](s16)
@@ -1130,20 +1001,16 @@ body: |
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; CI-LABEL: name: test_store_global_s64_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
@@ -1155,20 +1022,16 @@ body: |
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; GFX9-LABEL: name: test_store_global_s64_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
@@ -1275,50 +1138,38 @@ body: |
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
- ; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY4]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
- ; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY6]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C2]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
+ ; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY4]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C1]](s32)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY12]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY13]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY14]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY15]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C9]](s64)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY16]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; CI-LABEL: name: test_store_global_p0_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr2_vgpr3
@@ -1339,32 +1190,28 @@ body: |
; VI: [[LSHR3:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; VI: [[LSHR4:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC2]], [[C1]](s16)
; VI: [[LSHR5:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC3]], [[C1]](s16)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
; VI: G_STORE [[ANYEXT]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; VI: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR3]](s16)
; VI: G_STORE [[ANYEXT1]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; VI: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR4]](s16)
; VI: G_STORE [[ANYEXT2]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; VI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; VI: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR5]](s16)
@@ -1391,20 +1238,16 @@ body: |
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; CI-LABEL: name: test_store_global_p0_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr2_vgpr3
@@ -1416,20 +1259,16 @@ body: |
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; GFX9-LABEL: name: test_store_global_p0_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(p0) = COPY $vgpr2_vgpr3
@@ -1536,50 +1375,38 @@ body: |
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
- ; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY4]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
- ; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY6]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C2]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
+ ; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY4]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C1]](s32)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY12]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY13]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY14]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY15]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C9]](s64)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY16]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; CI-LABEL: name: test_store_global_p999_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(p999) = COPY $vgpr2_vgpr3
@@ -1600,32 +1427,28 @@ body: |
; VI: [[LSHR3:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; VI: [[LSHR4:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC2]], [[C1]](s16)
; VI: [[LSHR5:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC3]], [[C1]](s16)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
; VI: G_STORE [[ANYEXT]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; VI: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR3]](s16)
; VI: G_STORE [[ANYEXT1]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; VI: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR4]](s16)
; VI: G_STORE [[ANYEXT2]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; VI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; VI: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR5]](s16)
@@ -1652,20 +1475,16 @@ body: |
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; CI-LABEL: name: test_store_global_p999_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(p999) = COPY $vgpr2_vgpr3
@@ -1677,20 +1496,16 @@ body: |
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; GFX9-LABEL: name: test_store_global_p999_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(p999) = COPY $vgpr2_vgpr3
@@ -1797,36 +1612,28 @@ body: |
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; CI-LABEL: name: test_store_global_v2s32_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
@@ -1841,36 +1648,28 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; VI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; GFX9-LABEL: name: test_store_global_v2s32_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
@@ -1892,20 +1691,16 @@ body: |
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; CI-LABEL: name: test_store_global_v2s32_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
@@ -1916,20 +1711,16 @@ body: |
; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; GFX9-LABEL: name: test_store_global_v2s32_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
@@ -2037,37 +1828,29 @@ body: |
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C2]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[PTRTOINT]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[PTRTOINT]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; SI: [[PTRTOINT1:%[0-9]+]]:_(s32) = G_PTRTOINT [[UV1]](p3)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT1]], [[C]](s32)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT1]], [[C1]](s32)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT1]], [[C2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[PTRTOINT1]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[PTRTOINT1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; CI-LABEL: name: test_store_global_v2p3_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr2_vgpr3
@@ -2083,37 +1866,29 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C2]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[PTRTOINT]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[PTRTOINT]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; VI: [[PTRTOINT1:%[0-9]+]]:_(s32) = G_PTRTOINT [[UV1]](p3)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT1]], [[C]](s32)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT1]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT1]], [[C2]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[PTRTOINT1]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[PTRTOINT1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; VI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; GFX9-LABEL: name: test_store_global_v2p3_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr2_vgpr3
@@ -2136,21 +1911,17 @@ body: |
; SI: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[UV]](p3)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[PTRTOINT]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[PTRTOINT]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[PTRTOINT1:%[0-9]+]]:_(s32) = G_PTRTOINT [[UV1]](p3)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT1]], [[C]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[PTRTOINT1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[PTRTOINT1]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; CI-LABEL: name: test_store_global_v2p3_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr2_vgpr3
@@ -2162,21 +1933,17 @@ body: |
; VI: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[UV]](p3)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[PTRTOINT]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[PTRTOINT]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[PTRTOINT1:%[0-9]+]]:_(s32) = G_PTRTOINT [[UV1]](p3)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT1]], [[C]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[PTRTOINT1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[PTRTOINT1]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; GFX9-LABEL: name: test_store_global_v2p3_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x p3>) = COPY $vgpr2_vgpr3
@@ -2284,44 +2051,36 @@ body: |
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C2]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[BITCAST]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C3]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
; SI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C1]](s32)
; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[BITCAST2]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; SI: G_STORE [[LSHR6]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; SI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C2]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR10]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; SI: G_STORE [[LSHR11]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; CI-LABEL: name: test_store_global_v4s16_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
@@ -2337,44 +2096,36 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C2]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[BITCAST]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; VI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C2]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C3]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; VI: G_STORE [[LSHR5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
; VI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; VI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; VI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C1]](s32)
; VI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C2]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[BITCAST2]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; VI: G_STORE [[LSHR6]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
; VI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; VI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; VI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C1]](s32)
; VI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C2]](s32)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR10]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C3]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; VI: G_STORE [[LSHR11]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; GFX9-LABEL: name: test_store_global_v4s16_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
@@ -2399,20 +2150,16 @@ body: |
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[BITCAST]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[BITCAST1]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; CI-LABEL: name: test_store_global_v4s16_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
@@ -2426,20 +2173,16 @@ body: |
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; VI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[BITCAST]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[BITCAST1]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; GFX9-LABEL: name: test_store_global_v4s16_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
@@ -2548,52 +2291,40 @@ body: |
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; SI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C1]](s32)
; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C2]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[EXTRACT1]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[EXTRACT1]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; SI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; SI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; CI-LABEL: name: test_store_global_v3s32_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
@@ -2610,52 +2341,40 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; VI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; VI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; VI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
; VI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C1]](s32)
; VI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C2]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[EXTRACT1]](s32)
- ; VI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[EXTRACT1]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; VI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; VI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; VI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; VI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; GFX9-LABEL: name: test_store_global_v3s32_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
@@ -2679,28 +2398,22 @@ body: |
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[EXTRACT]](<2 x s32>)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[EXTRACT1]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[EXTRACT1]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; CI-LABEL: name: test_store_global_v3s32_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
@@ -2713,28 +2426,22 @@ body: |
; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[EXTRACT]](<2 x s32>)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[EXTRACT1]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[EXTRACT1]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; GFX9-LABEL: name: test_store_global_v3s32_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
@@ -2856,68 +2563,52 @@ body: |
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; SI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; SI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; SI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; SI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; SI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C3]](s64)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; SI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; SI: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; SI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C5]](s64)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; SI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; SI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; CI-LABEL: name: test_store_global_v4s32_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
@@ -2932,68 +2623,52 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; VI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; VI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; VI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; VI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; VI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; VI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; VI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; VI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; VI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; VI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; VI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; VI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; VI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C3]](s64)
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; VI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; VI: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; VI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; VI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C5]](s64)
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; VI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; VI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; GFX9-LABEL: name: test_store_global_v4s32_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
@@ -3016,36 +2691,28 @@ body: |
; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](<2 x s32>)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<2 x s32>)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; CI-LABEL: name: test_store_global_v4s32_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
@@ -3057,36 +2724,28 @@ body: |
; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](<2 x s32>)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; VI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<2 x s32>)
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; GFX9-LABEL: name: test_store_global_v4s32_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
@@ -3194,94 +2853,70 @@ body: |
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C2]]
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
- ; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY4]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
- ; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY6]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C2]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C2]]
+ ; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY4]](s32)
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C1]](s32)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY12]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY13]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY14]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY15]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C9]](s64)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY16]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; SI: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C10]](s64)
; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C2]]
- ; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY17]](s32)
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C2]]
- ; SI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY19]](s32)
- ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C2]]
- ; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY21]](s32)
- ; SI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C2]]
- ; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY23]](s32)
- ; SI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; SI: G_STORE [[COPY25]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[C2]]
+ ; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY5]](s32)
+ ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C2]]
+ ; SI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY6]](s32)
+ ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C2]]
+ ; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY7]](s32)
+ ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C2]]
+ ; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY8]](s32)
+ ; SI: G_STORE [[UV4]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; SI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: G_STORE [[COPY26]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; SI: G_STORE [[LSHR8]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; SI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: G_STORE [[COPY27]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR6]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; SI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; SI: G_STORE [[COPY28]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; SI: G_STORE [[LSHR9]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; SI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C6]](s64)
- ; SI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; SI: G_STORE [[COPY29]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV5]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C7]](s64)
- ; SI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; SI: G_STORE [[COPY30]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; SI: G_STORE [[LSHR10]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C8]](s64)
- ; SI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: G_STORE [[COPY31]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR7]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C9]](s64)
- ; SI: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; SI: G_STORE [[COPY32]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; SI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; CI-LABEL: name: test_store_global_v2s64_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
@@ -3303,32 +2938,28 @@ body: |
; VI: [[LSHR3:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; VI: [[LSHR4:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC2]], [[C1]](s16)
; VI: [[LSHR5:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC3]], [[C1]](s16)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
; VI: G_STORE [[ANYEXT]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; VI: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR3]](s16)
; VI: G_STORE [[ANYEXT1]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; VI: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR4]](s16)
; VI: G_STORE [[ANYEXT2]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; VI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; VI: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR5]](s16)
@@ -3346,26 +2977,22 @@ body: |
; VI: [[LSHR9:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC5]], [[C1]](s16)
; VI: [[LSHR10:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC6]], [[C1]](s16)
; VI: [[LSHR11:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC7]], [[C1]](s16)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV4]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; VI: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR8]](s16)
; VI: G_STORE [[ANYEXT4]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; VI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR6]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
; VI: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR9]](s16)
; VI: G_STORE [[ANYEXT5]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; VI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV5]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C6]](s64)
; VI: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR10]](s16)
; VI: G_STORE [[ANYEXT6]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; VI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C7]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR7]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C8]](s64)
; VI: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR11]](s16)
; VI: G_STORE [[ANYEXT7]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
@@ -3392,36 +3019,28 @@ body: |
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; CI-LABEL: name: test_store_global_v2s64_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
@@ -3434,36 +3053,28 @@ body: |
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; VI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; GFX9-LABEL: name: test_store_global_v2s64_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
@@ -3571,68 +3182,52 @@ body: |
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; SI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; SI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; SI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; SI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; SI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C3]](s64)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; SI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; SI: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; SI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C5]](s64)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; SI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; SI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; CI-LABEL: name: test_store_global_v8s16_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
@@ -3649,68 +3244,52 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; VI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; VI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; VI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; VI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; VI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; VI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; VI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; VI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; VI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; VI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; VI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; VI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; VI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C3]](s64)
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; VI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; VI: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; VI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; VI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C5]](s64)
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; VI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; VI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; GFX9-LABEL: name: test_store_global_v8s16_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
@@ -3735,36 +3314,28 @@ body: |
; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](<2 x s32>)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<2 x s32>)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; CI-LABEL: name: test_store_global_v8s16_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
@@ -3778,36 +3349,28 @@ body: |
; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](<2 x s32>)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; VI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<2 x s32>)
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; GFX9-LABEL: name: test_store_global_v8s16_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
@@ -3928,68 +3491,52 @@ body: |
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; SI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; SI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; SI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; SI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; SI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C3]](s64)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; SI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; SI: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; SI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C5]](s64)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; SI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; SI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; CI-LABEL: name: test_store_global_v2p0_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
@@ -4006,68 +3553,52 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; VI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; VI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; VI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; VI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; VI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; VI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; VI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; VI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; VI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; VI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; VI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; VI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; VI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C3]](s64)
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; VI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; VI: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; VI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; VI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C5]](s64)
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; VI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; VI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; GFX9-LABEL: name: test_store_global_v2p0_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
@@ -4092,36 +3623,28 @@ body: |
; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](<2 x s32>)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<2 x s32>)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; CI-LABEL: name: test_store_global_v2p0_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
@@ -4135,36 +3658,28 @@ body: |
; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](<2 x s32>)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; VI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<2 x s32>)
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; GFX9-LABEL: name: test_store_global_v2p0_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
@@ -4287,52 +3802,40 @@ body: |
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; SI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C1]](s32)
; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C2]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[EXTRACT1]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[EXTRACT1]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; SI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; SI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; CI-LABEL: name: test_store_global_s96_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr2_vgpr3_vgpr4
@@ -4351,52 +3854,40 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; VI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; VI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; VI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
; VI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C1]](s32)
; VI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C2]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[EXTRACT1]](s32)
- ; VI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[EXTRACT1]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; VI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; VI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; VI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; VI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; GFX9-LABEL: name: test_store_global_s96_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr2_vgpr3_vgpr4
@@ -4422,28 +3913,22 @@ body: |
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[EXTRACT]](<2 x s32>)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[EXTRACT1]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[EXTRACT1]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; CI-LABEL: name: test_store_global_s96_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr2_vgpr3_vgpr4
@@ -4458,28 +3943,22 @@ body: |
; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[EXTRACT]](<2 x s32>)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[EXTRACT1]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[EXTRACT1]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; GFX9-LABEL: name: test_store_global_s96_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s96) = COPY $vgpr2_vgpr3_vgpr4
@@ -4615,68 +4094,52 @@ body: |
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; SI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; SI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; SI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; SI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; SI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C3]](s64)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; SI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; SI: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; SI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C5]](s64)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; SI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; SI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; CI-LABEL: name: test_store_global_s128_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
@@ -4693,68 +4156,52 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; VI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; VI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; VI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; VI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; VI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; VI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; VI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; VI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; VI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; VI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; VI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; VI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; VI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C3]](s64)
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; VI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; VI: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; VI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; VI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C5]](s64)
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; VI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; VI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; GFX9-LABEL: name: test_store_global_s128_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
@@ -4779,36 +4226,28 @@ body: |
; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](<2 x s32>)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<2 x s32>)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; CI-LABEL: name: test_store_global_s128_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
@@ -4822,36 +4261,28 @@ body: |
; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](<2 x s32>)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; VI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<2 x s32>)
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; GFX9-LABEL: name: test_store_global_s128_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s128) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
@@ -4973,84 +4404,64 @@ body: |
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; SI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; SI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; SI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; SI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; SI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C3]](s64)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; SI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; SI: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; SI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C5]](s64)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; SI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; SI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; SI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI: [[PTR_ADD15:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C9]](s64)
; SI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
; SI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C1]](s32)
; SI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C2]](s32)
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[EXTRACT1]](s32)
- ; SI: G_STORE [[COPY18]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
+ ; SI: G_STORE [[EXTRACT1]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
; SI: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C3]](s64)
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; SI: G_STORE [[COPY19]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
+ ; SI: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
; SI: [[PTR_ADD17:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C4]](s64)
- ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; SI: G_STORE [[COPY20]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
+ ; SI: G_STORE [[LSHR13]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; SI: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C5]](s64)
- ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; SI: G_STORE [[COPY21]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
+ ; SI: G_STORE [[LSHR14]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
; CI-LABEL: name: test_store_global_v5s32_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<5 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
@@ -5072,84 +4483,64 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; VI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; VI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; VI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; VI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; VI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; VI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; VI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; VI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; VI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; VI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; VI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; VI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; VI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C3]](s64)
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; VI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; VI: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; VI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; VI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C5]](s64)
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; VI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; VI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; VI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI: [[PTR_ADD15:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C9]](s64)
; VI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
; VI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C1]](s32)
; VI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C2]](s32)
- ; VI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[EXTRACT1]](s32)
- ; VI: G_STORE [[COPY18]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
+ ; VI: G_STORE [[EXTRACT1]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
; VI: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C3]](s64)
- ; VI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; VI: G_STORE [[COPY19]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
+ ; VI: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
; VI: [[PTR_ADD17:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C4]](s64)
- ; VI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; VI: G_STORE [[COPY20]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
+ ; VI: G_STORE [[LSHR13]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; VI: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C5]](s64)
- ; VI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; VI: G_STORE [[COPY21]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
+ ; VI: G_STORE [[LSHR14]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
; GFX9-LABEL: name: test_store_global_v5s32_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<5 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
@@ -5179,44 +4570,34 @@ body: |
; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](<2 x s32>)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<2 x s32>)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[EXTRACT1]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
+ ; SI: G_STORE [[EXTRACT1]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
; CI-LABEL: name: test_store_global_v5s32_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<5 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
@@ -5235,44 +4616,34 @@ body: |
; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](<2 x s32>)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; VI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<2 x s32>)
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[EXTRACT1]](s32)
- ; VI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
+ ; VI: G_STORE [[EXTRACT1]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
; GFX9-LABEL: name: test_store_global_v5s32_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<5 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
@@ -5446,84 +4817,64 @@ body: |
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; SI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; SI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; SI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; SI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; SI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C3]](s64)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; SI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; SI: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; SI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C5]](s64)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; SI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; SI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; SI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI: [[PTR_ADD15:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C9]](s64)
; SI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
; SI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C1]](s32)
; SI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C2]](s32)
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[EXTRACT1]](s32)
- ; SI: G_STORE [[COPY18]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
+ ; SI: G_STORE [[EXTRACT1]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
; SI: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C3]](s64)
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; SI: G_STORE [[COPY19]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
+ ; SI: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
; SI: [[PTR_ADD17:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C4]](s64)
- ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; SI: G_STORE [[COPY20]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
+ ; SI: G_STORE [[LSHR13]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; SI: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C5]](s64)
- ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; SI: G_STORE [[COPY21]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
+ ; SI: G_STORE [[LSHR14]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
; CI-LABEL: name: test_store_global_v5p3_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<5 x p3>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
@@ -5547,84 +4898,64 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; VI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; VI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; VI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; VI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; VI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; VI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; VI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; VI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; VI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; VI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; VI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; VI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; VI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C3]](s64)
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; VI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; VI: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; VI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; VI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C5]](s64)
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; VI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; VI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; VI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI: [[PTR_ADD15:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C9]](s64)
; VI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
; VI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C1]](s32)
; VI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C2]](s32)
- ; VI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[EXTRACT1]](s32)
- ; VI: G_STORE [[COPY18]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
+ ; VI: G_STORE [[EXTRACT1]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
; VI: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C3]](s64)
- ; VI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; VI: G_STORE [[COPY19]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
+ ; VI: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
; VI: [[PTR_ADD17:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C4]](s64)
- ; VI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; VI: G_STORE [[COPY20]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
+ ; VI: G_STORE [[LSHR13]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; VI: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C5]](s64)
- ; VI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; VI: G_STORE [[COPY21]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
+ ; VI: G_STORE [[LSHR14]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
; GFX9-LABEL: name: test_store_global_v5p3_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<5 x p3>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
@@ -5656,44 +4987,34 @@ body: |
; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](<2 x s32>)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<2 x s32>)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[EXTRACT1]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
+ ; SI: G_STORE [[EXTRACT1]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
; CI-LABEL: name: test_store_global_v5p3_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<5 x p3>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
@@ -5714,44 +5035,34 @@ body: |
; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](<2 x s32>)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; VI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<2 x s32>)
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[EXTRACT1]](s32)
- ; VI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
+ ; VI: G_STORE [[EXTRACT1]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
; GFX9-LABEL: name: test_store_global_v5p3_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<5 x p3>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
@@ -6010,16 +5321,13 @@ body: |
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; SI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV79]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C1]](s32)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: G_STORE [[COPY1]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 16, align 16, addrspace 1)
+ ; SI: G_STORE [[BITCAST1]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 16, align 16, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C2]](s64)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C3]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 20, align 4, addrspace 1)
+ ; SI: G_STORE [[BITCAST2]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 20, align 4, addrspace 1)
; CI-LABEL: name: test_store_global_v11s16_align4
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[DEF:%[0-9]+]]:_(<12 x s16>) = G_IMPLICIT_DEF
@@ -6053,16 +5361,13 @@ body: |
; CI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; CI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV79]](<2 x s16>)
; CI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C1]](s32)
- ; CI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CI: G_STORE [[COPY1]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 16, align 16, addrspace 1)
+ ; CI: G_STORE [[BITCAST1]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 16, align 16, addrspace 1)
; CI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C2]](s64)
- ; CI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CI: G_STORE [[COPY2]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
+ ; CI: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
; CI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C3]](s64)
- ; CI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CI: G_STORE [[COPY3]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 20, align 4, addrspace 1)
+ ; CI: G_STORE [[BITCAST2]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 20, align 4, addrspace 1)
; VI-LABEL: name: test_store_global_v11s16_align4
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[DEF:%[0-9]+]]:_(<12 x s16>) = G_IMPLICIT_DEF
@@ -6096,16 +5401,13 @@ body: |
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; VI: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV79]](<2 x s16>)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C1]](s32)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; VI: G_STORE [[COPY1]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 16, align 16, addrspace 1)
+ ; VI: G_STORE [[BITCAST1]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 16, align 16, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C2]](s64)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 20, align 4, addrspace 1)
+ ; VI: G_STORE [[BITCAST2]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 20, align 4, addrspace 1)
; GFX9-LABEL: name: test_store_global_v11s16_align4
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[DEF:%[0-9]+]]:_(<12 x s16>) = G_IMPLICIT_DEF
@@ -6139,16 +5441,13 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV79]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C1]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: G_STORE [[COPY1]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 16, align 16, addrspace 1)
+ ; GFX9: G_STORE [[BITCAST1]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 16, align 16, addrspace 1)
; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; GFX9: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C2]](s64)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: G_STORE [[COPY2]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
+ ; GFX9: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
; GFX9: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; GFX9: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD]], [[C3]](s64)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX9: G_STORE [[COPY3]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 20, align 4, addrspace 1)
+ ; GFX9: G_STORE [[BITCAST2]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 20, align 4, addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(<11 x s16>) = G_IMPLICIT_DEF
G_STORE %1, %0 :: (store (<11 x s16>), align 16, addrspace 1)
@@ -6224,84 +5523,64 @@ body: |
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; SI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; SI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; SI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; SI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; SI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C3]](s64)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; SI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; SI: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; SI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C5]](s64)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; SI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; SI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; SI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI: [[PTR_ADD15:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C9]](s64)
; SI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
; SI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C1]](s32)
; SI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C2]](s32)
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[EXTRACT1]](s32)
- ; SI: G_STORE [[COPY18]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
+ ; SI: G_STORE [[EXTRACT1]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
; SI: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C3]](s64)
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; SI: G_STORE [[COPY19]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
+ ; SI: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
; SI: [[PTR_ADD17:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C4]](s64)
- ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; SI: G_STORE [[COPY20]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
+ ; SI: G_STORE [[LSHR13]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; SI: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C5]](s64)
- ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; SI: G_STORE [[COPY21]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
+ ; SI: G_STORE [[LSHR14]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
; CI-LABEL: name: test_store_global_s160_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s160) = COPY $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
@@ -6325,84 +5604,64 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; VI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; VI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; VI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; VI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; VI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; VI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; VI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; VI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; VI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; VI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; VI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; VI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; VI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C3]](s64)
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; VI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; VI: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; VI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; VI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C5]](s64)
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; VI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; VI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; VI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI: [[PTR_ADD15:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C9]](s64)
; VI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
; VI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C1]](s32)
; VI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C2]](s32)
- ; VI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[EXTRACT1]](s32)
- ; VI: G_STORE [[COPY18]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
+ ; VI: G_STORE [[EXTRACT1]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
; VI: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C3]](s64)
- ; VI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; VI: G_STORE [[COPY19]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
+ ; VI: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
; VI: [[PTR_ADD17:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C4]](s64)
- ; VI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; VI: G_STORE [[COPY20]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
+ ; VI: G_STORE [[LSHR13]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; VI: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C5]](s64)
- ; VI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; VI: G_STORE [[COPY21]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
+ ; VI: G_STORE [[LSHR14]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
; GFX9-LABEL: name: test_store_global_s160_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s160) = COPY $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
@@ -6434,44 +5693,34 @@ body: |
; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](<2 x s32>)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<2 x s32>)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[EXTRACT1]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
+ ; SI: G_STORE [[EXTRACT1]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
; CI-LABEL: name: test_store_global_s160_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s160) = COPY $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
@@ -6492,44 +5741,34 @@ body: |
; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](<2 x s32>)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; VI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<2 x s32>)
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT1]], [[C]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[EXTRACT1]](s32)
- ; VI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
+ ; VI: G_STORE [[EXTRACT1]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
; GFX9-LABEL: name: test_store_global_s160_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s160) = COPY $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
@@ -6715,130 +5954,98 @@ body: |
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; SI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C1]](s32)
; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C2]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV4]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; SI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; SI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; SI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; SI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C1]](s32)
; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C2]](s32)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; SI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV5]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C3]](s64)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; SI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; SI: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; SI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C5]](s64)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; SI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; SI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; SI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI: [[PTR_ADD15:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C9]](s64)
; SI: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<4 x s32>)
; SI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C]](s32)
; SI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C1]](s32)
; SI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C2]](s32)
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; SI: G_STORE [[COPY18]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
+ ; SI: G_STORE [[UV6]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
; SI: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C3]](s64)
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; SI: G_STORE [[COPY19]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
+ ; SI: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
; SI: [[PTR_ADD17:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C4]](s64)
- ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; SI: G_STORE [[COPY20]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
+ ; SI: G_STORE [[LSHR13]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; SI: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C5]](s64)
- ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; SI: G_STORE [[COPY21]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
+ ; SI: G_STORE [[LSHR14]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
; SI: [[PTR_ADD19:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C6]](s64)
; SI: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C]](s32)
; SI: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C1]](s32)
; SI: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C2]](s32)
- ; SI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; SI: G_STORE [[COPY22]](s32), [[PTR_ADD19]](p1) :: (store (s8) into unknown-address + 20, addrspace 1)
+ ; SI: G_STORE [[UV7]](s32), [[PTR_ADD19]](p1) :: (store (s8) into unknown-address + 20, addrspace 1)
; SI: [[PTR_ADD20:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C3]](s64)
- ; SI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; SI: G_STORE [[COPY23]](s32), [[PTR_ADD20]](p1) :: (store (s8) into unknown-address + 21, addrspace 1)
+ ; SI: G_STORE [[LSHR15]](s32), [[PTR_ADD20]](p1) :: (store (s8) into unknown-address + 21, addrspace 1)
; SI: [[PTR_ADD21:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C4]](s64)
- ; SI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; SI: G_STORE [[COPY24]](s32), [[PTR_ADD21]](p1) :: (store (s8) into unknown-address + 22, addrspace 1)
+ ; SI: G_STORE [[LSHR16]](s32), [[PTR_ADD21]](p1) :: (store (s8) into unknown-address + 22, addrspace 1)
; SI: [[PTR_ADD22:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C5]](s64)
- ; SI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; SI: G_STORE [[COPY25]](s32), [[PTR_ADD22]](p1) :: (store (s8) into unknown-address + 23, addrspace 1)
+ ; SI: G_STORE [[LSHR17]](s32), [[PTR_ADD22]](p1) :: (store (s8) into unknown-address + 23, addrspace 1)
; SI: [[PTR_ADD23:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C7]](s64)
; SI: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[UV8]], [[C]](s32)
; SI: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[UV8]], [[C1]](s32)
; SI: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[UV8]], [[C2]](s32)
- ; SI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[UV8]](s32)
- ; SI: G_STORE [[COPY26]](s32), [[PTR_ADD23]](p1) :: (store (s8) into unknown-address + 24, addrspace 1)
+ ; SI: G_STORE [[UV8]](s32), [[PTR_ADD23]](p1) :: (store (s8) into unknown-address + 24, addrspace 1)
; SI: [[PTR_ADD24:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C3]](s64)
- ; SI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; SI: G_STORE [[COPY27]](s32), [[PTR_ADD24]](p1) :: (store (s8) into unknown-address + 25, addrspace 1)
+ ; SI: G_STORE [[LSHR18]](s32), [[PTR_ADD24]](p1) :: (store (s8) into unknown-address + 25, addrspace 1)
; SI: [[PTR_ADD25:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C4]](s64)
- ; SI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; SI: G_STORE [[COPY28]](s32), [[PTR_ADD25]](p1) :: (store (s8) into unknown-address + 26, addrspace 1)
+ ; SI: G_STORE [[LSHR19]](s32), [[PTR_ADD25]](p1) :: (store (s8) into unknown-address + 26, addrspace 1)
; SI: [[PTR_ADD26:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C5]](s64)
- ; SI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; SI: G_STORE [[COPY29]](s32), [[PTR_ADD26]](p1) :: (store (s8) into unknown-address + 27, addrspace 1)
+ ; SI: G_STORE [[LSHR20]](s32), [[PTR_ADD26]](p1) :: (store (s8) into unknown-address + 27, addrspace 1)
; SI: [[PTR_ADD27:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C8]](s64)
; SI: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[UV9]], [[C]](s32)
; SI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[UV9]], [[C1]](s32)
; SI: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[UV9]], [[C2]](s32)
- ; SI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[UV9]](s32)
- ; SI: G_STORE [[COPY30]](s32), [[PTR_ADD27]](p1) :: (store (s8) into unknown-address + 28, addrspace 1)
+ ; SI: G_STORE [[UV9]](s32), [[PTR_ADD27]](p1) :: (store (s8) into unknown-address + 28, addrspace 1)
; SI: [[PTR_ADD28:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C3]](s64)
- ; SI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; SI: G_STORE [[COPY31]](s32), [[PTR_ADD28]](p1) :: (store (s8) into unknown-address + 29, addrspace 1)
+ ; SI: G_STORE [[LSHR21]](s32), [[PTR_ADD28]](p1) :: (store (s8) into unknown-address + 29, addrspace 1)
; SI: [[PTR_ADD29:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C4]](s64)
- ; SI: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; SI: G_STORE [[COPY32]](s32), [[PTR_ADD29]](p1) :: (store (s8) into unknown-address + 30, addrspace 1)
+ ; SI: G_STORE [[LSHR22]](s32), [[PTR_ADD29]](p1) :: (store (s8) into unknown-address + 30, addrspace 1)
; SI: [[PTR_ADD30:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C5]](s64)
- ; SI: [[COPY33:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; SI: G_STORE [[COPY33]](s32), [[PTR_ADD30]](p1) :: (store (s8) into unknown-address + 31, addrspace 1)
+ ; SI: G_STORE [[LSHR23]](s32), [[PTR_ADD30]](p1) :: (store (s8) into unknown-address + 31, addrspace 1)
; CI-LABEL: name: test_store_global_v8s32_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<8 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
@@ -6858,130 +6065,98 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; VI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; VI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; VI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
; VI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C1]](s32)
; VI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C2]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; VI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV4]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; VI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; VI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; VI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; VI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; VI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; VI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
; VI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C1]](s32)
; VI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C2]](s32)
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; VI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV5]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C3]](s64)
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; VI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; VI: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; VI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; VI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C5]](s64)
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; VI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; VI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; VI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI: [[PTR_ADD15:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C9]](s64)
; VI: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<4 x s32>)
; VI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C]](s32)
; VI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C1]](s32)
; VI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C2]](s32)
- ; VI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; VI: G_STORE [[COPY18]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
+ ; VI: G_STORE [[UV6]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
; VI: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C3]](s64)
- ; VI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; VI: G_STORE [[COPY19]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
+ ; VI: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
; VI: [[PTR_ADD17:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C4]](s64)
- ; VI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; VI: G_STORE [[COPY20]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
+ ; VI: G_STORE [[LSHR13]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; VI: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C5]](s64)
- ; VI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; VI: G_STORE [[COPY21]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
+ ; VI: G_STORE [[LSHR14]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
; VI: [[PTR_ADD19:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C6]](s64)
; VI: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C]](s32)
; VI: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C1]](s32)
; VI: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C2]](s32)
- ; VI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; VI: G_STORE [[COPY22]](s32), [[PTR_ADD19]](p1) :: (store (s8) into unknown-address + 20, addrspace 1)
+ ; VI: G_STORE [[UV7]](s32), [[PTR_ADD19]](p1) :: (store (s8) into unknown-address + 20, addrspace 1)
; VI: [[PTR_ADD20:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C3]](s64)
- ; VI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; VI: G_STORE [[COPY23]](s32), [[PTR_ADD20]](p1) :: (store (s8) into unknown-address + 21, addrspace 1)
+ ; VI: G_STORE [[LSHR15]](s32), [[PTR_ADD20]](p1) :: (store (s8) into unknown-address + 21, addrspace 1)
; VI: [[PTR_ADD21:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C4]](s64)
- ; VI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; VI: G_STORE [[COPY24]](s32), [[PTR_ADD21]](p1) :: (store (s8) into unknown-address + 22, addrspace 1)
+ ; VI: G_STORE [[LSHR16]](s32), [[PTR_ADD21]](p1) :: (store (s8) into unknown-address + 22, addrspace 1)
; VI: [[PTR_ADD22:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C5]](s64)
- ; VI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; VI: G_STORE [[COPY25]](s32), [[PTR_ADD22]](p1) :: (store (s8) into unknown-address + 23, addrspace 1)
+ ; VI: G_STORE [[LSHR17]](s32), [[PTR_ADD22]](p1) :: (store (s8) into unknown-address + 23, addrspace 1)
; VI: [[PTR_ADD23:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C7]](s64)
; VI: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[UV8]], [[C]](s32)
; VI: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[UV8]], [[C1]](s32)
; VI: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[UV8]], [[C2]](s32)
- ; VI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[UV8]](s32)
- ; VI: G_STORE [[COPY26]](s32), [[PTR_ADD23]](p1) :: (store (s8) into unknown-address + 24, addrspace 1)
+ ; VI: G_STORE [[UV8]](s32), [[PTR_ADD23]](p1) :: (store (s8) into unknown-address + 24, addrspace 1)
; VI: [[PTR_ADD24:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C3]](s64)
- ; VI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; VI: G_STORE [[COPY27]](s32), [[PTR_ADD24]](p1) :: (store (s8) into unknown-address + 25, addrspace 1)
+ ; VI: G_STORE [[LSHR18]](s32), [[PTR_ADD24]](p1) :: (store (s8) into unknown-address + 25, addrspace 1)
; VI: [[PTR_ADD25:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C4]](s64)
- ; VI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; VI: G_STORE [[COPY28]](s32), [[PTR_ADD25]](p1) :: (store (s8) into unknown-address + 26, addrspace 1)
+ ; VI: G_STORE [[LSHR19]](s32), [[PTR_ADD25]](p1) :: (store (s8) into unknown-address + 26, addrspace 1)
; VI: [[PTR_ADD26:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C5]](s64)
- ; VI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; VI: G_STORE [[COPY29]](s32), [[PTR_ADD26]](p1) :: (store (s8) into unknown-address + 27, addrspace 1)
+ ; VI: G_STORE [[LSHR20]](s32), [[PTR_ADD26]](p1) :: (store (s8) into unknown-address + 27, addrspace 1)
; VI: [[PTR_ADD27:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C8]](s64)
; VI: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[UV9]], [[C]](s32)
; VI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[UV9]], [[C1]](s32)
; VI: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[UV9]], [[C2]](s32)
- ; VI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[UV9]](s32)
- ; VI: G_STORE [[COPY30]](s32), [[PTR_ADD27]](p1) :: (store (s8) into unknown-address + 28, addrspace 1)
+ ; VI: G_STORE [[UV9]](s32), [[PTR_ADD27]](p1) :: (store (s8) into unknown-address + 28, addrspace 1)
; VI: [[PTR_ADD28:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C3]](s64)
- ; VI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; VI: G_STORE [[COPY31]](s32), [[PTR_ADD28]](p1) :: (store (s8) into unknown-address + 29, addrspace 1)
+ ; VI: G_STORE [[LSHR21]](s32), [[PTR_ADD28]](p1) :: (store (s8) into unknown-address + 29, addrspace 1)
; VI: [[PTR_ADD29:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C4]](s64)
- ; VI: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; VI: G_STORE [[COPY32]](s32), [[PTR_ADD29]](p1) :: (store (s8) into unknown-address + 30, addrspace 1)
+ ; VI: G_STORE [[LSHR22]](s32), [[PTR_ADD29]](p1) :: (store (s8) into unknown-address + 30, addrspace 1)
; VI: [[PTR_ADD30:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C5]](s64)
- ; VI: [[COPY33:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; VI: G_STORE [[COPY33]](s32), [[PTR_ADD30]](p1) :: (store (s8) into unknown-address + 31, addrspace 1)
+ ; VI: G_STORE [[LSHR23]](s32), [[PTR_ADD30]](p1) :: (store (s8) into unknown-address + 31, addrspace 1)
; GFX9-LABEL: name: test_store_global_v8s32_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<8 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
@@ -7009,68 +6184,52 @@ body: |
; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](<2 x s32>)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[UV4]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV5]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; SI: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](<2 x s32>)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV7]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; SI: [[UV8:%[0-9]+]]:_(<2 x s32>), [[UV9:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[UV1]](<4 x s32>)
; SI: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV8]](<2 x s32>)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV10]], [[C]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV10]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
+ ; SI: G_STORE [[UV10]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
; SI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV11]], [[C]](s32)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV11]](s32)
- ; SI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s16) into unknown-address + 20, addrspace 1)
+ ; SI: G_STORE [[UV11]](s32), [[PTR_ADD9]](p1) :: (store (s16) into unknown-address + 20, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD9]], [[C1]](s64)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s16) into unknown-address + 22, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD10]](p1) :: (store (s16) into unknown-address + 22, addrspace 1)
; SI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
; SI: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV9]](<2 x s32>)
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV12]], [[C]](s32)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV12]](s32)
- ; SI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s16) into unknown-address + 24, addrspace 1)
+ ; SI: G_STORE [[UV12]](s32), [[PTR_ADD11]](p1) :: (store (s16) into unknown-address + 24, addrspace 1)
; SI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C1]](s64)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s16) into unknown-address + 26, addrspace 1)
+ ; SI: G_STORE [[LSHR6]](s32), [[PTR_ADD12]](p1) :: (store (s16) into unknown-address + 26, addrspace 1)
; SI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV13]], [[C]](s32)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[UV13]](s32)
- ; SI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s16) into unknown-address + 28, addrspace 1)
+ ; SI: G_STORE [[UV13]](s32), [[PTR_ADD13]](p1) :: (store (s16) into unknown-address + 28, addrspace 1)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD13]], [[C1]](s64)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s16) into unknown-address + 30, addrspace 1)
+ ; SI: G_STORE [[LSHR7]](s32), [[PTR_ADD14]](p1) :: (store (s16) into unknown-address + 30, addrspace 1)
; CI-LABEL: name: test_store_global_v8s32_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<8 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
@@ -7087,68 +6246,52 @@ body: |
; VI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](<2 x s32>)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[UV4]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV5]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; VI: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](<2 x s32>)
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C]](s32)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV7]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; VI: [[UV8:%[0-9]+]]:_(<2 x s32>), [[UV9:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[UV1]](<4 x s32>)
; VI: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV8]](<2 x s32>)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV10]], [[C]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV10]](s32)
- ; VI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
+ ; VI: G_STORE [[UV10]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
; VI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV11]], [[C]](s32)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV11]](s32)
- ; VI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s16) into unknown-address + 20, addrspace 1)
+ ; VI: G_STORE [[UV11]](s32), [[PTR_ADD9]](p1) :: (store (s16) into unknown-address + 20, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD9]], [[C1]](s64)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s16) into unknown-address + 22, addrspace 1)
+ ; VI: G_STORE [[LSHR5]](s32), [[PTR_ADD10]](p1) :: (store (s16) into unknown-address + 22, addrspace 1)
; VI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
; VI: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV9]](<2 x s32>)
; VI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV12]], [[C]](s32)
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV12]](s32)
- ; VI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s16) into unknown-address + 24, addrspace 1)
+ ; VI: G_STORE [[UV12]](s32), [[PTR_ADD11]](p1) :: (store (s16) into unknown-address + 24, addrspace 1)
; VI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C1]](s64)
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s16) into unknown-address + 26, addrspace 1)
+ ; VI: G_STORE [[LSHR6]](s32), [[PTR_ADD12]](p1) :: (store (s16) into unknown-address + 26, addrspace 1)
; VI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; VI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV13]], [[C]](s32)
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[UV13]](s32)
- ; VI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s16) into unknown-address + 28, addrspace 1)
+ ; VI: G_STORE [[UV13]](s32), [[PTR_ADD13]](p1) :: (store (s16) into unknown-address + 28, addrspace 1)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD13]], [[C1]](s64)
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s16) into unknown-address + 30, addrspace 1)
+ ; VI: G_STORE [[LSHR7]](s32), [[PTR_ADD14]](p1) :: (store (s16) into unknown-address + 30, addrspace 1)
; GFX9-LABEL: name: test_store_global_v8s32_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<8 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
@@ -7356,130 +6499,98 @@ body: |
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; SI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C1]](s32)
; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C2]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV4]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; SI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; SI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; SI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; SI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C1]](s32)
; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C2]](s32)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; SI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV5]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C3]](s64)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; SI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; SI: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; SI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C5]](s64)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; SI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; SI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; SI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI: [[PTR_ADD15:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C9]](s64)
; SI: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<4 x s32>)
; SI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C]](s32)
; SI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C1]](s32)
; SI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C2]](s32)
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; SI: G_STORE [[COPY18]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
+ ; SI: G_STORE [[UV6]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
; SI: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C3]](s64)
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; SI: G_STORE [[COPY19]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
+ ; SI: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
; SI: [[PTR_ADD17:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C4]](s64)
- ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; SI: G_STORE [[COPY20]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
+ ; SI: G_STORE [[LSHR13]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; SI: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C5]](s64)
- ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; SI: G_STORE [[COPY21]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
+ ; SI: G_STORE [[LSHR14]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
; SI: [[PTR_ADD19:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C6]](s64)
; SI: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C]](s32)
; SI: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C1]](s32)
; SI: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C2]](s32)
- ; SI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; SI: G_STORE [[COPY22]](s32), [[PTR_ADD19]](p1) :: (store (s8) into unknown-address + 20, addrspace 1)
+ ; SI: G_STORE [[UV7]](s32), [[PTR_ADD19]](p1) :: (store (s8) into unknown-address + 20, addrspace 1)
; SI: [[PTR_ADD20:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C3]](s64)
- ; SI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; SI: G_STORE [[COPY23]](s32), [[PTR_ADD20]](p1) :: (store (s8) into unknown-address + 21, addrspace 1)
+ ; SI: G_STORE [[LSHR15]](s32), [[PTR_ADD20]](p1) :: (store (s8) into unknown-address + 21, addrspace 1)
; SI: [[PTR_ADD21:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C4]](s64)
- ; SI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; SI: G_STORE [[COPY24]](s32), [[PTR_ADD21]](p1) :: (store (s8) into unknown-address + 22, addrspace 1)
+ ; SI: G_STORE [[LSHR16]](s32), [[PTR_ADD21]](p1) :: (store (s8) into unknown-address + 22, addrspace 1)
; SI: [[PTR_ADD22:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C5]](s64)
- ; SI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; SI: G_STORE [[COPY25]](s32), [[PTR_ADD22]](p1) :: (store (s8) into unknown-address + 23, addrspace 1)
+ ; SI: G_STORE [[LSHR17]](s32), [[PTR_ADD22]](p1) :: (store (s8) into unknown-address + 23, addrspace 1)
; SI: [[PTR_ADD23:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C7]](s64)
; SI: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[UV8]], [[C]](s32)
; SI: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[UV8]], [[C1]](s32)
; SI: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[UV8]], [[C2]](s32)
- ; SI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[UV8]](s32)
- ; SI: G_STORE [[COPY26]](s32), [[PTR_ADD23]](p1) :: (store (s8) into unknown-address + 24, addrspace 1)
+ ; SI: G_STORE [[UV8]](s32), [[PTR_ADD23]](p1) :: (store (s8) into unknown-address + 24, addrspace 1)
; SI: [[PTR_ADD24:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C3]](s64)
- ; SI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; SI: G_STORE [[COPY27]](s32), [[PTR_ADD24]](p1) :: (store (s8) into unknown-address + 25, addrspace 1)
+ ; SI: G_STORE [[LSHR18]](s32), [[PTR_ADD24]](p1) :: (store (s8) into unknown-address + 25, addrspace 1)
; SI: [[PTR_ADD25:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C4]](s64)
- ; SI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; SI: G_STORE [[COPY28]](s32), [[PTR_ADD25]](p1) :: (store (s8) into unknown-address + 26, addrspace 1)
+ ; SI: G_STORE [[LSHR19]](s32), [[PTR_ADD25]](p1) :: (store (s8) into unknown-address + 26, addrspace 1)
; SI: [[PTR_ADD26:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C5]](s64)
- ; SI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; SI: G_STORE [[COPY29]](s32), [[PTR_ADD26]](p1) :: (store (s8) into unknown-address + 27, addrspace 1)
+ ; SI: G_STORE [[LSHR20]](s32), [[PTR_ADD26]](p1) :: (store (s8) into unknown-address + 27, addrspace 1)
; SI: [[PTR_ADD27:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C8]](s64)
; SI: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[UV9]], [[C]](s32)
; SI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[UV9]], [[C1]](s32)
; SI: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[UV9]], [[C2]](s32)
- ; SI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[UV9]](s32)
- ; SI: G_STORE [[COPY30]](s32), [[PTR_ADD27]](p1) :: (store (s8) into unknown-address + 28, addrspace 1)
+ ; SI: G_STORE [[UV9]](s32), [[PTR_ADD27]](p1) :: (store (s8) into unknown-address + 28, addrspace 1)
; SI: [[PTR_ADD28:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C3]](s64)
- ; SI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; SI: G_STORE [[COPY31]](s32), [[PTR_ADD28]](p1) :: (store (s8) into unknown-address + 29, addrspace 1)
+ ; SI: G_STORE [[LSHR21]](s32), [[PTR_ADD28]](p1) :: (store (s8) into unknown-address + 29, addrspace 1)
; SI: [[PTR_ADD29:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C4]](s64)
- ; SI: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; SI: G_STORE [[COPY32]](s32), [[PTR_ADD29]](p1) :: (store (s8) into unknown-address + 30, addrspace 1)
+ ; SI: G_STORE [[LSHR22]](s32), [[PTR_ADD29]](p1) :: (store (s8) into unknown-address + 30, addrspace 1)
; SI: [[PTR_ADD30:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C5]](s64)
- ; SI: [[COPY33:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; SI: G_STORE [[COPY33]](s32), [[PTR_ADD30]](p1) :: (store (s8) into unknown-address + 31, addrspace 1)
+ ; SI: G_STORE [[LSHR23]](s32), [[PTR_ADD30]](p1) :: (store (s8) into unknown-address + 31, addrspace 1)
; CI-LABEL: name: test_store_global_s256_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s256) = COPY $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
@@ -7501,130 +6612,98 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; VI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; VI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; VI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
; VI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C1]](s32)
; VI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C2]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; VI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV4]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; VI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; VI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; VI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; VI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; VI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; VI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
; VI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C1]](s32)
; VI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C2]](s32)
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; VI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV5]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C3]](s64)
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; VI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; VI: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; VI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; VI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C5]](s64)
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; VI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; VI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; VI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI: [[PTR_ADD15:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C9]](s64)
; VI: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<4 x s32>)
; VI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C]](s32)
; VI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C1]](s32)
; VI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C2]](s32)
- ; VI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; VI: G_STORE [[COPY18]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
+ ; VI: G_STORE [[UV6]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
; VI: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C3]](s64)
- ; VI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; VI: G_STORE [[COPY19]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
+ ; VI: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
; VI: [[PTR_ADD17:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C4]](s64)
- ; VI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; VI: G_STORE [[COPY20]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
+ ; VI: G_STORE [[LSHR13]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; VI: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C5]](s64)
- ; VI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; VI: G_STORE [[COPY21]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
+ ; VI: G_STORE [[LSHR14]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
; VI: [[PTR_ADD19:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C6]](s64)
; VI: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C]](s32)
; VI: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C1]](s32)
; VI: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C2]](s32)
- ; VI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; VI: G_STORE [[COPY22]](s32), [[PTR_ADD19]](p1) :: (store (s8) into unknown-address + 20, addrspace 1)
+ ; VI: G_STORE [[UV7]](s32), [[PTR_ADD19]](p1) :: (store (s8) into unknown-address + 20, addrspace 1)
; VI: [[PTR_ADD20:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C3]](s64)
- ; VI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; VI: G_STORE [[COPY23]](s32), [[PTR_ADD20]](p1) :: (store (s8) into unknown-address + 21, addrspace 1)
+ ; VI: G_STORE [[LSHR15]](s32), [[PTR_ADD20]](p1) :: (store (s8) into unknown-address + 21, addrspace 1)
; VI: [[PTR_ADD21:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C4]](s64)
- ; VI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; VI: G_STORE [[COPY24]](s32), [[PTR_ADD21]](p1) :: (store (s8) into unknown-address + 22, addrspace 1)
+ ; VI: G_STORE [[LSHR16]](s32), [[PTR_ADD21]](p1) :: (store (s8) into unknown-address + 22, addrspace 1)
; VI: [[PTR_ADD22:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C5]](s64)
- ; VI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; VI: G_STORE [[COPY25]](s32), [[PTR_ADD22]](p1) :: (store (s8) into unknown-address + 23, addrspace 1)
+ ; VI: G_STORE [[LSHR17]](s32), [[PTR_ADD22]](p1) :: (store (s8) into unknown-address + 23, addrspace 1)
; VI: [[PTR_ADD23:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C7]](s64)
; VI: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[UV8]], [[C]](s32)
; VI: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[UV8]], [[C1]](s32)
; VI: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[UV8]], [[C2]](s32)
- ; VI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[UV8]](s32)
- ; VI: G_STORE [[COPY26]](s32), [[PTR_ADD23]](p1) :: (store (s8) into unknown-address + 24, addrspace 1)
+ ; VI: G_STORE [[UV8]](s32), [[PTR_ADD23]](p1) :: (store (s8) into unknown-address + 24, addrspace 1)
; VI: [[PTR_ADD24:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C3]](s64)
- ; VI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; VI: G_STORE [[COPY27]](s32), [[PTR_ADD24]](p1) :: (store (s8) into unknown-address + 25, addrspace 1)
+ ; VI: G_STORE [[LSHR18]](s32), [[PTR_ADD24]](p1) :: (store (s8) into unknown-address + 25, addrspace 1)
; VI: [[PTR_ADD25:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C4]](s64)
- ; VI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; VI: G_STORE [[COPY28]](s32), [[PTR_ADD25]](p1) :: (store (s8) into unknown-address + 26, addrspace 1)
+ ; VI: G_STORE [[LSHR19]](s32), [[PTR_ADD25]](p1) :: (store (s8) into unknown-address + 26, addrspace 1)
; VI: [[PTR_ADD26:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C5]](s64)
- ; VI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; VI: G_STORE [[COPY29]](s32), [[PTR_ADD26]](p1) :: (store (s8) into unknown-address + 27, addrspace 1)
+ ; VI: G_STORE [[LSHR20]](s32), [[PTR_ADD26]](p1) :: (store (s8) into unknown-address + 27, addrspace 1)
; VI: [[PTR_ADD27:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C8]](s64)
; VI: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[UV9]], [[C]](s32)
; VI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[UV9]], [[C1]](s32)
; VI: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[UV9]], [[C2]](s32)
- ; VI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[UV9]](s32)
- ; VI: G_STORE [[COPY30]](s32), [[PTR_ADD27]](p1) :: (store (s8) into unknown-address + 28, addrspace 1)
+ ; VI: G_STORE [[UV9]](s32), [[PTR_ADD27]](p1) :: (store (s8) into unknown-address + 28, addrspace 1)
; VI: [[PTR_ADD28:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C3]](s64)
- ; VI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; VI: G_STORE [[COPY31]](s32), [[PTR_ADD28]](p1) :: (store (s8) into unknown-address + 29, addrspace 1)
+ ; VI: G_STORE [[LSHR21]](s32), [[PTR_ADD28]](p1) :: (store (s8) into unknown-address + 29, addrspace 1)
; VI: [[PTR_ADD29:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C4]](s64)
- ; VI: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; VI: G_STORE [[COPY32]](s32), [[PTR_ADD29]](p1) :: (store (s8) into unknown-address + 30, addrspace 1)
+ ; VI: G_STORE [[LSHR22]](s32), [[PTR_ADD29]](p1) :: (store (s8) into unknown-address + 30, addrspace 1)
; VI: [[PTR_ADD30:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C5]](s64)
- ; VI: [[COPY33:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; VI: G_STORE [[COPY33]](s32), [[PTR_ADD30]](p1) :: (store (s8) into unknown-address + 31, addrspace 1)
+ ; VI: G_STORE [[LSHR23]](s32), [[PTR_ADD30]](p1) :: (store (s8) into unknown-address + 31, addrspace 1)
; GFX9-LABEL: name: test_store_global_s256_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s256) = COPY $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
@@ -7654,68 +6733,52 @@ body: |
; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](<2 x s32>)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[UV4]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV5]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; SI: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](<2 x s32>)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV7]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; SI: [[UV8:%[0-9]+]]:_(<2 x s32>), [[UV9:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[UV1]](<4 x s32>)
; SI: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV8]](<2 x s32>)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV10]], [[C]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV10]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
+ ; SI: G_STORE [[UV10]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
; SI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV11]], [[C]](s32)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV11]](s32)
- ; SI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s16) into unknown-address + 20, addrspace 1)
+ ; SI: G_STORE [[UV11]](s32), [[PTR_ADD9]](p1) :: (store (s16) into unknown-address + 20, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD9]], [[C1]](s64)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s16) into unknown-address + 22, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD10]](p1) :: (store (s16) into unknown-address + 22, addrspace 1)
; SI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
; SI: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV9]](<2 x s32>)
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV12]], [[C]](s32)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV12]](s32)
- ; SI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s16) into unknown-address + 24, addrspace 1)
+ ; SI: G_STORE [[UV12]](s32), [[PTR_ADD11]](p1) :: (store (s16) into unknown-address + 24, addrspace 1)
; SI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C1]](s64)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s16) into unknown-address + 26, addrspace 1)
+ ; SI: G_STORE [[LSHR6]](s32), [[PTR_ADD12]](p1) :: (store (s16) into unknown-address + 26, addrspace 1)
; SI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV13]], [[C]](s32)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[UV13]](s32)
- ; SI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s16) into unknown-address + 28, addrspace 1)
+ ; SI: G_STORE [[UV13]](s32), [[PTR_ADD13]](p1) :: (store (s16) into unknown-address + 28, addrspace 1)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD13]], [[C1]](s64)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s16) into unknown-address + 30, addrspace 1)
+ ; SI: G_STORE [[LSHR7]](s32), [[PTR_ADD14]](p1) :: (store (s16) into unknown-address + 30, addrspace 1)
; CI-LABEL: name: test_store_global_s256_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(s256) = COPY $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
@@ -7734,68 +6797,52 @@ body: |
; VI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV2]](<2 x s32>)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[UV4]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV5]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; VI: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV3]](<2 x s32>)
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV6]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C]](s32)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV7]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; VI: [[UV8:%[0-9]+]]:_(<2 x s32>), [[UV9:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[UV1]](<4 x s32>)
; VI: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV8]](<2 x s32>)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV10]], [[C]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV10]](s32)
- ; VI: G_STORE [[COPY10]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
+ ; VI: G_STORE [[UV10]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY11]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
; VI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV11]], [[C]](s32)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV11]](s32)
- ; VI: G_STORE [[COPY12]](s32), [[PTR_ADD9]](p1) :: (store (s16) into unknown-address + 20, addrspace 1)
+ ; VI: G_STORE [[UV11]](s32), [[PTR_ADD9]](p1) :: (store (s16) into unknown-address + 20, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD9]], [[C1]](s64)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: G_STORE [[COPY13]](s32), [[PTR_ADD10]](p1) :: (store (s16) into unknown-address + 22, addrspace 1)
+ ; VI: G_STORE [[LSHR5]](s32), [[PTR_ADD10]](p1) :: (store (s16) into unknown-address + 22, addrspace 1)
; VI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
; VI: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV9]](<2 x s32>)
; VI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV12]], [[C]](s32)
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV12]](s32)
- ; VI: G_STORE [[COPY14]](s32), [[PTR_ADD11]](p1) :: (store (s16) into unknown-address + 24, addrspace 1)
+ ; VI: G_STORE [[UV12]](s32), [[PTR_ADD11]](p1) :: (store (s16) into unknown-address + 24, addrspace 1)
; VI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C1]](s64)
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: G_STORE [[COPY15]](s32), [[PTR_ADD12]](p1) :: (store (s16) into unknown-address + 26, addrspace 1)
+ ; VI: G_STORE [[LSHR6]](s32), [[PTR_ADD12]](p1) :: (store (s16) into unknown-address + 26, addrspace 1)
; VI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; VI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV13]], [[C]](s32)
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[UV13]](s32)
- ; VI: G_STORE [[COPY16]](s32), [[PTR_ADD13]](p1) :: (store (s16) into unknown-address + 28, addrspace 1)
+ ; VI: G_STORE [[UV13]](s32), [[PTR_ADD13]](p1) :: (store (s16) into unknown-address + 28, addrspace 1)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD13]], [[C1]](s64)
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: G_STORE [[COPY17]](s32), [[PTR_ADD14]](p1) :: (store (s16) into unknown-address + 30, addrspace 1)
+ ; VI: G_STORE [[LSHR7]](s32), [[PTR_ADD14]](p1) :: (store (s16) into unknown-address + 30, addrspace 1)
; GFX9-LABEL: name: test_store_global_s256_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s256) = COPY $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
@@ -8063,146 +7110,110 @@ body: |
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; SI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY12]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: G_STORE [[COPY13]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; SI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; SI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: G_STORE [[COPY14]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: G_STORE [[COPY15]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; SI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; SI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; SI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; SI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; SI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; SI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY16]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C3]](s64)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; SI: G_STORE [[COPY17]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; SI: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; SI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; SI: G_STORE [[COPY18]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C5]](s64)
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; SI: G_STORE [[COPY19]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; SI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; SI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI: [[PTR_ADD15:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C9]](s64)
; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[EXTRACT1]](<4 x s32>)
; SI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
; SI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C1]](s32)
; SI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C2]](s32)
- ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; SI: G_STORE [[COPY20]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
+ ; SI: G_STORE [[UV4]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
; SI: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C3]](s64)
- ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; SI: G_STORE [[COPY21]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
+ ; SI: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
; SI: [[PTR_ADD17:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C4]](s64)
- ; SI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; SI: G_STORE [[COPY22]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
+ ; SI: G_STORE [[LSHR13]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; SI: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C5]](s64)
- ; SI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; SI: G_STORE [[COPY23]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
+ ; SI: G_STORE [[LSHR14]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
; SI: [[PTR_ADD19:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C6]](s64)
; SI: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
; SI: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C1]](s32)
; SI: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C2]](s32)
- ; SI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; SI: G_STORE [[COPY24]](s32), [[PTR_ADD19]](p1) :: (store (s8) into unknown-address + 20, addrspace 1)
+ ; SI: G_STORE [[UV5]](s32), [[PTR_ADD19]](p1) :: (store (s8) into unknown-address + 20, addrspace 1)
; SI: [[PTR_ADD20:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C3]](s64)
- ; SI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; SI: G_STORE [[COPY25]](s32), [[PTR_ADD20]](p1) :: (store (s8) into unknown-address + 21, addrspace 1)
+ ; SI: G_STORE [[LSHR15]](s32), [[PTR_ADD20]](p1) :: (store (s8) into unknown-address + 21, addrspace 1)
; SI: [[PTR_ADD21:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C4]](s64)
- ; SI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; SI: G_STORE [[COPY26]](s32), [[PTR_ADD21]](p1) :: (store (s8) into unknown-address + 22, addrspace 1)
+ ; SI: G_STORE [[LSHR16]](s32), [[PTR_ADD21]](p1) :: (store (s8) into unknown-address + 22, addrspace 1)
; SI: [[PTR_ADD22:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C5]](s64)
- ; SI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; SI: G_STORE [[COPY27]](s32), [[PTR_ADD22]](p1) :: (store (s8) into unknown-address + 23, addrspace 1)
+ ; SI: G_STORE [[LSHR17]](s32), [[PTR_ADD22]](p1) :: (store (s8) into unknown-address + 23, addrspace 1)
; SI: [[PTR_ADD23:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C7]](s64)
; SI: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C]](s32)
; SI: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C1]](s32)
; SI: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C2]](s32)
- ; SI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; SI: G_STORE [[COPY28]](s32), [[PTR_ADD23]](p1) :: (store (s8) into unknown-address + 24, addrspace 1)
+ ; SI: G_STORE [[UV6]](s32), [[PTR_ADD23]](p1) :: (store (s8) into unknown-address + 24, addrspace 1)
; SI: [[PTR_ADD24:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C3]](s64)
- ; SI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; SI: G_STORE [[COPY29]](s32), [[PTR_ADD24]](p1) :: (store (s8) into unknown-address + 25, addrspace 1)
+ ; SI: G_STORE [[LSHR18]](s32), [[PTR_ADD24]](p1) :: (store (s8) into unknown-address + 25, addrspace 1)
; SI: [[PTR_ADD25:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C4]](s64)
- ; SI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; SI: G_STORE [[COPY30]](s32), [[PTR_ADD25]](p1) :: (store (s8) into unknown-address + 26, addrspace 1)
+ ; SI: G_STORE [[LSHR19]](s32), [[PTR_ADD25]](p1) :: (store (s8) into unknown-address + 26, addrspace 1)
; SI: [[PTR_ADD26:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C5]](s64)
- ; SI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; SI: G_STORE [[COPY31]](s32), [[PTR_ADD26]](p1) :: (store (s8) into unknown-address + 27, addrspace 1)
+ ; SI: G_STORE [[LSHR20]](s32), [[PTR_ADD26]](p1) :: (store (s8) into unknown-address + 27, addrspace 1)
; SI: [[PTR_ADD27:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C8]](s64)
; SI: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C]](s32)
; SI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C1]](s32)
; SI: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C2]](s32)
- ; SI: [[COPY32:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; SI: G_STORE [[COPY32]](s32), [[PTR_ADD27]](p1) :: (store (s8) into unknown-address + 28, addrspace 1)
+ ; SI: G_STORE [[UV7]](s32), [[PTR_ADD27]](p1) :: (store (s8) into unknown-address + 28, addrspace 1)
; SI: [[PTR_ADD28:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C3]](s64)
- ; SI: [[COPY33:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; SI: G_STORE [[COPY33]](s32), [[PTR_ADD28]](p1) :: (store (s8) into unknown-address + 29, addrspace 1)
+ ; SI: G_STORE [[LSHR21]](s32), [[PTR_ADD28]](p1) :: (store (s8) into unknown-address + 29, addrspace 1)
; SI: [[PTR_ADD29:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C4]](s64)
- ; SI: [[COPY34:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; SI: G_STORE [[COPY34]](s32), [[PTR_ADD29]](p1) :: (store (s8) into unknown-address + 30, addrspace 1)
+ ; SI: G_STORE [[LSHR22]](s32), [[PTR_ADD29]](p1) :: (store (s8) into unknown-address + 30, addrspace 1)
; SI: [[PTR_ADD30:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C5]](s64)
- ; SI: [[COPY35:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; SI: G_STORE [[COPY35]](s32), [[PTR_ADD30]](p1) :: (store (s8) into unknown-address + 31, addrspace 1)
+ ; SI: G_STORE [[LSHR23]](s32), [[PTR_ADD30]](p1) :: (store (s8) into unknown-address + 31, addrspace 1)
; SI: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; SI: [[PTR_ADD31:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C10]](s64)
; SI: [[LSHR24:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT2]], [[C]](s32)
; SI: [[LSHR25:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT2]], [[C1]](s32)
; SI: [[LSHR26:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT2]], [[C2]](s32)
- ; SI: [[COPY36:%[0-9]+]]:_(s32) = COPY [[EXTRACT2]](s32)
- ; SI: G_STORE [[COPY36]](s32), [[PTR_ADD31]](p1) :: (store (s8) into unknown-address + 32, addrspace 1)
+ ; SI: G_STORE [[EXTRACT2]](s32), [[PTR_ADD31]](p1) :: (store (s8) into unknown-address + 32, addrspace 1)
; SI: [[PTR_ADD32:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD31]], [[C3]](s64)
- ; SI: [[COPY37:%[0-9]+]]:_(s32) = COPY [[LSHR24]](s32)
- ; SI: G_STORE [[COPY37]](s32), [[PTR_ADD32]](p1) :: (store (s8) into unknown-address + 33, addrspace 1)
+ ; SI: G_STORE [[LSHR24]](s32), [[PTR_ADD32]](p1) :: (store (s8) into unknown-address + 33, addrspace 1)
; SI: [[PTR_ADD33:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD31]], [[C4]](s64)
- ; SI: [[COPY38:%[0-9]+]]:_(s32) = COPY [[LSHR25]](s32)
- ; SI: G_STORE [[COPY38]](s32), [[PTR_ADD33]](p1) :: (store (s8) into unknown-address + 34, addrspace 1)
+ ; SI: G_STORE [[LSHR25]](s32), [[PTR_ADD33]](p1) :: (store (s8) into unknown-address + 34, addrspace 1)
; SI: [[PTR_ADD34:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD31]], [[C5]](s64)
- ; SI: [[COPY39:%[0-9]+]]:_(s32) = COPY [[LSHR26]](s32)
- ; SI: G_STORE [[COPY39]](s32), [[PTR_ADD34]](p1) :: (store (s8) into unknown-address + 35, addrspace 1)
+ ; SI: G_STORE [[LSHR26]](s32), [[PTR_ADD34]](p1) :: (store (s8) into unknown-address + 35, addrspace 1)
; CI-LABEL: name: test_store_global_v9s32_align1
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
@@ -8235,146 +7246,110 @@ body: |
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C6]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD3]](p1) :: (store (s8) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C3]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD4]](p1) :: (store (s8) into unknown-address + 5, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C4]](s64)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY10]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD5]](p1) :: (store (s8) into unknown-address + 6, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C5]](s64)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: G_STORE [[COPY11]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
+ ; VI: G_STORE [[LSHR5]](s32), [[PTR_ADD6]](p1) :: (store (s8) into unknown-address + 7, addrspace 1)
; VI: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C7]](s64)
; VI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; VI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; VI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY12]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[PTR_ADD7]](p1) :: (store (s8) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: G_STORE [[COPY13]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
+ ; VI: G_STORE [[LSHR6]](s32), [[PTR_ADD8]](p1) :: (store (s8) into unknown-address + 9, addrspace 1)
; VI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C4]](s64)
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: G_STORE [[COPY14]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR7]](s32), [[PTR_ADD9]](p1) :: (store (s8) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C5]](s64)
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; VI: G_STORE [[COPY15]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
+ ; VI: G_STORE [[LSHR8]](s32), [[PTR_ADD10]](p1) :: (store (s8) into unknown-address + 11, addrspace 1)
; VI: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; VI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C8]](s64)
; VI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
; VI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C1]](s32)
; VI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY16]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD11]](p1) :: (store (s8) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C3]](s64)
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; VI: G_STORE [[COPY17]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
+ ; VI: G_STORE [[LSHR9]](s32), [[PTR_ADD12]](p1) :: (store (s8) into unknown-address + 13, addrspace 1)
; VI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C4]](s64)
- ; VI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; VI: G_STORE [[COPY18]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR10]](s32), [[PTR_ADD13]](p1) :: (store (s8) into unknown-address + 14, addrspace 1)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C5]](s64)
- ; VI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; VI: G_STORE [[COPY19]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
+ ; VI: G_STORE [[LSHR11]](s32), [[PTR_ADD14]](p1) :: (store (s8) into unknown-address + 15, addrspace 1)
; VI: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI: [[PTR_ADD15:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C9]](s64)
; VI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[EXTRACT1]](<4 x s32>)
; VI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
; VI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C1]](s32)
; VI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C2]](s32)
- ; VI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; VI: G_STORE [[COPY20]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
+ ; VI: G_STORE [[UV4]](s32), [[PTR_ADD15]](p1) :: (store (s8) into unknown-address + 16, addrspace 1)
; VI: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C3]](s64)
- ; VI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; VI: G_STORE [[COPY21]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
+ ; VI: G_STORE [[LSHR12]](s32), [[PTR_ADD16]](p1) :: (store (s8) into unknown-address + 17, addrspace 1)
; VI: [[PTR_ADD17:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C4]](s64)
- ; VI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; VI: G_STORE [[COPY22]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
+ ; VI: G_STORE [[LSHR13]](s32), [[PTR_ADD17]](p1) :: (store (s8) into unknown-address + 18, addrspace 1)
; VI: [[PTR_ADD18:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C5]](s64)
- ; VI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
- ; VI: G_STORE [[COPY23]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
+ ; VI: G_STORE [[LSHR14]](s32), [[PTR_ADD18]](p1) :: (store (s8) into unknown-address + 19, addrspace 1)
; VI: [[PTR_ADD19:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C6]](s64)
; VI: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
; VI: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C1]](s32)
; VI: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C2]](s32)
- ; VI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; VI: G_STORE [[COPY24]](s32), [[PTR_ADD19]](p1) :: (store (s8) into unknown-address + 20, addrspace 1)
+ ; VI: G_STORE [[UV5]](s32), [[PTR_ADD19]](p1) :: (store (s8) into unknown-address + 20, addrspace 1)
; VI: [[PTR_ADD20:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C3]](s64)
- ; VI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; VI: G_STORE [[COPY25]](s32), [[PTR_ADD20]](p1) :: (store (s8) into unknown-address + 21, addrspace 1)
+ ; VI: G_STORE [[LSHR15]](s32), [[PTR_ADD20]](p1) :: (store (s8) into unknown-address + 21, addrspace 1)
; VI: [[PTR_ADD21:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C4]](s64)
- ; VI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
- ; VI: G_STORE [[COPY26]](s32), [[PTR_ADD21]](p1) :: (store (s8) into unknown-address + 22, addrspace 1)
+ ; VI: G_STORE [[LSHR16]](s32), [[PTR_ADD21]](p1) :: (store (s8) into unknown-address + 22, addrspace 1)
; VI: [[PTR_ADD22:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD19]], [[C5]](s64)
- ; VI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
- ; VI: G_STORE [[COPY27]](s32), [[PTR_ADD22]](p1) :: (store (s8) into unknown-address + 23, addrspace 1)
+ ; VI: G_STORE [[LSHR17]](s32), [[PTR_ADD22]](p1) :: (store (s8) into unknown-address + 23, addrspace 1)
; VI: [[PTR_ADD23:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C7]](s64)
; VI: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C]](s32)
; VI: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C1]](s32)
; VI: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[UV6]], [[C2]](s32)
- ; VI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; VI: G_STORE [[COPY28]](s32), [[PTR_ADD23]](p1) :: (store (s8) into unknown-address + 24, addrspace 1)
+ ; VI: G_STORE [[UV6]](s32), [[PTR_ADD23]](p1) :: (store (s8) into unknown-address + 24, addrspace 1)
; VI: [[PTR_ADD24:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C3]](s64)
- ; VI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
- ; VI: G_STORE [[COPY29]](s32), [[PTR_ADD24]](p1) :: (store (s8) into unknown-address + 25, addrspace 1)
+ ; VI: G_STORE [[LSHR18]](s32), [[PTR_ADD24]](p1) :: (store (s8) into unknown-address + 25, addrspace 1)
; VI: [[PTR_ADD25:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C4]](s64)
- ; VI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
- ; VI: G_STORE [[COPY30]](s32), [[PTR_ADD25]](p1) :: (store (s8) into unknown-address + 26, addrspace 1)
+ ; VI: G_STORE [[LSHR19]](s32), [[PTR_ADD25]](p1) :: (store (s8) into unknown-address + 26, addrspace 1)
; VI: [[PTR_ADD26:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD23]], [[C5]](s64)
- ; VI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
- ; VI: G_STORE [[COPY31]](s32), [[PTR_ADD26]](p1) :: (store (s8) into unknown-address + 27, addrspace 1)
+ ; VI: G_STORE [[LSHR20]](s32), [[PTR_ADD26]](p1) :: (store (s8) into unknown-address + 27, addrspace 1)
; VI: [[PTR_ADD27:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C8]](s64)
; VI: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C]](s32)
; VI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C1]](s32)
; VI: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[UV7]], [[C2]](s32)
- ; VI: [[COPY32:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; VI: G_STORE [[COPY32]](s32), [[PTR_ADD27]](p1) :: (store (s8) into unknown-address + 28, addrspace 1)
+ ; VI: G_STORE [[UV7]](s32), [[PTR_ADD27]](p1) :: (store (s8) into unknown-address + 28, addrspace 1)
; VI: [[PTR_ADD28:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C3]](s64)
- ; VI: [[COPY33:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
- ; VI: G_STORE [[COPY33]](s32), [[PTR_ADD28]](p1) :: (store (s8) into unknown-address + 29, addrspace 1)
+ ; VI: G_STORE [[LSHR21]](s32), [[PTR_ADD28]](p1) :: (store (s8) into unknown-address + 29, addrspace 1)
; VI: [[PTR_ADD29:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C4]](s64)
- ; VI: [[COPY34:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
- ; VI: G_STORE [[COPY34]](s32), [[PTR_ADD29]](p1) :: (store (s8) into unknown-address + 30, addrspace 1)
+ ; VI: G_STORE [[LSHR22]](s32), [[PTR_ADD29]](p1) :: (store (s8) into unknown-address + 30, addrspace 1)
; VI: [[PTR_ADD30:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD27]], [[C5]](s64)
- ; VI: [[COPY35:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
- ; VI: G_STORE [[COPY35]](s32), [[PTR_ADD30]](p1) :: (store (s8) into unknown-address + 31, addrspace 1)
+ ; VI: G_STORE [[LSHR23]](s32), [[PTR_ADD30]](p1) :: (store (s8) into unknown-address + 31, addrspace 1)
; VI: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; VI: [[PTR_ADD31:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C10]](s64)
; VI: [[LSHR24:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT2]], [[C]](s32)
; VI: [[LSHR25:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT2]], [[C1]](s32)
; VI: [[LSHR26:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT2]], [[C2]](s32)
- ; VI: [[COPY36:%[0-9]+]]:_(s32) = COPY [[EXTRACT2]](s32)
- ; VI: G_STORE [[COPY36]](s32), [[PTR_ADD31]](p1) :: (store (s8) into unknown-address + 32, addrspace 1)
+ ; VI: G_STORE [[EXTRACT2]](s32), [[PTR_ADD31]](p1) :: (store (s8) into unknown-address + 32, addrspace 1)
; VI: [[PTR_ADD32:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD31]], [[C3]](s64)
- ; VI: [[COPY37:%[0-9]+]]:_(s32) = COPY [[LSHR24]](s32)
- ; VI: G_STORE [[COPY37]](s32), [[PTR_ADD32]](p1) :: (store (s8) into unknown-address + 33, addrspace 1)
+ ; VI: G_STORE [[LSHR24]](s32), [[PTR_ADD32]](p1) :: (store (s8) into unknown-address + 33, addrspace 1)
; VI: [[PTR_ADD33:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD31]], [[C4]](s64)
- ; VI: [[COPY38:%[0-9]+]]:_(s32) = COPY [[LSHR25]](s32)
- ; VI: G_STORE [[COPY38]](s32), [[PTR_ADD33]](p1) :: (store (s8) into unknown-address + 34, addrspace 1)
+ ; VI: G_STORE [[LSHR25]](s32), [[PTR_ADD33]](p1) :: (store (s8) into unknown-address + 34, addrspace 1)
; VI: [[PTR_ADD34:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD31]], [[C5]](s64)
- ; VI: [[COPY39:%[0-9]+]]:_(s32) = COPY [[LSHR26]](s32)
- ; VI: G_STORE [[COPY39]](s32), [[PTR_ADD34]](p1) :: (store (s8) into unknown-address + 35, addrspace 1)
+ ; VI: G_STORE [[LSHR26]](s32), [[PTR_ADD34]](p1) :: (store (s8) into unknown-address + 35, addrspace 1)
; GFX9-LABEL: name: test_store_global_v9s32_align1
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
@@ -8418,76 +7393,58 @@ body: |
; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](<2 x s32>)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; SI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<2 x s32>)
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; SI: G_STORE [[UV4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; SI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY9]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; SI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; SI: G_STORE [[COPY10]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; SI: G_STORE [[UV5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; SI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: G_STORE [[COPY11]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; SI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; SI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; SI: [[UV6:%[0-9]+]]:_(<2 x s32>), [[UV7:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[EXTRACT1]](<4 x s32>)
; SI: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV6]](<2 x s32>)
; SI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV8]], [[C]](s32)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV8]](s32)
- ; SI: G_STORE [[COPY12]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
+ ; SI: G_STORE [[UV8]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
; SI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; SI: G_STORE [[COPY13]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
+ ; SI: G_STORE [[LSHR4]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
; SI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; SI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV9]], [[C]](s32)
- ; SI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV9]](s32)
- ; SI: G_STORE [[COPY14]](s32), [[PTR_ADD9]](p1) :: (store (s16) into unknown-address + 20, addrspace 1)
+ ; SI: G_STORE [[UV9]](s32), [[PTR_ADD9]](p1) :: (store (s16) into unknown-address + 20, addrspace 1)
; SI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD9]], [[C1]](s64)
- ; SI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; SI: G_STORE [[COPY15]](s32), [[PTR_ADD10]](p1) :: (store (s16) into unknown-address + 22, addrspace 1)
+ ; SI: G_STORE [[LSHR5]](s32), [[PTR_ADD10]](p1) :: (store (s16) into unknown-address + 22, addrspace 1)
; SI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
; SI: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV7]](<2 x s32>)
; SI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV10]], [[C]](s32)
- ; SI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[UV10]](s32)
- ; SI: G_STORE [[COPY16]](s32), [[PTR_ADD11]](p1) :: (store (s16) into unknown-address + 24, addrspace 1)
+ ; SI: G_STORE [[UV10]](s32), [[PTR_ADD11]](p1) :: (store (s16) into unknown-address + 24, addrspace 1)
; SI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C1]](s64)
- ; SI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; SI: G_STORE [[COPY17]](s32), [[PTR_ADD12]](p1) :: (store (s16) into unknown-address + 26, addrspace 1)
+ ; SI: G_STORE [[LSHR6]](s32), [[PTR_ADD12]](p1) :: (store (s16) into unknown-address + 26, addrspace 1)
; SI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; SI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV11]], [[C]](s32)
- ; SI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[UV11]](s32)
- ; SI: G_STORE [[COPY18]](s32), [[PTR_ADD13]](p1) :: (store (s16) into unknown-address + 28, addrspace 1)
+ ; SI: G_STORE [[UV11]](s32), [[PTR_ADD13]](p1) :: (store (s16) into unknown-address + 28, addrspace 1)
; SI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD13]], [[C1]](s64)
- ; SI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; SI: G_STORE [[COPY19]](s32), [[PTR_ADD14]](p1) :: (store (s16) into unknown-address + 30, addrspace 1)
+ ; SI: G_STORE [[LSHR7]](s32), [[PTR_ADD14]](p1) :: (store (s16) into unknown-address + 30, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; SI: [[PTR_ADD15:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
; SI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT2]], [[C]](s32)
- ; SI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[EXTRACT2]](s32)
- ; SI: G_STORE [[COPY20]](s32), [[PTR_ADD15]](p1) :: (store (s16) into unknown-address + 32, addrspace 1)
+ ; SI: G_STORE [[EXTRACT2]](s32), [[PTR_ADD15]](p1) :: (store (s16) into unknown-address + 32, addrspace 1)
; SI: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C1]](s64)
- ; SI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; SI: G_STORE [[COPY21]](s32), [[PTR_ADD16]](p1) :: (store (s16) into unknown-address + 34, addrspace 1)
+ ; SI: G_STORE [[LSHR8]](s32), [[PTR_ADD16]](p1) :: (store (s16) into unknown-address + 34, addrspace 1)
; CI-LABEL: name: test_store_global_v9s32_align2
; CI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
@@ -8517,76 +7474,58 @@ body: |
; VI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](<2 x s32>)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY6]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD1]](p1) :: (store (s16) into unknown-address + 4, addrspace 1)
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD1]], [[C1]](s64)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; VI: G_STORE [[COPY7]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
+ ; VI: G_STORE [[LSHR1]](s32), [[PTR_ADD2]](p1) :: (store (s16) into unknown-address + 6, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; VI: [[PTR_ADD3:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
; VI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](<2 x s32>)
; VI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV4]], [[C]](s32)
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; VI: G_STORE [[COPY8]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
+ ; VI: G_STORE [[UV4]](s32), [[PTR_ADD3]](p1) :: (store (s16) into unknown-address + 8, addrspace 1)
; VI: [[PTR_ADD4:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C1]](s64)
- ; VI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; VI: G_STORE [[COPY9]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
+ ; VI: G_STORE [[LSHR2]](s32), [[PTR_ADD4]](p1) :: (store (s16) into unknown-address + 10, addrspace 1)
; VI: [[PTR_ADD5:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD3]], [[C2]](s64)
; VI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
- ; VI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; VI: G_STORE [[COPY10]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
+ ; VI: G_STORE [[UV5]](s32), [[PTR_ADD5]](p1) :: (store (s16) into unknown-address + 12, addrspace 1)
; VI: [[PTR_ADD6:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD5]], [[C1]](s64)
- ; VI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; VI: G_STORE [[COPY11]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
+ ; VI: G_STORE [[LSHR3]](s32), [[PTR_ADD6]](p1) :: (store (s16) into unknown-address + 14, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; VI: [[PTR_ADD7:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; VI: [[UV6:%[0-9]+]]:_(<2 x s32>), [[UV7:%[0-9]+]]:_(<2 x s32>) = G_UNMERGE_VALUES [[EXTRACT1]](<4 x s32>)
; VI: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV6]](<2 x s32>)
; VI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV8]], [[C]](s32)
- ; VI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV8]](s32)
- ; VI: G_STORE [[COPY12]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
+ ; VI: G_STORE [[UV8]](s32), [[PTR_ADD7]](p1) :: (store (s16) into unknown-address + 16, addrspace 1)
; VI: [[PTR_ADD8:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C1]](s64)
- ; VI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; VI: G_STORE [[COPY13]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
+ ; VI: G_STORE [[LSHR4]](s32), [[PTR_ADD8]](p1) :: (store (s16) into unknown-address + 18, addrspace 1)
; VI: [[PTR_ADD9:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C2]](s64)
; VI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV9]], [[C]](s32)
- ; VI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV9]](s32)
- ; VI: G_STORE [[COPY14]](s32), [[PTR_ADD9]](p1) :: (store (s16) into unknown-address + 20, addrspace 1)
+ ; VI: G_STORE [[UV9]](s32), [[PTR_ADD9]](p1) :: (store (s16) into unknown-address + 20, addrspace 1)
; VI: [[PTR_ADD10:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD9]], [[C1]](s64)
- ; VI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; VI: G_STORE [[COPY15]](s32), [[PTR_ADD10]](p1) :: (store (s16) into unknown-address + 22, addrspace 1)
+ ; VI: G_STORE [[LSHR5]](s32), [[PTR_ADD10]](p1) :: (store (s16) into unknown-address + 22, addrspace 1)
; VI: [[PTR_ADD11:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD7]], [[C3]](s64)
; VI: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV7]](<2 x s32>)
; VI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV10]], [[C]](s32)
- ; VI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[UV10]](s32)
- ; VI: G_STORE [[COPY16]](s32), [[PTR_ADD11]](p1) :: (store (s16) into unknown-address + 24, addrspace 1)
+ ; VI: G_STORE [[UV10]](s32), [[PTR_ADD11]](p1) :: (store (s16) into unknown-address + 24, addrspace 1)
; VI: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C1]](s64)
- ; VI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; VI: G_STORE [[COPY17]](s32), [[PTR_ADD12]](p1) :: (store (s16) into unknown-address + 26, addrspace 1)
+ ; VI: G_STORE [[LSHR6]](s32), [[PTR_ADD12]](p1) :: (store (s16) into unknown-address + 26, addrspace 1)
; VI: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD11]], [[C2]](s64)
; VI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV11]], [[C]](s32)
- ; VI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[UV11]](s32)
- ; VI: G_STORE [[COPY18]](s32), [[PTR_ADD13]](p1) :: (store (s16) into unknown-address + 28, addrspace 1)
+ ; VI: G_STORE [[UV11]](s32), [[PTR_ADD13]](p1) :: (store (s16) into unknown-address + 28, addrspace 1)
; VI: [[PTR_ADD14:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD13]], [[C1]](s64)
- ; VI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; VI: G_STORE [[COPY19]](s32), [[PTR_ADD14]](p1) :: (store (s16) into unknown-address + 30, addrspace 1)
+ ; VI: G_STORE [[LSHR7]](s32), [[PTR_ADD14]](p1) :: (store (s16) into unknown-address + 30, addrspace 1)
; VI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
; VI: [[PTR_ADD15:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
; VI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[EXTRACT2]], [[C]](s32)
- ; VI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[EXTRACT2]](s32)
- ; VI: G_STORE [[COPY20]](s32), [[PTR_ADD15]](p1) :: (store (s16) into unknown-address + 32, addrspace 1)
+ ; VI: G_STORE [[EXTRACT2]](s32), [[PTR_ADD15]](p1) :: (store (s16) into unknown-address + 32, addrspace 1)
; VI: [[PTR_ADD16:%[0-9]+]]:_(p1) = G_PTR_ADD [[PTR_ADD15]], [[C1]](s64)
- ; VI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; VI: G_STORE [[COPY21]](s32), [[PTR_ADD16]](p1) :: (store (s16) into unknown-address + 34, addrspace 1)
+ ; VI: G_STORE [[LSHR8]](s32), [[PTR_ADD16]](p1) :: (store (s16) into unknown-address + 34, addrspace 1)
; GFX9-LABEL: name: test_store_global_v9s32_align2
; GFX9: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
index 9090d70e5a9fd..e9bc9a2532f4c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
@@ -223,15 +223,12 @@ body: |
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI-LABEL: name: test_truncstore_global_s64_to_s16_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
@@ -241,8 +238,7 @@ body: |
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; VI: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
@@ -285,24 +281,20 @@ body: |
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
; VI-LABEL: name: test_truncstore_global_s64_to_s32_align2
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](s64)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s16) into unknown-address + 2, addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
G_STORE %1, %0 :: (store (s32), addrspace 1, align 2)
@@ -323,26 +315,20 @@ body: |
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY2]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
; SI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C1]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR1]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY7]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C5]](s64)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: G_STORE [[COPY8]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI-LABEL: name: test_truncstore_global_s64_to_s32_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
@@ -354,16 +340,14 @@ body: |
; VI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; VI: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
; VI: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR1]](s16)
; VI: G_STORE [[ANYEXT]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
; VI: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR2]](s16)
@@ -425,16 +409,14 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
; SI: G_STORE [[AND1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI-LABEL: name: test_store_global_i1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
; VI: G_STORE [[AND1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1
@@ -452,13 +434,11 @@ body: |
; SI-LABEL: name: test_store_global_i8
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI-LABEL: name: test_store_global_i8
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s8) = G_TRUNC %1
@@ -474,13 +454,11 @@ body: |
; SI-LABEL: name: test_store_global_i16
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; SI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI-LABEL: name: test_store_global_i16
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
+ ; VI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s16) = G_TRUNC %1
@@ -565,22 +543,18 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI-LABEL: name: test_store_global_v2s8_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[DEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<2 x s32>)
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY1]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(<2 x s8>) = G_IMPLICIT_DEF
G_STORE %1, %0 :: (store (<2 x s8>), addrspace 1, align 1)
@@ -602,8 +576,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -644,8 +617,7 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
@@ -689,24 +661,21 @@ body: |
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY2]](s32)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC2]]
- ; SI: [[COPY4:%[0-9]+]]:_(s16) = COPY [[OR]](s16)
- ; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY4]](s16)
+ ; SI: [[COPY3:%[0-9]+]]:_(s16) = COPY [[OR]](s16)
+ ; SI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY3]](s16)
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT]], [[C1]](s32)
- ; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY4]](s16)
+ ; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY3]](s16)
; SI: G_STORE [[ANYEXT]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY6]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI-LABEL: name: test_store_global_v3s8_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
@@ -731,8 +700,7 @@ body: |
; VI: G_STORE [[ANYEXT1]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
%2:_(<3 x s8>) = G_TRUNC %1
@@ -757,18 +725,16 @@ body: |
; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC2]]
- ; SI: [[COPY3:%[0-9]+]]:_(s16) = COPY [[OR]](s16)
- ; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY3]](s16)
+ ; SI: [[COPY2:%[0-9]+]]:_(s16) = COPY [[OR]](s16)
+ ; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY2]](s16)
; SI: G_STORE [[ANYEXT]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; SI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
; VI-LABEL: name: test_store_global_v3s8_align2
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
@@ -788,8 +754,7 @@ body: |
; VI: G_STORE [[ANYEXT]](s32), [[COPY]](p1) :: (store (s16), addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
%2:_(<3 x s8>) = G_TRUNC %1
@@ -814,15 +779,13 @@ body: |
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY2]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[C2]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -831,12 +794,11 @@ body: |
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C3]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY6]], [[C3]](s32)
+ ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
+ ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C3]](s32)
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C4]](s64)
- ; SI: G_STORE [[COPY6]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
+ ; SI: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
; SI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
; VI-LABEL: name: test_store_global_v3s8_align4
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
@@ -863,11 +825,10 @@ body: |
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY3]], [[C2]](s32)
+ ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C2]](s32)
; VI: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C3]](s64)
- ; VI: G_STORE [[COPY3]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
+ ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s16), align 4, addrspace 1)
; VI: G_STORE [[LSHR]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 2, align 2, addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(<3 x s32>) = COPY $vgpr2_vgpr3_vgpr4
@@ -886,38 +847,30 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; SI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; SI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; SI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; SI: G_STORE [[UV1]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; SI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; SI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; SI: G_STORE [[UV2]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; SI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; SI: G_STORE [[UV3]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
; VI-LABEL: name: test_store_global_v4s8_align1
; VI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; VI: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: G_STORE [[COPY2]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
+ ; VI: G_STORE [[UV]](s32), [[COPY]](p1) :: (store (s8), addrspace 1)
; VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; VI: [[PTR_ADD:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C]](s64)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: G_STORE [[COPY3]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
+ ; VI: G_STORE [[UV1]](s32), [[PTR_ADD]](p1) :: (store (s8) into unknown-address + 1, addrspace 1)
; VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; VI: [[PTR_ADD1:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C1]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: G_STORE [[COPY4]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
+ ; VI: G_STORE [[UV2]](s32), [[PTR_ADD1]](p1) :: (store (s8) into unknown-address + 2, addrspace 1)
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; VI: [[PTR_ADD2:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY]], [[C2]](s64)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: G_STORE [[COPY5]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
+ ; VI: G_STORE [[UV3]](s32), [[PTR_ADD2]](p1) :: (store (s8) into unknown-address + 3, addrspace 1)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
%2:_(<4 x s8>) = G_TRUNC %1
@@ -941,15 +894,13 @@ body: |
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY2]](s32)
; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[UV2]](s32)
; SI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C2]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C1]](s32)
; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; SI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC3]]
@@ -1001,20 +952,16 @@ body: |
; SI: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C]]
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; SI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; SI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
@@ -1024,20 +971,16 @@ body: |
; VI: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr2_vgpr3_vgpr4_vgpr5
; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<4 x s32>)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; VI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C1]](s32)
; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; VI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
; VI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; VI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C]]
; VI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; VI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C3]](s32)
; VI: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir
index f61b95608a461..c3e975491830e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir
@@ -79,12 +79,9 @@ body: |
; GFX6-LABEL: name: test_sub_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
+ ; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; GFX6: $vgpr0 = COPY [[AND]](s32)
; GFX8-LABEL: name: test_sub_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
@@ -125,17 +122,11 @@ body: |
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY4]], [[COPY5]]
+ ; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[BITCAST]], [[BITCAST1]]
+ ; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[LSHR]], [[LSHR1]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C1]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -183,17 +174,11 @@ body: |
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY6]], [[COPY7]]
+ ; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY3]]
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SUB]](s32)
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY8]], [[COPY9]]
+ ; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY4]]
; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SUB1]](s32)
- ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY10]], [[COPY11]]
+ ; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY5]]
; GFX6: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SUB2]](s32)
; GFX6: S_ENDPGM 0, implicit [[TRUNC]](s16), implicit [[TRUNC1]](s16), implicit [[TRUNC2]](s16)
; GFX8-LABEL: name: test_sub_v3s16
@@ -220,19 +205,13 @@ body: |
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[COPY1]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[COPY9]](s32)
+ ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY6]](s32)
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[COPY11]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[COPY4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY5]](s32), [[DEF]](s32)
; GFX9: [[SUB:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]]
; GFX9: [[SUB1:%[0-9]+]]:_(<2 x s16>) = G_SUB [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]]
; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[SUB]](<2 x s16>)
@@ -283,30 +262,18 @@ body: |
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY4]], [[COPY5]]
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[COPY6]], [[COPY7]]
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[COPY8]], [[COPY9]]
+ ; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[BITCAST]], [[BITCAST2]]
+ ; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[LSHR]], [[LSHR2]]
+ ; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[BITCAST1]], [[BITCAST3]]
+ ; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[LSHR1]], [[LSHR3]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C1]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SUB2]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[SUB3]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB2]], [[C1]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB3]], [[C1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
@@ -413,11 +380,8 @@ body: |
; GFX6-LABEL: name: test_sub_s7
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
+ ; GFX6: $vgpr0 = COPY [[SUB]](s32)
; GFX8-LABEL: name: test_sub_s7
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -452,27 +416,18 @@ body: |
; GFX6-LABEL: name: test_sub_s24
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
+ ; GFX6: $vgpr0 = COPY [[SUB]](s32)
; GFX8-LABEL: name: test_sub_s24
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; GFX8: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX8: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
+ ; GFX8: $vgpr0 = COPY [[SUB]](s32)
; GFX9-LABEL: name: test_sub_s24
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX9: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
+ ; GFX9: $vgpr0 = COPY [[SUB]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s24) = G_TRUNC %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uadde.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uadde.mir
index 343c700498419..a95f0c1ad1750 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uadde.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uadde.mir
@@ -57,10 +57,8 @@ body: |
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP3]](s1)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; CHECK: $vgpr2_vgpr3 = COPY [[BUILD_VECTOR1]](<2 x s32>)
@@ -89,17 +87,13 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY %13(s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND %13, [[C1]]
; CHECK: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[AND]], [[AND1]], [[ICMP]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UADDE]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UADDE]], [[C1]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UADDE]](s32), [[AND2]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UADDE]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP1]](s1)
- ; CHECK: $vgpr0 = COPY [[COPY6]](s32)
+ ; CHECK: $vgpr0 = COPY [[UADDE]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
index 135bb3735cc0c..fa60edc6ccdff 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
@@ -32,16 +32,12 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; CHECK: $vgpr0 = COPY [[AND3]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
@@ -67,16 +63,12 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; CHECK: $vgpr0 = COPY [[AND3]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
@@ -152,10 +144,8 @@ body: |
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; CHECK: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
; CHECK: $vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<2 x s32>)
@@ -225,26 +215,20 @@ body: |
; CHECK: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ADD2]](s16)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST6]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; CHECK: [[BITCAST9:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST7]], [[C1]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; CHECK: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST8]](<2 x s16>), [[BITCAST9]](<2 x s16>), [[BITCAST10]](<2 x s16>)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C2]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND3]](s32), [[AND4]](s32), [[AND5]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
@@ -321,14 +305,10 @@ body: |
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP3]](s1)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C1]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
; CHECK: $vgpr2_vgpr3_vgpr4_vgpr5 = COPY [[BUILD_VECTOR]](<4 x s32>)
@@ -360,10 +340,8 @@ body: |
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C]]
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; CHECK: $vgpr2_vgpr3 = COPY [[BUILD_VECTOR1]](<2 x s32>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
index dbcf803c88fba..67b82910e4a1a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
@@ -13,18 +13,15 @@ body: |
; GFX6-LABEL: name: uaddsat_s7
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; GFX6: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SHL]], [[C1]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[SHL1]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[UMIN]]
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[LSHR]](s32)
; GFX8-LABEL: name: uaddsat_s7
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -67,18 +64,15 @@ body: |
; GFX6-LABEL: name: uaddsat_s8
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; GFX6: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SHL]], [[C1]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[SHL1]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[UMIN]]
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[LSHR]](s32)
; GFX8-LABEL: name: uaddsat_s8
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -130,19 +124,15 @@ body: |
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C2]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C2]](s32)
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; GFX6: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SHL]], [[C3]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[SHL1]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[UMIN]]
; GFX6: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C2]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]](s32)
- ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C2]](s32)
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C2]](s32)
+ ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR3]], [[C2]](s32)
; GFX6: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[SHL2]], [[C3]]
; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[XOR1]], [[SHL3]]
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SHL2]], [[UMIN1]]
@@ -150,11 +140,10 @@ body: |
; GFX6: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR6]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C5]]
- ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY6]](s32)
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C5]]
+ ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY2]](s32)
; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -185,10 +174,8 @@ body: |
; GFX8: [[UADDSAT1:%[0-9]+]]:_(s16) = G_UADDSAT [[SHL2]], [[SHL3]]
; GFX8: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[UADDSAT1]], [[C3]](s16)
; GFX8: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX8: [[COPY2:%[0-9]+]]:_(s16) = COPY [[LSHR6]](s16)
- ; GFX8: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C4]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s16) = COPY [[LSHR7]](s16)
- ; GFX8: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C4]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s16) = G_AND [[LSHR6]], [[C4]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s16) = G_AND [[LSHR7]], [[C4]]
; GFX8: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16)
; GFX8: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -205,15 +192,11 @@ body: |
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[LSHR]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[LSHR3]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY6]](s32)
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY2]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[SHL1:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[UADDSAT:%[0-9]+]]:_(<2 x s16>) = G_UADDSAT [[SHL]], [[SHL1]]
@@ -223,10 +206,8 @@ body: |
; GFX9: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR7]](s32)
; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX9: [[COPY7:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
- ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
- ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C4]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C4]]
; GFX9: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16)
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL2]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -252,18 +233,15 @@ body: |
; GFX6-LABEL: name: uaddsat_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; GFX6: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SHL]], [[C1]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[SHL1]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[UMIN]]
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[LSHR]](s32)
; GFX8-LABEL: name: uaddsat_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -303,28 +281,22 @@ body: |
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; GFX6: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SHL]], [[C1]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[SHL1]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[UMIN]]
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
- ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
; GFX6: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[SHL2]], [[C1]]
; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[XOR1]], [[SHL3]]
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SHL2]], [[UMIN1]]
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C2]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C2]]
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL4]]
; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -379,27 +351,21 @@ body: |
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; GFX6: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SHL]], [[C1]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[SHL1]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[UMIN]]
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
- ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[BITCAST3]], [[C]](s32)
; GFX6: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[SHL2]], [[C1]]
; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[XOR1]], [[SHL3]]
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SHL2]], [[UMIN1]]
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)
- ; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32)
+ ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[C]](s32)
+ ; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[LSHR3]], [[C]](s32)
; GFX6: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[SHL4]], [[C1]]
; GFX6: [[UMIN2:%[0-9]+]]:_(s32) = G_UMIN [[XOR2]], [[SHL5]]
; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SHL4]], [[UMIN2]]
@@ -414,24 +380,18 @@ body: |
; GFX6: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; GFX6: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C2]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C2]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C2]]
; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL6]]
; GFX6: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C2]]
- ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C2]]
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C2]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C2]]
; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL7]]
; GFX6: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C2]]
- ; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C2]]
+ ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C2]]
+ ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C2]]
; GFX6: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX6: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL8]]
; GFX6: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -475,15 +435,12 @@ body: |
; GFX8: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[UADDSAT2]](s16)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; GFX8: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; GFX8: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; GFX8: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; GFX8: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -497,23 +454,17 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[DEF]](s32)
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[BITCAST3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR3]](s32), [[DEF]](s32)
; GFX9: [[UADDSAT:%[0-9]+]]:_(<2 x s16>) = G_UADDSAT [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]]
; GFX9: [[UADDSAT1:%[0-9]+]]:_(<2 x s16>) = G_UADDSAT [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]]
; GFX9: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@@ -527,15 +478,9 @@ body: |
; GFX9: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; GFX9: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; GFX9: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST4]](s32), [[LSHR4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST5]](s32), [[BITCAST6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR6]](s32), [[BITCAST7]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC4]](<2 x s16>), [[BUILD_VECTOR_TRUNC5]](<2 x s16>), [[BUILD_VECTOR_TRUNC6]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
@@ -566,51 +511,39 @@ body: |
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[BITCAST2]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; GFX6: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SHL]], [[C1]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[SHL1]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[UMIN]]
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
- ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[C]](s32)
; GFX6: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[SHL2]], [[C1]]
; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[XOR1]], [[SHL3]]
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SHL2]], [[UMIN1]]
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C]](s32)
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32)
- ; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C]](s32)
+ ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[C]](s32)
+ ; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[BITCAST3]], [[C]](s32)
; GFX6: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[SHL4]], [[C1]]
; GFX6: [[UMIN2:%[0-9]+]]:_(s32) = G_UMIN [[XOR2]], [[SHL5]]
; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SHL4]], [[UMIN2]]
; GFX6: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD2]], [[C]](s32)
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C]](s32)
- ; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C]](s32)
+ ; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
+ ; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[LSHR3]], [[C]](s32)
; GFX6: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SHL6]], [[C1]]
; GFX6: [[UMIN3:%[0-9]+]]:_(s32) = G_UMIN [[XOR3]], [[SHL7]]
; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[SHL6]], [[UMIN3]]
; GFX6: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[ADD3]], [[C]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C2]]
- ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C2]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C2]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C2]]
; GFX6: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL8]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C2]]
- ; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C2]]
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C2]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C2]]
; GFX6: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL9]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir
index 774cb0d9fd894..25136c1db223c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir
@@ -52,14 +52,10 @@ body: |
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
- ; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
- ; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN: [[UBFX:%[0-9]+]]:_(s32) = G_UBFX [[COPY5]], [[AND]](s32), [[AND1]]
- ; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UBFX]](s32)
- ; GCN: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+ ; GCN: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GCN: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GCN: [[UBFX:%[0-9]+]]:_(s32) = G_UBFX [[COPY]], [[AND]](s32), [[AND1]]
+ ; GCN: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UBFX]], [[C]]
; GCN: $vgpr0 = COPY [[AND2]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -83,14 +79,10 @@ body: |
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GCN: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
- ; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GCN: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
- ; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GCN: [[UBFX:%[0-9]+]]:_(s32) = G_UBFX [[COPY5]], [[AND]](s32), [[AND1]]
- ; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UBFX]](s32)
- ; GCN: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+ ; GCN: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GCN: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; GCN: [[UBFX:%[0-9]+]]:_(s32) = G_UBFX [[COPY]], [[AND]](s32), [[AND1]]
+ ; GCN: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UBFX]], [[C]]
; GCN: $vgpr0 = COPY [[AND2]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
index 0ecbdb9b267e2..8fa77d46896e2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
@@ -1652,10 +1652,8 @@ body: |
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX6: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX6: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1678,17 +1676,14 @@ body: |
; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT1]](s32), [[AND1]]
; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C3]]
; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT2]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT2]], [[C]]
; GFX6: $vgpr0 = COPY [[AND2]](s32)
; GFX8-LABEL: name: test_udiv_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX8: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1711,17 +1706,14 @@ body: |
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT1]](s32), [[AND1]]
; GFX8: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C3]]
; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT2]](s32)
- ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT2]], [[C]]
; GFX8: $vgpr0 = COPY [[AND2]](s32)
; GFX9-LABEL: name: test_udiv_s16
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX9: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1744,8 +1736,7 @@ body: |
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT1]](s32), [[AND1]]
; GFX9: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C3]]
; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT2]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT2]], [[C]]
; GFX9: $vgpr0 = COPY [[AND2]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -1771,10 +1762,8 @@ body: |
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; GFX6: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX6: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1797,10 +1786,8 @@ body: |
; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT1]](s32), [[AND1]]
; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C4]]
; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; GFX6: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[AND3]](s32)
; GFX6: [[AMDGPU_RCP_IFLAG1:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP1]](s32)
; GFX6: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1821,10 +1808,8 @@ body: |
; GFX6: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT4]](s32), [[AND3]]
; GFX6: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[SELECT3]], [[C4]]
; GFX6: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[ADD5]], [[SELECT3]]
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT2]](s32)
- ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT5]](s32)
- ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SELECT2]], [[C1]]
+ ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SELECT5]], [[C1]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -1838,10 +1823,8 @@ body: |
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; GFX8: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX8: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1864,10 +1847,8 @@ body: |
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT1]](s32), [[AND1]]
; GFX8: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C4]]
; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; GFX8: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[AND3]](s32)
; GFX8: [[AMDGPU_RCP_IFLAG1:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP1]](s32)
; GFX8: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1888,10 +1869,8 @@ body: |
; GFX8: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT4]](s32), [[AND3]]
; GFX8: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[SELECT3]], [[C4]]
; GFX8: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[ADD5]], [[SELECT3]]
- ; GFX8: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT2]](s32)
- ; GFX8: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; GFX8: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT5]](s32)
- ; GFX8: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; GFX8: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SELECT2]], [[C1]]
+ ; GFX8: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SELECT5]], [[C1]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -1905,10 +1884,8 @@ body: |
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; GFX9: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX9: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1931,10 +1908,8 @@ body: |
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT1]](s32), [[AND1]]
; GFX9: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C4]]
; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; GFX9: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[AND3]](s32)
; GFX9: [[AMDGPU_RCP_IFLAG1:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP1]](s32)
; GFX9: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1955,9 +1930,7 @@ body: |
; GFX9: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT4]](s32), [[AND3]]
; GFX9: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[SELECT3]], [[C4]]
; GFX9: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[ADD5]], [[SELECT3]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT2]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT5]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[SELECT2]](s32), [[SELECT5]](s32)
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
@@ -1975,10 +1948,8 @@ body: |
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX6: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX6: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -2001,16 +1972,13 @@ body: |
; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT1]](s32), [[AND1]]
; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C3]]
; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT2]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[SELECT2]](s32)
; GFX8-LABEL: name: test_udiv_s7
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX8: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -2033,16 +2001,13 @@ body: |
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT1]](s32), [[AND1]]
; GFX8: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C3]]
; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT2]](s32)
- ; GFX8: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX8: $vgpr0 = COPY [[SELECT2]](s32)
; GFX9-LABEL: name: test_udiv_s7
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX9: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -2065,8 +2030,7 @@ body: |
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT1]](s32), [[AND1]]
; GFX9: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C3]]
; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT2]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX9: $vgpr0 = COPY [[SELECT2]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s7) = G_TRUNC %0
@@ -2086,10 +2050,8 @@ body: |
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 131071
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX6: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX6: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -2112,16 +2074,13 @@ body: |
; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT1]](s32), [[AND1]]
; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C3]]
; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT2]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[SELECT2]](s32)
; GFX8-LABEL: name: test_udiv_s17
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 131071
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX8: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -2144,16 +2103,13 @@ body: |
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT1]](s32), [[AND1]]
; GFX8: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C3]]
; GFX8: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT2]](s32)
- ; GFX8: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX8: $vgpr0 = COPY [[SELECT2]](s32)
; GFX9-LABEL: name: test_udiv_s17
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 131071
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX9: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -2176,8 +2132,7 @@ body: |
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT1]](s32), [[AND1]]
; GFX9: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C3]]
; GFX9: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[ADD2]], [[SELECT]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT2]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX9: $vgpr0 = COPY [[SELECT2]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s17) = G_TRUNC %0
@@ -2197,10 +2152,8 @@ body: |
; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX6: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; GFX6: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
- ; GFX6: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; GFX6: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]]
- ; GFX6: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; GFX6: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY3]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX6: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX6: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
@@ -2350,16 +2303,13 @@ body: |
; GFX6: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]]
; GFX6: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX6: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s64) = COPY [[SELECT3]](s64)
- ; GFX6: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; GFX6: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
; GFX8-LABEL: name: test_udiv_s33
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; GFX8: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
- ; GFX8: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; GFX8: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; GFX8: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY3]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX8: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX8: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
@@ -2509,16 +2459,13 @@ body: |
; GFX8: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]]
; GFX8: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX8: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s64) = COPY [[SELECT3]](s64)
- ; GFX8: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; GFX8: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
; GFX9-LABEL: name: test_udiv_s33
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; GFX9: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
- ; GFX9: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; GFX9: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; GFX9: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY3]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX9: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX9: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
@@ -2668,8 +2615,7 @@ body: |
; GFX9: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]]
; GFX9: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX9: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s64) = COPY [[SELECT3]](s64)
- ; GFX9: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; GFX9: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s33) = G_TRUNC %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
index 747bd70082f5f..ae931a5c2fd9e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir
@@ -144,8 +144,7 @@ body: |
; GFX6-LABEL: name: test_uitofp_s16_to_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX6: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s32)
; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UITOFP]](s16)
; GFX6: $vgpr0 = COPY [[ANYEXT]](s32)
@@ -171,15 +170,13 @@ body: |
; GFX6-LABEL: name: test_uitofp_s16_to_s32
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX6: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
; GFX6: $vgpr0 = COPY [[UITOFP]](s32)
; GFX8-LABEL: name: test_uitofp_s16_to_s32
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX8: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
; GFX8: $vgpr0 = COPY [[UITOFP]](s32)
%0:_(s32) = COPY $vgpr0
@@ -197,15 +194,13 @@ body: |
; GFX6-LABEL: name: test_uitofp_s16_to_s64
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX6: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32)
; GFX6: $vgpr0_vgpr1 = COPY [[UITOFP]](s64)
; GFX8-LABEL: name: test_uitofp_s16_to_s64
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX8: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[UITOFP]](s64)
%0:_(s32) = COPY $vgpr0
@@ -223,16 +218,14 @@ body: |
; GFX6-LABEL: name: test_uitofp_s8_to_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX6: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s32)
; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UITOFP]](s16)
; GFX6: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX8-LABEL: name: test_uitofp_s8_to_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX8: [[UITOFP:%[0-9]+]]:_(s16) = G_UITOFP [[AND]](s32)
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UITOFP]](s16)
; GFX8: $vgpr0 = COPY [[ANYEXT]](s32)
@@ -252,15 +245,13 @@ body: |
; GFX6-LABEL: name: test_uitofp_s8_to_s32
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX6: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
; GFX6: $vgpr0 = COPY [[UITOFP]](s32)
; GFX8-LABEL: name: test_uitofp_s8_to_s32
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX8: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
; GFX8: $vgpr0 = COPY [[UITOFP]](s32)
%0:_(s32) = COPY $vgpr0
@@ -278,15 +269,13 @@ body: |
; GFX6-LABEL: name: test_uitofp_s8_to_s64
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX6: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32)
; GFX6: $vgpr0_vgpr1 = COPY [[UITOFP]](s64)
; GFX8-LABEL: name: test_uitofp_s8_to_s64
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; GFX8: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[AND]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[UITOFP]](s64)
%0:_(s32) = COPY $vgpr0
@@ -385,8 +374,7 @@ body: |
; GFX6-LABEL: name: test_uitofp_s33_to_s32
; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX6: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
- ; GFX6: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; GFX6: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
@@ -403,8 +391,7 @@ body: |
; GFX8-LABEL: name: test_uitofp_s33_to_s32
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
- ; GFX8: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; GFX8: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND]](s64)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
index bd116d1c89425..0699bbf049f35 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
@@ -71,13 +71,10 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UMAX]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[UMAX]](s32)
; VI-LABEL: name: test_umax_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -113,13 +110,10 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UMAX]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[UMAX]](s32)
; VI-LABEL: name: test_umax_s8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -161,35 +155,26 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 131071
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UMAX]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[UMAX]](s32)
; VI-LABEL: name: test_umax_s17
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 131071
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UMAX]](s32)
- ; VI: $vgpr0 = COPY [[COPY4]](s32)
+ ; VI: $vgpr0 = COPY [[UMAX]](s32)
; GFX9-LABEL: name: test_umax_s17
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 131071
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UMAX]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX9: $vgpr0 = COPY [[UMAX]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s17) = G_TRUNC %0
@@ -295,20 +280,14 @@ body: |
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; SI: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; SI: [[UMAX1:%[0-9]+]]:_(s32) = G_UMAX [[AND2]], [[AND3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UMAX]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UMAX1]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UMAX]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[UMAX1]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -366,27 +345,18 @@ body: |
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; SI: [[UMAX1:%[0-9]+]]:_(s32) = G_UMAX [[AND2]], [[AND3]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; SI: [[UMAX2:%[0-9]+]]:_(s32) = G_UMAX [[AND4]], [[AND5]]
; SI: [[DEF3:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; SI: [[DEF4:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UMAX]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UMAX1]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UMAX2]](s32)
- ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32)
+ ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UMAX]](s32), [[UMAX1]](s32), [[UMAX2]](s32)
; SI: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
; VI-LABEL: name: test_umax_v3s16
; VI: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@@ -438,10 +408,7 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UMAX1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s16>) = G_IMPLICIT_DEF
%1:_(<3 x s16>) = G_IMPLICIT_DEF
@@ -471,37 +438,25 @@ body: |
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; SI: [[UMAX1:%[0-9]+]]:_(s32) = G_UMAX [[AND2]], [[AND3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; SI: [[UMAX2:%[0-9]+]]:_(s32) = G_UMAX [[AND4]], [[AND5]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
; SI: [[UMAX3:%[0-9]+]]:_(s32) = G_UMAX [[AND6]], [[AND7]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UMAX]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UMAX1]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UMAX]], [[C1]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[UMAX1]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UMAX2]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UMAX3]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[UMAX2]], [[C1]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[UMAX3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL1]]
; SI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
index e8b596ecd7ead..ea6f606f3f982 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
@@ -71,13 +71,10 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UMIN]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[UMIN]](s32)
; VI-LABEL: name: test_umin_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -113,13 +110,10 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UMIN]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[UMIN]](s32)
; VI-LABEL: name: test_umin_s8
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -161,35 +155,26 @@ body: |
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 131071
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; SI: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UMIN]](s32)
- ; SI: $vgpr0 = COPY [[COPY4]](s32)
+ ; SI: $vgpr0 = COPY [[UMIN]](s32)
; VI-LABEL: name: test_umin_s17
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 131071
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; VI: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UMIN]](s32)
- ; VI: $vgpr0 = COPY [[COPY4]](s32)
+ ; VI: $vgpr0 = COPY [[UMIN]](s32)
; GFX9-LABEL: name: test_umin_s17
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 131071
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UMIN]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX9: $vgpr0 = COPY [[UMIN]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s17) = G_TRUNC %0
@@ -295,20 +280,14 @@ body: |
; SI: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; SI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; SI: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; SI: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AND2]], [[AND3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UMIN]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UMIN1]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UMIN]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[UMIN1]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; SI: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -366,27 +345,18 @@ body: |
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]]
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; SI: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AND2]], [[AND3]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; SI: [[UMIN2:%[0-9]+]]:_(s32) = G_UMIN [[AND4]], [[AND5]]
; SI: [[DEF3:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; SI: [[DEF4:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UMIN]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UMIN1]](s32)
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UMIN2]](s32)
- ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32)
+ ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UMIN]](s32), [[UMIN1]](s32), [[UMIN2]](s32)
; SI: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
; VI-LABEL: name: test_umin_v3s16
; VI: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@@ -438,10 +408,7 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UMIN1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
+ ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[LSHR]](s32), [[BITCAST1]](s32)
; GFX9: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s16>) = G_IMPLICIT_DEF
%1:_(<3 x s16>) = G_IMPLICIT_DEF
@@ -471,37 +438,25 @@ body: |
; SI: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; SI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; SI: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[AND]], [[AND1]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
; SI: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[AND2]], [[AND3]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; SI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; SI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; SI: [[UMIN2:%[0-9]+]]:_(s32) = G_UMIN [[AND4]], [[AND5]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
- ; SI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
+ ; SI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; SI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
; SI: [[UMIN3:%[0-9]+]]:_(s32) = G_UMIN [[AND6]], [[AND7]]
- ; SI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UMIN]](s32)
- ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; SI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UMIN1]](s32)
- ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; SI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UMIN]], [[C1]]
+ ; SI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[UMIN1]], [[C1]]
; SI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL]]
; SI: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; SI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UMIN2]](s32)
- ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; SI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UMIN3]](s32)
- ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; SI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[UMIN2]], [[C1]]
+ ; SI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[UMIN3]], [[C1]]
; SI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C]](s32)
; SI: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL1]]
; SI: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
index 07bb9756c7ada..83f55dc3c3ba2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
@@ -132,29 +132,23 @@ body: |
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C1]](s32)
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C]]
; GFX8: $vgpr0 = COPY [[AND2]](s32)
; GFX9-LABEL: name: test_umulh_s16
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C1]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C]]
; GFX9: $vgpr0 = COPY [[AND2]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -221,32 +215,24 @@ body: |
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX8: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C]]
; GFX8: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C1]](s32)
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
- ; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
+ ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C]]
; GFX8: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND2]], [[AND3]]
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C1]](s32)
- ; GFX8: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
- ; GFX8: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
+ ; GFX8: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C]]
+ ; GFX8: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C1]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; GFX8: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST]](<2 x s16>)
; GFX8: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; GFX8: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX8: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
- ; GFX8: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX8: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
+ ; GFX8: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C]]
+ ; GFX8: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C]]
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND6]](s32), [[AND7]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX9-LABEL: name: test_umulh_v2s16
@@ -255,28 +241,20 @@ body: |
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C]]
; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C1]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C]]
; GFX9: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND2]], [[AND3]]
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C1]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR]](s32), [[LSHR1]](s32)
; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C]]
; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND4]](s32), [[AND5]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
@@ -321,14 +299,11 @@ body: |
; GFX8: [[MUL2:%[0-9]+]]:_(s16) = G_MUL [[AND4]], [[AND5]]
; GFX8: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[MUL2]], [[C1]](s16)
; GFX8: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX8: [[COPY6:%[0-9]+]]:_(s16) = COPY [[LSHR]](s16)
- ; GFX8: [[AND6:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C]]
- ; GFX8: [[COPY7:%[0-9]+]]:_(s16) = COPY [[LSHR1]](s16)
- ; GFX8: [[AND7:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C]]
+ ; GFX8: [[AND6:%[0-9]+]]:_(s16) = G_AND [[LSHR]], [[C]]
+ ; GFX8: [[AND7:%[0-9]+]]:_(s16) = G_AND [[LSHR1]], [[C]]
; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND7]], [[C1]](s16)
; GFX8: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[SHL]]
- ; GFX8: [[COPY8:%[0-9]+]]:_(s16) = COPY [[LSHR2]](s16)
- ; GFX8: [[AND8:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C]]
+ ; GFX8: [[AND8:%[0-9]+]]:_(s16) = G_AND [[LSHR2]], [[C]]
; GFX8: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
; GFX8: [[AND9:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C]]
; GFX8: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND9]], [[C1]](s16)
@@ -338,8 +313,7 @@ body: |
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; GFX8: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX8: [[COPY9:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX8: $vgpr0 = COPY [[COPY9]](s32)
+ ; GFX8: $vgpr0 = COPY [[OR2]](s32)
; GFX9-LABEL: name: test_umulh_v3s8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -358,43 +332,35 @@ body: |
; GFX9: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[COPY5]](s32)
; GFX9: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX9: [[COPY6:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
- ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
- ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[AND1]](s16)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s16) = COPY [[TRUNC4]](s16)
- ; GFX9: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C]]
- ; GFX9: [[COPY9:%[0-9]+]]:_(s16) = COPY [[TRUNC5]](s16)
- ; GFX9: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY9]], [[C]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC5]], [[C]]
; GFX9: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[AND2]](s16)
; GFX9: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[AND3]](s16)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[ANYEXT3]](s32)
; GFX9: [[MUL:%[0-9]+]]:_(<2 x s16>) = G_MUL [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC1]]
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY10]](s32), [[C1]](s32)
+ ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[C1]](s32)
; GFX9: [[LSHR:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[MUL]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s16) = COPY [[TRUNC2]](s16)
- ; GFX9: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY11]], [[C]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s16) = COPY [[TRUNC3]](s16)
- ; GFX9: [[AND5:%[0-9]+]]:_(s16) = G_AND [[COPY12]], [[C]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C]]
; GFX9: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[AND4]](s16)
; GFX9: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[AND5]](s16)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT4]](s32), [[ANYEXT5]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s16) = COPY [[TRUNC6]](s16)
- ; GFX9: [[AND6:%[0-9]+]]:_(s16) = G_AND [[COPY13]], [[C]]
- ; GFX9: [[COPY14:%[0-9]+]]:_(s16) = COPY [[TRUNC7]](s16)
- ; GFX9: [[AND7:%[0-9]+]]:_(s16) = G_AND [[COPY14]], [[C]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s16) = G_AND [[TRUNC7]], [[C]]
; GFX9: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[AND6]](s16)
; GFX9: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[AND7]](s16)
; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT6]](s32), [[ANYEXT7]](s32)
; GFX9: [[MUL1:%[0-9]+]]:_(<2 x s16>) = G_MUL [[BUILD_VECTOR_TRUNC3]], [[BUILD_VECTOR_TRUNC4]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY15]](s32), [[COPY16]](s32)
+ ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
; GFX9: [[LSHR1:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[MUL1]], [[BUILD_VECTOR_TRUNC5]](<2 x s16>)
; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[LSHR]](<2 x s16>)
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
@@ -419,8 +385,7 @@ body: |
; GFX9: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL2]]
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[OR2]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY17]](s32)
+ ; GFX9: $vgpr0 = COPY [[OR2]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2
@@ -466,10 +431,8 @@ body: |
; GFX8: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C]]
; GFX8: [[MUL1:%[0-9]+]]:_(s16) = G_MUL [[AND2]], [[AND3]]
; GFX8: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[MUL1]], [[C1]](s16)
- ; GFX8: [[COPY4:%[0-9]+]]:_(s16) = COPY [[LSHR]](s16)
- ; GFX8: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C]]
- ; GFX8: [[COPY5:%[0-9]+]]:_(s16) = COPY [[LSHR1]](s16)
- ; GFX8: [[AND5:%[0-9]+]]:_(s16) = G_AND [[COPY5]], [[C]]
+ ; GFX8: [[AND4:%[0-9]+]]:_(s16) = G_AND [[LSHR]], [[C]]
+ ; GFX8: [[AND5:%[0-9]+]]:_(s16) = G_AND [[LSHR1]], [[C]]
; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C1]](s16)
; GFX8: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -484,35 +447,29 @@ body: |
; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY3]](s32)
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX9: [[COPY4:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
- ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
- ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY5]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[AND1]](s16)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s16) = COPY [[TRUNC2]](s16)
- ; GFX9: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s16) = COPY [[TRUNC3]](s16)
- ; GFX9: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C]]
; GFX9: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[AND2]](s16)
; GFX9: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[AND3]](s16)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[ANYEXT3]](s32)
; GFX9: [[MUL:%[0-9]+]]:_(<2 x s16>) = G_MUL [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC1]]
; GFX9: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY8]](s32), [[C2]](s32)
+ ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[C2]](s32)
; GFX9: [[LSHR:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[MUL]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[LSHR]](<2 x s16>)
; GFX9: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C3]](s32)
; GFX9: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s16) = COPY [[TRUNC4]](s16)
- ; GFX9: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY9]], [[C]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s16) = COPY [[TRUNC5]](s16)
- ; GFX9: [[AND5:%[0-9]+]]:_(s16) = G_AND [[COPY10]], [[C]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC5]], [[C]]
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C1]](s16)
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL]]
; GFX9: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -614,61 +571,49 @@ body: |
; GFX9: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR4]](s32)
; GFX9: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR5]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX9: [[COPY2:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
- ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C3]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
- ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C3]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[AND1]](s16)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s16) = COPY [[TRUNC4]](s16)
- ; GFX9: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C3]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s16) = COPY [[TRUNC5]](s16)
- ; GFX9: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY5]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC5]], [[C3]]
; GFX9: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[AND2]](s16)
; GFX9: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[AND3]](s16)
; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[ANYEXT3]](s32)
; GFX9: [[MUL:%[0-9]+]]:_(<2 x s16>) = G_MUL [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC1]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
; GFX9: [[LSHR6:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[MUL]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s16) = COPY [[TRUNC2]](s16)
- ; GFX9: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C3]]
- ; GFX9: [[COPY9:%[0-9]+]]:_(s16) = COPY [[TRUNC3]](s16)
- ; GFX9: [[AND5:%[0-9]+]]:_(s16) = G_AND [[COPY9]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C3]]
+ ; GFX9: [[AND5:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C3]]
; GFX9: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[AND4]](s16)
; GFX9: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[AND5]](s16)
; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT4]](s32), [[ANYEXT5]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s16) = COPY [[TRUNC6]](s16)
- ; GFX9: [[AND6:%[0-9]+]]:_(s16) = G_AND [[COPY10]], [[C3]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s16) = COPY [[TRUNC7]](s16)
- ; GFX9: [[AND7:%[0-9]+]]:_(s16) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC6]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s16) = G_AND [[TRUNC7]], [[C3]]
; GFX9: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[AND6]](s16)
; GFX9: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[AND7]](s16)
; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT6]](s32), [[ANYEXT7]](s32)
; GFX9: [[MUL1:%[0-9]+]]:_(<2 x s16>) = G_MUL [[BUILD_VECTOR_TRUNC3]], [[BUILD_VECTOR_TRUNC4]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY12]](s32), [[COPY13]](s32)
+ ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
; GFX9: [[LSHR7:%[0-9]+]]:_(<2 x s16>) = G_LSHR [[MUL1]], [[BUILD_VECTOR_TRUNC5]](<2 x s16>)
; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[LSHR6]](<2 x s16>)
; GFX9: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[LSHR7]](<2 x s16>)
; GFX9: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C4]]
- ; GFX9: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C4]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C4]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C4]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL]]
- ; GFX9: [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C4]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C4]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C1]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY17:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C4]]
+ ; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C4]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; GFX9: $vgpr0 = COPY [[OR2]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir
index c3e130924acbb..a51e8168ef3df 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir
@@ -58,10 +58,8 @@ body: |
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
; GFX8: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX8: $vgpr2_vgpr3 = COPY [[BUILD_VECTOR1]](<2 x s32>)
@@ -200,10 +198,8 @@ body: |
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[AND1]]
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX8: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
@@ -211,8 +207,7 @@ body: |
; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[AND2]]
; GFX8: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP]], [[ICMP1]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s1)
; GFX8: $vgpr0 = COPY [[AND3]](s32)
; GFX8: $vgpr1 = COPY [[ZEXT]](s32)
@@ -220,10 +215,8 @@ body: |
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[AND1]]
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
@@ -231,8 +224,7 @@ body: |
; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[AND2]]
; GFX9: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP]], [[ICMP1]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; GFX9: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s1)
; GFX9: $vgpr0 = COPY [[AND3]](s32)
; GFX9: $vgpr1 = COPY [[ZEXT]](s32)
@@ -258,15 +250,12 @@ body: |
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[AND2]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; GFX8: $vgpr0 = COPY [[AND3]](s32)
; GFX8: $vgpr1 = COPY [[ZEXT]](s32)
@@ -274,15 +263,12 @@ body: |
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[AND2]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; GFX9: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; GFX9: $vgpr0 = COPY [[AND3]](s32)
; GFX9: $vgpr1 = COPY [[ZEXT]](s32)
@@ -307,15 +293,12 @@ body: |
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[AND2]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; GFX8: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; GFX8: $vgpr0 = COPY [[AND3]](s32)
; GFX8: $vgpr1 = COPY [[ZEXT]](s32)
@@ -323,15 +306,12 @@ body: |
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[AND2]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; GFX9: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; GFX9: $vgpr0 = COPY [[AND3]](s32)
; GFX9: $vgpr1 = COPY [[ZEXT]](s32)
@@ -357,24 +337,18 @@ body: |
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX8: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C]]
; GFX8: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[AND2]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
- ; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; GFX8: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
+ ; GFX8: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C]]
; GFX8: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[AND4]]
; GFX8: [[AND5:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C]]
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL1]](s32), [[AND5]]
- ; GFX8: [[COPY6:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX8: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
- ; GFX8: [[COPY7:%[0-9]+]]:_(s32) = COPY [[MUL1]](s32)
- ; GFX8: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
+ ; GFX8: [[AND6:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
+ ; GFX8: [[AND7:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C]]
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C1]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL]]
@@ -382,17 +356,13 @@ body: |
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX8: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; GFX8: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; GFX8: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C2]]
- ; GFX8: [[COPY9:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; GFX8: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C2]]
+ ; GFX8: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
+ ; GFX8: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]]
; GFX8: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND8]](s32), [[AND9]](s32)
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST]](<2 x s16>)
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C1]](s32)
- ; GFX8: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX8: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
- ; GFX8: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
+ ; GFX8: [[AND10:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C]]
+ ; GFX8: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C]]
; GFX8: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND10]](s32), [[AND11]](s32)
; GFX8: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR1]](<2 x s32>)
; GFX8: $vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s32>)
@@ -402,23 +372,17 @@ body: |
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX9: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C]]
; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[AND2]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C]]
; GFX9: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[AND4]]
; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C]]
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL1]](s32), [[AND5]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[MUL1]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[MUL]](s32), [[MUL1]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
@@ -428,10 +392,8 @@ body: |
; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[BUILD_VECTOR_TRUNC]](<2 x s16>)
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C2]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
+ ; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C]]
; GFX9: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND8]](s32), [[AND9]](s32)
; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR1]](<2 x s32>)
; GFX9: $vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s32>)
@@ -458,17 +420,13 @@ body: |
; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
- ; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX8: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[AND2]]
- ; GFX8: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
- ; GFX8: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX8: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
+ ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX8: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX8: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[AND4]]
; GFX8: [[AND5:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C]]
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL1]](s32), [[AND5]]
@@ -492,17 +450,13 @@ body: |
; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[AND2]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX9: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[AND4]]
; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C]]
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL1]](s32), [[AND5]]
@@ -561,46 +515,34 @@ body: |
; GFX8: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX8: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX8: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C3]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; GFX8: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C3]]
; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[AND2]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
- ; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX8: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
+ ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; GFX8: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; GFX8: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[AND4]]
; GFX8: [[AND5:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C3]]
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL1]](s32), [[AND5]]
- ; GFX8: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
- ; GFX8: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX8: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX8: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
+ ; GFX8: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; GFX8: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[AND6]], [[AND7]]
; GFX8: [[AND8:%[0-9]+]]:_(s32) = G_AND [[MUL2]], [[C3]]
; GFX8: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL2]](s32), [[AND8]]
- ; GFX8: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX8: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
- ; GFX8: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX8: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
+ ; GFX8: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
+ ; GFX8: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; GFX8: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[AND9]], [[AND10]]
; GFX8: [[AND11:%[0-9]+]]:_(s32) = G_AND [[MUL3]], [[C3]]
; GFX8: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL3]](s32), [[AND11]]
- ; GFX8: [[COPY10:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX8: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
- ; GFX8: [[COPY11:%[0-9]+]]:_(s32) = COPY [[MUL1]](s32)
- ; GFX8: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX8: [[AND12:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C3]]
+ ; GFX8: [[AND13:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C3]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL]]
- ; GFX8: [[COPY12:%[0-9]+]]:_(s32) = COPY [[MUL2]](s32)
- ; GFX8: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX8: [[AND14:%[0-9]+]]:_(s32) = G_AND [[MUL2]], [[C3]]
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C1]](s32)
; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX8: [[COPY13:%[0-9]+]]:_(s32) = COPY [[MUL3]](s32)
- ; GFX8: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
+ ; GFX8: [[AND15:%[0-9]+]]:_(s32) = G_AND [[MUL3]], [[C3]]
; GFX8: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C2]](s32)
; GFX8: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
@@ -619,46 +561,34 @@ body: |
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C3]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; GFX9: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C3]]
; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL]](s32), [[AND2]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
+ ; GFX9: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
; GFX9: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[AND4]]
; GFX9: [[AND5:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C3]]
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL1]](s32), [[AND5]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; GFX9: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
+ ; GFX9: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; GFX9: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[AND6]], [[AND7]]
; GFX9: [[AND8:%[0-9]+]]:_(s32) = G_AND [[MUL2]], [[C3]]
; GFX9: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL2]](s32), [[AND8]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
+ ; GFX9: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
+ ; GFX9: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; GFX9: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[AND9]], [[AND10]]
; GFX9: [[AND11:%[0-9]+]]:_(s32) = G_AND [[MUL3]], [[C3]]
; GFX9: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[MUL3]](s32), [[AND11]]
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[MUL1]](s32)
- ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; GFX9: [[AND12:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C3]]
+ ; GFX9: [[AND13:%[0-9]+]]:_(s32) = G_AND [[MUL1]], [[C3]]
; GFX9: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[C]](s32)
; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND12]], [[SHL]]
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[MUL2]](s32)
- ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
+ ; GFX9: [[AND14:%[0-9]+]]:_(s32) = G_AND [[MUL2]], [[C3]]
; GFX9: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C1]](s32)
; GFX9: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
- ; GFX9: [[COPY13:%[0-9]+]]:_(s32) = COPY [[MUL3]](s32)
- ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
+ ; GFX9: [[AND15:%[0-9]+]]:_(s32) = G_AND [[MUL3]], [[C3]]
; GFX9: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND15]], [[C2]](s32)
; GFX9: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL2]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
index 4cedb8b02b6d5..8acd19c449581 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
@@ -42,10 +42,8 @@ body: |
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
+ ; CHECK: $vgpr0 = COPY [[BITCAST]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR]](s32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s16), %2:_(s16) = G_UNMERGE_VALUES %0
%3:_(s32) = G_ANYEXT %1
@@ -67,12 +65,9 @@ body: |
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY1]](s32)
- ; CHECK: $vgpr2 = COPY [[COPY2]](s32)
+ ; CHECK: $vgpr0 = COPY [[BITCAST]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR]](s32)
+ ; CHECK: $vgpr2 = COPY [[BITCAST1]](s32)
%0:_(<3 x s16>) = G_IMPLICIT_DEF
%1:_(s16), %2:_(s16), %3:_(s16) = G_UNMERGE_VALUES %0
%4:_(s32) = G_ANYEXT %1
@@ -97,14 +92,10 @@ body: |
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
- ; CHECK: $vgpr2 = COPY [[COPY3]](s32)
- ; CHECK: $vgpr3 = COPY [[COPY4]](s32)
+ ; CHECK: $vgpr0 = COPY [[BITCAST]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR]](s32)
+ ; CHECK: $vgpr2 = COPY [[BITCAST1]](s32)
+ ; CHECK: $vgpr3 = COPY [[LSHR1]](s32)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(s16), %2:_(s16), %3:_(s16), %4:_(s16) = G_UNMERGE_VALUES %0
%5:_(s32) = G_ANYEXT %1
@@ -132,18 +123,12 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
- ; CHECK: $vgpr2 = COPY [[COPY3]](s32)
- ; CHECK: $vgpr3 = COPY [[COPY4]](s32)
- ; CHECK: $vgpr4 = COPY [[COPY5]](s32)
- ; CHECK: $vgpr5 = COPY [[COPY6]](s32)
+ ; CHECK: $vgpr0 = COPY [[BITCAST]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR]](s32)
+ ; CHECK: $vgpr2 = COPY [[BITCAST1]](s32)
+ ; CHECK: $vgpr3 = COPY [[LSHR1]](s32)
+ ; CHECK: $vgpr4 = COPY [[BITCAST2]](s32)
+ ; CHECK: $vgpr5 = COPY [[LSHR2]](s32)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(s16), %2:_(s16), %3:_(s16), %4:_(s16), %5:_(s16), %6:_(s16) = G_UNMERGE_VALUES %0
%7:_(s32) = G_ANYEXT %1
@@ -174,10 +159,8 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s8), %3:_(s8) = G_UNMERGE_VALUES %1
@@ -200,14 +183,10 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
- ; CHECK: $vgpr2 = COPY [[COPY3]](s32)
- ; CHECK: $vgpr3 = COPY [[COPY4]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR]](s32)
+ ; CHECK: $vgpr2 = COPY [[LSHR1]](s32)
+ ; CHECK: $vgpr3 = COPY [[LSHR2]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8), %2:_(s8), %3:_(s8), %4:_(s8) = G_UNMERGE_VALUES %0
%5:_(s32) = G_ANYEXT %1
@@ -234,28 +213,19 @@ body: |
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
- ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY2]](s32)
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C1]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY6]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY7]](s32)
- ; CHECK: $vgpr2 = COPY [[COPY8]](s32)
- ; CHECK: $vgpr3 = COPY [[COPY9]](s32)
- ; CHECK: $vgpr4 = COPY [[COPY10]](s32)
- ; CHECK: $vgpr5 = COPY [[COPY11]](s32)
+ ; CHECK: $vgpr0 = COPY [[UV]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR2]](s32)
+ ; CHECK: $vgpr2 = COPY [[LSHR]](s32)
+ ; CHECK: $vgpr3 = COPY [[LSHR3]](s32)
+ ; CHECK: $vgpr4 = COPY [[UV1]](s32)
+ ; CHECK: $vgpr5 = COPY [[LSHR4]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s48) = G_TRUNC %0
%2:_(s8), %3:_(s8), %4:_(s8), %5:_(s8), %6:_(s8), %7:_(s8) = G_UNMERGE_VALUES %1
@@ -284,12 +254,9 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
- ; CHECK: $vgpr2 = COPY [[COPY3]](s32)
+ ; CHECK: $vgpr0 = COPY [[UV]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR]](s32)
+ ; CHECK: $vgpr2 = COPY [[UV1]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s48) = G_TRUNC %0
%2:_(s16), %3:_(s16), %4:_(s16) = G_UNMERGE_VALUES %1
@@ -315,36 +282,24 @@ body: |
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY2]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
- ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
- ; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
+ ; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY3]](s32)
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C1]](s32)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY8]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY9]](s32)
- ; CHECK: $vgpr2 = COPY [[COPY10]](s32)
- ; CHECK: $vgpr3 = COPY [[COPY11]](s32)
- ; CHECK: $vgpr4 = COPY [[COPY12]](s32)
- ; CHECK: $vgpr5 = COPY [[COPY13]](s32)
- ; CHECK: $vgpr6 = COPY [[COPY14]](s32)
- ; CHECK: $vgpr7 = COPY [[COPY15]](s32)
+ ; CHECK: $vgpr0 = COPY [[UV]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR2]](s32)
+ ; CHECK: $vgpr2 = COPY [[LSHR]](s32)
+ ; CHECK: $vgpr3 = COPY [[LSHR3]](s32)
+ ; CHECK: $vgpr4 = COPY [[UV1]](s32)
+ ; CHECK: $vgpr5 = COPY [[LSHR4]](s32)
+ ; CHECK: $vgpr6 = COPY [[LSHR1]](s32)
+ ; CHECK: $vgpr7 = COPY [[LSHR5]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s8), %2:_(s8), %3:_(s8), %4:_(s8), %5:_(s8), %6:_(s8), %7:_(s8), %8:_(s8) = G_UNMERGE_VALUES %0
%10:_(s32) = G_ANYEXT %1
@@ -379,36 +334,24 @@ body: |
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY2]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
- ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
- ; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
+ ; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY3]](s32)
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C1]](s32)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY8]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY9]](s32)
- ; CHECK: $vgpr2 = COPY [[COPY10]](s32)
- ; CHECK: $vgpr3 = COPY [[COPY11]](s32)
- ; CHECK: $vgpr4 = COPY [[COPY12]](s32)
- ; CHECK: $vgpr5 = COPY [[COPY13]](s32)
- ; CHECK: $vgpr6 = COPY [[COPY14]](s32)
- ; CHECK: $vgpr7 = COPY [[COPY15]](s32)
+ ; CHECK: $vgpr0 = COPY [[UV]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR2]](s32)
+ ; CHECK: $vgpr2 = COPY [[LSHR]](s32)
+ ; CHECK: $vgpr3 = COPY [[LSHR3]](s32)
+ ; CHECK: $vgpr4 = COPY [[UV1]](s32)
+ ; CHECK: $vgpr5 = COPY [[LSHR4]](s32)
+ ; CHECK: $vgpr6 = COPY [[LSHR1]](s32)
+ ; CHECK: $vgpr7 = COPY [[LSHR5]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s8), %2:_(s8), %3:_(s8), %4:_(s8), %5:_(s8), %6:_(s8), %7:_(s8), %8:_(s8) = G_UNMERGE_VALUES %0
%10:_(s32) = G_ANYEXT %1
@@ -443,84 +386,56 @@ body: |
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
- ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
+ ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY2]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
- ; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C2]]
+ ; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY3]](s32)
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY4]](s32)
+ ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY5]](s32)
+ ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]
+ ; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY6]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C2]]
- ; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY7]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C2]]
- ; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY9]](s32)
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C2]]
- ; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY11]](s32)
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C2]]
- ; CHECK: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY13]](s32)
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C2]]
- ; CHECK: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY15]](s32)
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C2]]
- ; CHECK: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[COPY17]](s32)
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C2]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
+ ; CHECK: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY7]](s32)
+ ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
+ ; CHECK: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY8]](s32)
+ ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C2]]
+ ; CHECK: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[COPY9]](s32)
+ ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; CHECK: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[C1]](s32)
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C2]]
+ ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; CHECK: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[C3]](s32)
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C2]]
+ ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C2]]
; CHECK: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[C4]](s32)
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[COPY35:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; CHECK: [[COPY36:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
- ; CHECK: [[COPY37:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY22]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY23]](s32)
- ; CHECK: $vgpr2 = COPY [[COPY24]](s32)
- ; CHECK: $vgpr3 = COPY [[COPY25]](s32)
- ; CHECK: $vgpr4 = COPY [[COPY26]](s32)
- ; CHECK: $vgpr5 = COPY [[COPY27]](s32)
- ; CHECK: $vgpr6 = COPY [[COPY28]](s32)
- ; CHECK: $vgpr7 = COPY [[COPY29]](s32)
- ; CHECK: $vgpr8 = COPY [[COPY30]](s32)
- ; CHECK: $vgpr9 = COPY [[COPY31]](s32)
- ; CHECK: $vgpr10 = COPY [[COPY32]](s32)
- ; CHECK: $vgpr11 = COPY [[COPY33]](s32)
- ; CHECK: $vgpr12 = COPY [[COPY34]](s32)
- ; CHECK: $vgpr13 = COPY [[COPY35]](s32)
- ; CHECK: $vgpr14 = COPY [[COPY36]](s32)
- ; CHECK: $vgpr15 = COPY [[COPY37]](s32)
+ ; CHECK: $vgpr0 = COPY [[UV]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR2]](s32)
+ ; CHECK: $vgpr2 = COPY [[LSHR3]](s32)
+ ; CHECK: $vgpr3 = COPY [[LSHR4]](s32)
+ ; CHECK: $vgpr4 = COPY [[LSHR]](s32)
+ ; CHECK: $vgpr5 = COPY [[LSHR5]](s32)
+ ; CHECK: $vgpr6 = COPY [[LSHR6]](s32)
+ ; CHECK: $vgpr7 = COPY [[LSHR7]](s32)
+ ; CHECK: $vgpr8 = COPY [[UV1]](s32)
+ ; CHECK: $vgpr9 = COPY [[LSHR8]](s32)
+ ; CHECK: $vgpr10 = COPY [[LSHR9]](s32)
+ ; CHECK: $vgpr11 = COPY [[LSHR10]](s32)
+ ; CHECK: $vgpr12 = COPY [[LSHR1]](s32)
+ ; CHECK: $vgpr13 = COPY [[LSHR11]](s32)
+ ; CHECK: $vgpr14 = COPY [[LSHR12]](s32)
+ ; CHECK: $vgpr15 = COPY [[LSHR13]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s4), %2:_(s4), %3:_(s4), %4:_(s4), %5:_(s4), %6:_(s4), %7:_(s4), %8:_(s4), %9:_(s4), %10:_(s4), %11:_(s4), %12:_(s4), %13:_(s4), %14:_(s4), %15:_(s4), %16:_(s4) = G_UNMERGE_VALUES %0
%17:_(s32) = G_ANYEXT %1
@@ -568,14 +483,10 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
- ; CHECK: $vgpr2 = COPY [[COPY3]](s32)
- ; CHECK: $vgpr3 = COPY [[COPY4]](s32)
+ ; CHECK: $vgpr0 = COPY [[UV]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR]](s32)
+ ; CHECK: $vgpr2 = COPY [[UV1]](s32)
+ ; CHECK: $vgpr3 = COPY [[LSHR1]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s16), %2:_(s16), %3:_(s16), %4:_(s16) = G_UNMERGE_VALUES %0
%5:_(s32) = G_ANYEXT %1
@@ -613,10 +524,8 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16), %2:_(s16) = G_UNMERGE_VALUES %0
%3:_(s32) = G_ANYEXT %1
@@ -635,10 +544,8 @@ body: |
; CHECK: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[PTRTOINT]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
+ ; CHECK: $vgpr0 = COPY [[PTRTOINT]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s16), %2:_(s16) = G_UNMERGE_VALUES %0
%3:_(s32) = G_ANYEXT %1
@@ -661,14 +568,10 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C2]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[PTRTOINT]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
- ; CHECK: $vgpr2 = COPY [[COPY3]](s32)
- ; CHECK: $vgpr3 = COPY [[COPY4]](s32)
+ ; CHECK: $vgpr0 = COPY [[PTRTOINT]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR]](s32)
+ ; CHECK: $vgpr2 = COPY [[LSHR1]](s32)
+ ; CHECK: $vgpr3 = COPY [[LSHR2]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s8), %2:_(s8), %3:_(s8), %4:_(s8) = G_UNMERGE_VALUES %0
%5:_(s32) = G_ANYEXT %1
@@ -693,14 +596,10 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
- ; CHECK: $vgpr2 = COPY [[COPY3]](s32)
- ; CHECK: $vgpr3 = COPY [[COPY4]](s32)
+ ; CHECK: $vgpr0 = COPY [[UV]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR]](s32)
+ ; CHECK: $vgpr2 = COPY [[UV1]](s32)
+ ; CHECK: $vgpr3 = COPY [[LSHR1]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s16), %2:_(s16), %3:_(s16), %4:_(s16) = G_UNMERGE_VALUES %0
%5:_(s32) = G_ANYEXT %1
@@ -782,12 +681,9 @@ body: |
; CHECK: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C29]](s32)
; CHECK: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C30]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
- ; CHECK: $vgpr2 = COPY [[COPY3]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR]](s32)
+ ; CHECK: $vgpr2 = COPY [[LSHR1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s3) = G_TRUNC %0
%2:_(s1), %3:_(s1), %4:_(s1) = G_UNMERGE_VALUES %1
@@ -868,22 +764,14 @@ body: |
; CHECK: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C29]](s32)
; CHECK: [[C30:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C30]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
- ; CHECK: $vgpr2 = COPY [[COPY3]](s32)
- ; CHECK: $vgpr3 = COPY [[COPY4]](s32)
- ; CHECK: $vgpr4 = COPY [[COPY5]](s32)
- ; CHECK: $vgpr5 = COPY [[COPY6]](s32)
- ; CHECK: $vgpr6 = COPY [[COPY7]](s32)
- ; CHECK: $vgpr7 = COPY [[COPY8]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR]](s32)
+ ; CHECK: $vgpr2 = COPY [[LSHR1]](s32)
+ ; CHECK: $vgpr3 = COPY [[LSHR2]](s32)
+ ; CHECK: $vgpr4 = COPY [[LSHR3]](s32)
+ ; CHECK: $vgpr5 = COPY [[LSHR4]](s32)
+ ; CHECK: $vgpr6 = COPY [[LSHR5]](s32)
+ ; CHECK: $vgpr7 = COPY [[LSHR6]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
%2:_(s1), %3:_(s1), %4:_(s1), %5:_(s1), %6:_(s1), %7:_(s1), %8:_(s1), %9:_(s1) = G_UNMERGE_VALUES %1
@@ -1042,14 +930,10 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
- ; CHECK: $vgpr2 = COPY [[COPY3]](s32)
- ; CHECK: $vgpr3 = COPY [[COPY4]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR]](s32)
+ ; CHECK: $vgpr2 = COPY [[LSHR1]](s32)
+ ; CHECK: $vgpr3 = COPY [[LSHR2]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(<4 x s8>) = G_BITCAST %0
%2:_(s8), %3:_(s8), %4:_(s8), %5:_(s8) = G_UNMERGE_VALUES %1
@@ -1077,12 +961,9 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
- ; CHECK: $vgpr2 = COPY [[COPY3]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR]](s32)
+ ; CHECK: $vgpr2 = COPY [[LSHR1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s24) = G_TRUNC %0
%2:_(<3 x s8>) = G_BITCAST %1
@@ -1109,10 +990,8 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
- ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
+ ; CHECK: $vgpr0 = COPY [[COPY]](s32)
+ ; CHECK: $vgpr1 = COPY [[LSHR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(<2 x s8>) = G_BITCAST %1
@@ -1165,40 +1044,16 @@ body: |
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C2]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C1]](s32)
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C2]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C]](s32)
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C1]](s32)
; CHECK: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[UV2]], [[C2]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
- ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32)
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32)
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[COPY12]](s32)
- ; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[LSHR]](s32), [[LSHR1]](s32)
+ ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR2]](s32), [[UV1]](s32), [[LSHR3]](s32)
+ ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR4]](s32), [[LSHR5]](s32), [[UV2]](s32)
+ ; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR6]](s32), [[LSHR7]](s32), [[LSHR8]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
; CHECK: $vgpr3_vgpr4_vgpr5 = COPY [[BUILD_VECTOR1]](<3 x s32>)
; CHECK: $vgpr6_vgpr7_vgpr8 = COPY [[BUILD_VECTOR2]](<3 x s32>)
@@ -1231,37 +1086,25 @@ body: |
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[BITCAST]](s32), [[LSHR]](s32), [[BITCAST1]](s32)
; CHECK: [[UV6:%[0-9]+]]:_(<2 x s16>), [[UV7:%[0-9]+]]:_(<2 x s16>), [[UV8:%[0-9]+]]:_(<2 x s16>), [[UV9:%[0-9]+]]:_(<2 x s16>), [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<12 x s16>)
; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV8]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)
+ ; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR2]](s32), [[BITCAST3]](s32), [[LSHR3]](s32)
; CHECK: [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>), [[UV14:%[0-9]+]]:_(<2 x s16>), [[UV15:%[0-9]+]]:_(<2 x s16>), [[UV16:%[0-9]+]]:_(<2 x s16>), [[UV17:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<12 x s16>)
; CHECK: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[UV15]](<2 x s16>)
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; CHECK: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV16]](<2 x s16>)
; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32)
+ ; CHECK: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[BITCAST4]](s32), [[LSHR4]](s32), [[BITCAST5]](s32)
; CHECK: [[UV18:%[0-9]+]]:_(<2 x s16>), [[UV19:%[0-9]+]]:_(<2 x s16>), [[UV20:%[0-9]+]]:_(<2 x s16>), [[UV21:%[0-9]+]]:_(<2 x s16>), [[UV22:%[0-9]+]]:_(<2 x s16>), [[UV23:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<12 x s16>)
; CHECK: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[UV22]](<2 x s16>)
; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; CHECK: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV23]](<2 x s16>)
; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32)
+ ; CHECK: [[BUILD_VECTOR3:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[LSHR6]](s32), [[BITCAST7]](s32), [[LSHR7]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
; CHECK: $vgpr3_vgpr4_vgpr5 = COPY [[BUILD_VECTOR1]](<3 x s32>)
; CHECK: $vgpr6_vgpr7_vgpr8 = COPY [[BUILD_VECTOR2]](<3 x s32>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
index ed54ca8bf3140..a9910b24f1de5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir
@@ -1568,10 +1568,8 @@ body: |
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX6: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX6: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1591,17 +1589,14 @@ body: |
; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C]]
; GFX6: $vgpr0 = COPY [[AND2]](s32)
; GFX8-LABEL: name: test_urem_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX8: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1621,17 +1616,14 @@ body: |
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
; GFX8: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX8: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C]]
; GFX8: $vgpr0 = COPY [[AND2]](s32)
; GFX9-LABEL: name: test_urem_s16
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX9: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1651,8 +1643,7 @@ body: |
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX9: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C]]
; GFX9: $vgpr0 = COPY [[AND2]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -1678,10 +1669,8 @@ body: |
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; GFX6: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX6: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1701,10 +1690,8 @@ body: |
; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; GFX6: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[AND3]](s32)
; GFX6: [[AMDGPU_RCP_IFLAG1:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP1]](s32)
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1723,10 +1710,8 @@ body: |
; GFX6: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT2]](s32), [[AND3]]
; GFX6: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[SELECT2]], [[AND3]]
; GFX6: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[SUB7]], [[SELECT2]]
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
- ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C1]]
+ ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SELECT3]], [[C1]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -1740,10 +1725,8 @@ body: |
; GFX8: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX8: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; GFX8: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX8: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1763,10 +1746,8 @@ body: |
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
; GFX8: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX8: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; GFX8: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX8: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; GFX8: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[AND3]](s32)
; GFX8: [[AMDGPU_RCP_IFLAG1:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP1]](s32)
; GFX8: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1785,10 +1766,8 @@ body: |
; GFX8: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT2]](s32), [[AND3]]
; GFX8: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[SELECT2]], [[AND3]]
; GFX8: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[SUB7]], [[SELECT2]]
- ; GFX8: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX8: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; GFX8: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
- ; GFX8: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; GFX8: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C1]]
+ ; GFX8: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SELECT3]], [[C1]]
; GFX8: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX8: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; GFX8: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -1802,10 +1781,8 @@ body: |
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; GFX9: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX9: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1825,10 +1802,8 @@ body: |
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX9: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; GFX9: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[AND3]](s32)
; GFX9: [[AMDGPU_RCP_IFLAG1:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP1]](s32)
; GFX9: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1847,9 +1822,7 @@ body: |
; GFX9: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT2]](s32), [[AND3]]
; GFX9: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[SELECT2]], [[AND3]]
; GFX9: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[SUB7]], [[SELECT2]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY7]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[SELECT1]](s32), [[SELECT3]](s32)
; GFX9: $vgpr0 = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(<2 x s16>) = COPY $vgpr1
@@ -1867,10 +1840,8 @@ body: |
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX6: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX6: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1890,16 +1861,13 @@ body: |
; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[SELECT1]](s32)
; GFX8-LABEL: name: test_urem_s7
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX8: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1919,16 +1887,13 @@ body: |
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
; GFX8: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX8: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX8: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX8: $vgpr0 = COPY [[SELECT1]](s32)
; GFX9-LABEL: name: test_urem_s7
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX9: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1948,8 +1913,7 @@ body: |
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX9: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX9: $vgpr0 = COPY [[SELECT1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s7) = G_TRUNC %0
@@ -1969,10 +1933,8 @@ body: |
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 131071
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX6: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX6: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -1992,16 +1954,13 @@ body: |
; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[SELECT1]](s32)
; GFX8-LABEL: name: test_urem_s17
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 131071
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX8: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX8: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -2021,16 +1980,13 @@ body: |
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
; GFX8: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX8: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX8: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX8: $vgpr0 = COPY [[SELECT1]](s32)
; GFX9-LABEL: name: test_urem_s17
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 131071
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX9: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND1]](s32)
; GFX9: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[UITOFP]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41EFFFFFC0000000
@@ -2050,8 +2006,7 @@ body: |
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[SELECT]](s32), [[AND1]]
; GFX9: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[AND1]]
; GFX9: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[SUB3]], [[SELECT]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX9: $vgpr0 = COPY [[SELECT1]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s17) = G_TRUNC %0
@@ -2071,10 +2026,8 @@ body: |
; GFX6: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX6: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; GFX6: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
- ; GFX6: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; GFX6: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]]
- ; GFX6: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; GFX6: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY3]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX6: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX6: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
@@ -2217,16 +2170,13 @@ body: |
; GFX6: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]]
; GFX6: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX6: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
- ; GFX6: [[COPY4:%[0-9]+]]:_(s64) = COPY [[SELECT3]](s64)
- ; GFX6: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; GFX6: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
; GFX8-LABEL: name: test_urem_s33
; GFX8: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX8: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; GFX8: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
- ; GFX8: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; GFX8: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; GFX8: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY3]], [[C]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX8: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX8: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
@@ -2369,16 +2319,13 @@ body: |
; GFX8: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]]
; GFX8: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX8: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
- ; GFX8: [[COPY4:%[0-9]+]]:_(s64) = COPY [[SELECT3]](s64)
- ; GFX8: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; GFX8: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
; GFX9-LABEL: name: test_urem_s33
; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; GFX9: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
- ; GFX9: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; GFX9: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; GFX9: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY3]], [[C]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AND1]](s64)
; GFX9: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[UV]](s32)
; GFX9: [[UITOFP1:%[0-9]+]]:_(s32) = G_UITOFP [[UV1]](s32)
@@ -2521,8 +2468,7 @@ body: |
; GFX9: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP6]](s1), [[MV2]], [[MV1]]
; GFX9: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SELECT]](s32), [[C6]]
; GFX9: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP7]](s1), [[SELECT2]], [[MV]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s64) = COPY [[SELECT3]](s64)
- ; GFX9: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; GFX9: $vgpr0_vgpr1 = COPY [[SELECT3]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s33) = G_TRUNC %0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
index d485a6c54e6d6..0c3ebf1c8bfa9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
@@ -13,20 +13,17 @@ body: |
; GFX6-LABEL: name: ushlsat_s7
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C1]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND]](s32)
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[SHL1]], [[AND]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; GFX6: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[LSHR]]
; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C2]], [[SHL1]]
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SELECT]], [[C1]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[LSHR1]](s32)
; GFX8-LABEL: name: ushlsat_s7
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -79,20 +76,17 @@ body: |
; GFX6-LABEL: name: ushlsat_s8
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C1]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND]](s32)
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[SHL1]], [[AND]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; GFX6: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[LSHR]]
; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C2]], [[SHL1]]
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SELECT]], [[C1]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[LSHR1]](s32)
; GFX8-LABEL: name: ushlsat_s8
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -154,21 +148,17 @@ body: |
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32)
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND]](s32)
; GFX6: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SHL1]], [[AND]](s32)
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; GFX6: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[LSHR6]]
; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C4]], [[SHL1]]
; GFX6: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[SELECT]], [[C2]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]](s32)
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C3]]
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C2]](s32)
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[AND1]](s32)
; GFX6: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[SHL3]], [[AND1]](s32)
; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s32), [[LSHR8]]
@@ -177,10 +167,9 @@ body: |
; GFX6: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR7]](s32)
; GFX6: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C5]]
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
- ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY6]](s32)
+ ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
+ ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[COPY2]](s32)
; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[TRUNC1]]
; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -218,10 +207,8 @@ body: |
; GFX8: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s16), [[LSHR8]]
; GFX8: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP1]](s1), [[C5]], [[SHL3]]
; GFX8: [[LSHR9:%[0-9]+]]:_(s16) = G_LSHR [[SELECT1]], [[C4]](s16)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s16) = COPY [[LSHR7]](s16)
- ; GFX8: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C3]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s16) = COPY [[LSHR9]](s16)
- ; GFX8: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C3]]
+ ; GFX8: [[AND2:%[0-9]+]]:_(s16) = G_AND [[LSHR7]], [[C3]]
+ ; GFX8: [[AND3:%[0-9]+]]:_(s16) = G_AND [[LSHR9]], [[C3]]
; GFX8: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C4]](s16)
; GFX8: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL4]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -259,10 +246,8 @@ body: |
; GFX9: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s16), [[LSHR8]]
; GFX9: [[SELECT1:%[0-9]+]]:_(s16) = G_SELECT [[ICMP1]](s1), [[C5]], [[SHL3]]
; GFX9: [[LSHR9:%[0-9]+]]:_(s16) = G_LSHR [[SELECT1]], [[C4]](s16)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s16) = COPY [[LSHR7]](s16)
- ; GFX9: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C3]]
- ; GFX9: [[COPY3:%[0-9]+]]:_(s16) = COPY [[LSHR9]](s16)
- ; GFX9: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C3]]
+ ; GFX9: [[AND2:%[0-9]+]]:_(s16) = G_AND [[LSHR7]], [[C3]]
+ ; GFX9: [[AND3:%[0-9]+]]:_(s16) = G_AND [[LSHR9]], [[C3]]
; GFX9: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C4]](s16)
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL4]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -288,20 +273,17 @@ body: |
; GFX6-LABEL: name: ushlsat_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C1]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND]](s32)
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[SHL1]], [[AND]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; GFX6: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[LSHR]]
; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C2]], [[SHL1]]
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SELECT]], [[C1]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[LSHR1]](s32)
; GFX8-LABEL: name: ushlsat_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -349,30 +331,24 @@ body: |
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND]](s32)
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[SHL1]], [[AND]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; GFX6: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[LSHR2]]
; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C2]], [[SHL1]]
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SELECT]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[AND1]](s32)
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[SHL3]], [[AND1]](s32)
; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s32), [[LSHR4]]
; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C2]], [[SHL3]]
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SELECT1]], [[C]](s32)
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL4]]
; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -454,30 +430,24 @@ body: |
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND]](s32)
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[SHL1]], [[AND]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; GFX6: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[LSHR4]]
; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C2]], [[SHL1]]
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SELECT]], [[C]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[AND1]](s32)
; GFX6: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SHL3]], [[AND1]](s32)
; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s32), [[LSHR6]]
; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C2]], [[SHL3]]
; GFX6: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[SELECT1]], [[C]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[C]](s32)
; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[SHL4]], [[AND2]](s32)
; GFX6: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[SHL5]], [[AND2]](s32)
; GFX6: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL4]](s32), [[LSHR8]]
@@ -492,24 +462,18 @@ body: |
; GFX6: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST4]], [[C]](s32)
; GFX6: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; GFX6: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
+ ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C1]]
; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL6]]
; GFX6: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX6: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C1]]
+ ; GFX6: [[AND6:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL7]]
; GFX6: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
- ; GFX6: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX6: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; GFX6: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR10]], [[C1]]
+ ; GFX6: [[AND8:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; GFX6: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
; GFX6: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL8]]
; GFX6: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -563,15 +527,12 @@ body: |
; GFX8: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[SELECT2]](s16)
; GFX8: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C2]]
; GFX8: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL4]]
; GFX8: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C2]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C2]]
+ ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C2]]
; GFX8: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; GFX8: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL5]]
; GFX8: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -622,11 +583,8 @@ body: |
; GFX9: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT1]](s16)
; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT1]](s32)
; GFX9: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT2]](s16)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[COPY1]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT2]](s32), [[BITCAST4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR7]](s32), [[BITCAST5]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC]](<2 x s16>), [[BUILD_VECTOR_TRUNC1]](<2 x s16>), [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
@@ -657,55 +615,43 @@ body: |
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[AND]](s32)
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[SHL1]], [[AND]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; GFX6: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[LSHR4]]
; GFX6: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C2]], [[SHL1]]
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SELECT]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[SHL2]], [[AND1]](s32)
; GFX6: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SHL3]], [[AND1]](s32)
; GFX6: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL2]](s32), [[LSHR6]]
; GFX6: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C2]], [[SHL3]]
; GFX6: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[SELECT1]], [[C]](s32)
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32)
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
+ ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[C]](s32)
; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[SHL4]], [[AND2]](s32)
; GFX6: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[SHL5]], [[AND2]](s32)
; GFX6: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL4]](s32), [[LSHR8]]
; GFX6: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s1), [[C2]], [[SHL5]]
; GFX6: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[SELECT2]], [[C]](s32)
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C]](s32)
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
+ ; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[SHL6]], [[AND3]](s32)
; GFX6: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[SHL7]], [[AND3]](s32)
; GFX6: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL6]](s32), [[LSHR10]]
; GFX6: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[C2]], [[SHL7]]
; GFX6: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[SELECT3]], [[C]](s32)
- ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
+ ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C1]]
; GFX6: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL8]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; GFX6: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; GFX6: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; GFX6: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C1]]
+ ; GFX6: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C1]]
; GFX6: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL9]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usube.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usube.mir
index 8f8128827d734..8bc18064085db 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usube.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usube.mir
@@ -68,10 +68,8 @@ body: |
; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT1]](s16)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT4]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT5]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT4]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT5]], [[C1]]
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; CHECK: $vgpr2_vgpr3 = COPY [[BUILD_VECTOR1]](<2 x s32>)
@@ -100,17 +98,13 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY %13(s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND %13, [[C1]]
; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[AND]], [[AND1]], [[ICMP]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[USUBE]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[USUBE]], [[C1]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[USUBE]](s32), [[AND2]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[USUBE]](s32)
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP1]](s1)
- ; CHECK: $vgpr0 = COPY [[COPY6]](s32)
+ ; CHECK: $vgpr0 = COPY [[USUBE]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
index 11f0b594de169..f3a0728f9a04f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
@@ -32,16 +32,12 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; CHECK: $vgpr0 = COPY [[AND3]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
@@ -67,16 +63,12 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; CHECK: $vgpr0 = COPY [[AND3]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
@@ -156,10 +148,8 @@ body: |
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; CHECK: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
; CHECK: $vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<2 x s32>)
@@ -237,26 +227,20 @@ body: |
; CHECK: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[SUB2]](s16)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST8]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; CHECK: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR8]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST9]], [[C1]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; CHECK: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST10]](<2 x s16>), [[BITCAST11]](<2 x s16>), [[BITCAST12]](<2 x s16>)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C2]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C2]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C2]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND3]](s32), [[AND4]](s32), [[AND5]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
@@ -342,14 +326,10 @@ body: |
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP2]](s1)
; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP3]](s1)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT3]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ANYEXT2]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ANYEXT3]], [[C1]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
; CHECK: $vgpr2_vgpr3_vgpr4_vgpr5 = COPY [[BUILD_VECTOR]](<4 x s32>)
@@ -382,10 +362,8 @@ body: |
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP1]](s1)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C]]
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; CHECK: $vgpr2_vgpr3 = COPY [[BUILD_VECTOR1]](<2 x s32>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
index 69c9e35b7c4b9..fc929d9a6f331 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
@@ -13,16 +13,13 @@ body: |
; GFX6-LABEL: name: usubsat_s7
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[SHL]], [[SHL1]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[UMIN]]
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[LSHR]](s32)
; GFX8-LABEL: name: usubsat_s7
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -65,16 +62,13 @@ body: |
; GFX6-LABEL: name: usubsat_s8
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[SHL]], [[SHL1]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[UMIN]]
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[LSHR]](s32)
; GFX8-LABEL: name: usubsat_s8
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -126,28 +120,23 @@ body: |
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C2]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C2]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C2]](s32)
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[SHL]], [[SHL1]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[UMIN]]
; GFX6: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C2]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]](s32)
- ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C2]](s32)
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C2]](s32)
+ ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR3]], [[C2]](s32)
; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[SHL2]], [[SHL3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SHL2]], [[UMIN1]]
; GFX6: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[SUB1]], [[C2]](s32)
; GFX6: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR6]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
- ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY6]](s32)
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C4]]
+ ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY2]](s32)
; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -178,10 +167,8 @@ body: |
; GFX8: [[USUBSAT1:%[0-9]+]]:_(s16) = G_USUBSAT [[SHL2]], [[SHL3]]
; GFX8: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[USUBSAT1]], [[C3]](s16)
; GFX8: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX8: [[COPY2:%[0-9]+]]:_(s16) = COPY [[LSHR6]](s16)
- ; GFX8: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C4]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s16) = COPY [[LSHR7]](s16)
- ; GFX8: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C4]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s16) = G_AND [[LSHR6]], [[C4]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s16) = G_AND [[LSHR7]], [[C4]]
; GFX8: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16)
; GFX8: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL4]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -198,15 +185,11 @@ body: |
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX9: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX9: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY3]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY]](s32), [[LSHR]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[LSHR3]](s32)
; GFX9: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[COPY6]](s32)
+ ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY2]](s32), [[COPY2]](s32)
; GFX9: [[SHL:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[SHL1:%[0-9]+]]:_(<2 x s16>) = G_SHL [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC2]](<2 x s16>)
; GFX9: [[USUBSAT:%[0-9]+]]:_(<2 x s16>) = G_USUBSAT [[SHL]], [[SHL1]]
@@ -216,10 +199,8 @@ body: |
; GFX9: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32)
; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR7]](s32)
; GFX9: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
- ; GFX9: [[COPY7:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
- ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C4]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
- ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C4]]
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C4]]
; GFX9: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16)
; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL2]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
@@ -245,16 +226,13 @@ body: |
; GFX6-LABEL: name: usubsat_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[SHL]], [[SHL1]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[UMIN]]
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY4]](s32)
+ ; GFX6: $vgpr0 = COPY [[LSHR]](s32)
; GFX8-LABEL: name: usubsat_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
@@ -294,25 +272,19 @@ body: |
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[C]](s32)
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[SHL]], [[SHL1]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[UMIN]]
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
- ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[SHL2]], [[SHL3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SHL2]], [[UMIN1]]
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SUB1]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL4]]
; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
@@ -367,24 +339,18 @@ body: |
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[C]](s32)
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[SHL]], [[SHL1]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[UMIN]]
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
- ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[BITCAST3]], [[C]](s32)
; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[SHL2]], [[SHL3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SHL2]], [[UMIN1]]
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SUB1]], [[C]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)
- ; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32)
+ ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[C]](s32)
+ ; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[LSHR3]], [[C]](s32)
; GFX6: [[UMIN2:%[0-9]+]]:_(s32) = G_UMIN [[SHL4]], [[SHL5]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL4]], [[UMIN2]]
; GFX6: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SUB2]], [[C]](s32)
@@ -398,24 +364,18 @@ body: |
; GFX6: [[BITCAST5:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; GFX6: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST5]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL6]]
; GFX6: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
- ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL7]]
; GFX6: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
- ; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
+ ; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C1]]
+ ; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; GFX6: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX6: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL8]]
; GFX6: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -459,15 +419,12 @@ body: |
; GFX8: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX8: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[USUBSAT2]](s16)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; GFX8: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST4]], [[C1]]
; GFX8: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32)
; GFX8: [[OR1:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL1]]
; GFX8: [[BITCAST7:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; GFX8: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; GFX8: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST5]], [[C1]]
; GFX8: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C]](s32)
; GFX8: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL2]]
; GFX8: [[BITCAST8:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -481,23 +438,17 @@ body: |
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX9: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX9: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
- ; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY1]](s32), [[COPY2]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST]](s32), [[LSHR]](s32)
; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY3]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST1]](s32), [[DEF]](s32)
; GFX9: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX9: [[UV3:%[0-9]+]]:_(<2 x s16>), [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
; GFX9: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; GFX9: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX9: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; GFX9: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY4]](s32), [[COPY5]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY6]](s32), [[DEF]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC2:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR2]](s32), [[BITCAST3]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC3:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR3]](s32), [[DEF]](s32)
; GFX9: [[USUBSAT:%[0-9]+]]:_(<2 x s16>) = G_USUBSAT [[BUILD_VECTOR_TRUNC]], [[BUILD_VECTOR_TRUNC2]]
; GFX9: [[USUBSAT1:%[0-9]+]]:_(<2 x s16>) = G_USUBSAT [[BUILD_VECTOR_TRUNC1]], [[BUILD_VECTOR_TRUNC3]]
; GFX9: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
@@ -511,15 +462,9 @@ body: |
; GFX9: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; GFX9: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; GFX9: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST4]](s32)
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY7]](s32), [[COPY8]](s32)
- ; GFX9: [[COPY9:%[0-9]+]]:_(s32) = COPY [[BITCAST5]](s32)
- ; GFX9: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY9]](s32), [[COPY10]](s32)
- ; GFX9: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX9: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
- ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[COPY11]](s32), [[COPY12]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC4:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST4]](s32), [[LSHR4]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC5:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[BITCAST5]](s32), [[BITCAST6]](s32)
+ ; GFX9: [[BUILD_VECTOR_TRUNC6:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[LSHR6]](s32), [[BITCAST7]](s32)
; GFX9: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BUILD_VECTOR_TRUNC4]](<2 x s16>), [[BUILD_VECTOR_TRUNC5]](<2 x s16>), [[BUILD_VECTOR_TRUNC6]](<2 x s16>)
; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS]](<6 x s16>)
%0:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
@@ -550,46 +495,34 @@ body: |
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
- ; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
- ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[BITCAST]], [[C]](s32)
+ ; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[BITCAST2]], [[C]](s32)
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[SHL]], [[SHL1]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[UMIN]]
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C]](s32)
- ; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
- ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)
+ ; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32)
+ ; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[C]](s32)
; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[SHL2]], [[SHL3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SHL2]], [[UMIN1]]
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SUB1]], [[C]](s32)
- ; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32)
- ; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C]](s32)
+ ; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[BITCAST1]], [[C]](s32)
+ ; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[BITCAST3]], [[C]](s32)
; GFX6: [[UMIN2:%[0-9]+]]:_(s32) = G_UMIN [[SHL4]], [[SHL5]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL4]], [[UMIN2]]
; GFX6: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SUB2]], [[C]](s32)
- ; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
- ; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C]](s32)
- ; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C]](s32)
+ ; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32)
+ ; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[LSHR3]], [[C]](s32)
; GFX6: [[UMIN3:%[0-9]+]]:_(s32) = G_UMIN [[SHL6]], [[SHL7]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SHL6]], [[UMIN3]]
; GFX6: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[SUB3]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
- ; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
+ ; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]
+ ; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
; GFX6: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL8]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
+ ; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C1]]
+ ; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C1]]
; GFX6: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL9]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
index 6283d780fde3d..814a4f9c528f6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
@@ -60,9 +60,7 @@ body: |
; CHECK: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP3]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR1]](s1)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = COPY $vgpr2_vgpr3
@@ -100,10 +98,7 @@ body: |
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s1)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR1]](s1)
; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR2]](s1)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ANYEXT2]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32), [[ANYEXT2]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
%1:_(<3 x s32>) = COPY $vgpr3_vgpr4_vgpr5
@@ -186,11 +181,8 @@ body: |
; CHECK-LABEL: name: test_xor_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
+ ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY1]]
+ ; CHECK: $vgpr0 = COPY [[XOR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s7) = G_TRUNC %0
@@ -209,11 +201,8 @@ body: |
; CHECK-LABEL: name: test_xor_s8
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
+ ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY1]]
+ ; CHECK: $vgpr0 = COPY [[XOR]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s8) = G_TRUNC %0
@@ -278,11 +267,8 @@ body: |
; CHECK-LABEL: name: test_xor_s48
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
- ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
- ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[XOR]](s64)
- ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
+ ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[COPY1]]
+ ; CHECK: $vgpr0_vgpr1 = COPY [[XOR]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s48) = G_TRUNC %0
@@ -457,24 +443,18 @@ body: |
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -543,24 +523,18 @@ body: |
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV19]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[BITCAST2]], [[C1]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C1]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[BITCAST3]], [[C1]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
; CHECK: [[BITCAST6:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
@@ -629,27 +603,11 @@ body: |
; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](<4 x s32>)
; CHECK: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](<4 x s32>)
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; CHECK: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; CHECK: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[COPY4]], [[COPY5]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; CHECK: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[COPY6]], [[COPY7]]
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[XOR1]](s32)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[XOR2]](s32)
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[XOR3]](s32)
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[COPY8]](s32)
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY9]](s32)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY10]](s32)
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY11]](s32)
- ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
+ ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[UV]], [[UV4]]
+ ; CHECK: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[UV1]], [[UV5]]
+ ; CHECK: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[UV2]], [[UV6]]
+ ; CHECK: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[UV3]], [[UV7]]
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[XOR]](s32), [[XOR1]](s32), [[XOR2]](s32), [[XOR3]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
%0:_(<4 x s8>) = G_IMPLICIT_DEF
%1:_(<4 x s8>) = G_IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
index 1b6f948196c1e..fc29df0cc2b1f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
@@ -43,8 +43,7 @@ body: |
; CHECK-LABEL: name: test_zext_s16_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
@@ -61,8 +60,7 @@ body: |
; CHECK-LABEL: name: test_zext_s24_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s24) = G_TRUNC %0
@@ -127,10 +125,8 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s16>) = COPY $vgpr0
@@ -156,12 +152,9 @@ body: |
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
@@ -185,14 +178,10 @@ body: |
; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[BITCAST]], [[C1]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[BITCAST1]], [[C1]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[AND]](s32), [[AND1]](s32), [[AND2]](s32), [[AND3]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
@@ -285,9 +274,7 @@ body: |
; CHECK-LABEL: name: test_zext_s8_to_s24
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY2]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s24) = G_TRUNC [[AND]](s32)
; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s24)
%0:_(s32) = COPY $vgpr0
@@ -306,8 +293,7 @@ body: |
; CHECK-LABEL: name: test_zext_s7_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: S_ENDPGM 0, implicit [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0
@@ -324,8 +310,7 @@ body: |
; CHECK-LABEL: name: test_zext_s8_to_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: S_ENDPGM 0, implicit [[AND]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
@@ -681,48 +666,39 @@ body: |
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C2]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[C3]]
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C2]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV2]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[UV2]], [[C3]]
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR2]], [[C3]]
; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C2]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL2]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV3]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
+ ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C2]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C2]](s32)
; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL3]]
; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR2]](s32), [[OR3]](s32)
; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C3]]
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]
; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C2]](s32)
; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL4]]
; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[C4]], [[C2]](s32)
; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[C4]], [[SHL5]]
; CHECK: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR4]](s32), [[OR5]](s32)
; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; CHECK: [[COPY11:%[0-9]+]]:_(s64) = COPY [[MV2]](s64)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV2]](s64)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s48) = G_EXTRACT [[DEF1]](s64), 0
- ; CHECK: [[COPY12:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; CHECK: [[EXTRACT1:%[0-9]+]]:_(s48) = G_EXTRACT [[MV1]](s64), 0
- ; CHECK: [[AND9:%[0-9]+]]:_(s64) = G_AND [[COPY11]], [[COPY12]]
+ ; CHECK: [[AND9:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[EXTRACT]](s48)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[EXTRACT1]](s48)
; CHECK: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[ANYEXT1]]
@@ -745,70 +721,51 @@ body: |
; CHECK: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF2]](s64)
; CHECK: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[UV14]], [[C2]](s32)
; CHECK: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[UV15]], [[C2]](s32)
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV4]](s32)
- ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
- ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
+ ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[UV4]], [[C3]]
+ ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]
; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C2]](s32)
; CHECK: [[OR6:%[0-9]+]]:_(s32) = G_OR [[AND11]], [[SHL6]]
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[UV5]](s32)
- ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
- ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C3]]
+ ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C3]]
+ ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C3]]
; CHECK: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C2]](s32)
; CHECK: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND13]], [[SHL7]]
; CHECK: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR6]](s32), [[OR7]](s32)
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[UV6]](s32)
- ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
- ; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C3]]
+ ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[UV6]], [[C3]]
+ ; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[LSHR7]], [[C3]]
; CHECK: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND16]], [[C2]](s32)
; CHECK: [[OR8:%[0-9]+]]:_(s32) = G_OR [[AND15]], [[SHL8]]
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[UV7]](s32)
- ; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
+ ; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[UV7]], [[C3]]
; CHECK: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND17]], [[SHL3]]
; CHECK: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR8]](s32), [[OR9]](s32)
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[UV8]](s32)
- ; CHECK: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C3]]
+ ; CHECK: [[AND18:%[0-9]+]]:_(s32) = G_AND [[UV8]], [[C3]]
; CHECK: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND18]], [[C2]](s32)
- ; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[COPY8]], [[SHL9]]
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
- ; CHECK: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[UV9]](s32)
- ; CHECK: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C3]]
+ ; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[SHL9]]
+ ; CHECK: [[AND19:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C3]]
+ ; CHECK: [[AND20:%[0-9]+]]:_(s32) = G_AND [[UV9]], [[C3]]
; CHECK: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND20]], [[C2]](s32)
; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[AND19]], [[SHL10]]
; CHECK: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR10]](s32), [[OR11]](s32)
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[UV10]](s32)
- ; CHECK: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
- ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
- ; CHECK: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY24]], [[C3]]
+ ; CHECK: [[AND21:%[0-9]+]]:_(s32) = G_AND [[UV10]], [[C3]]
+ ; CHECK: [[AND22:%[0-9]+]]:_(s32) = G_AND [[LSHR11]], [[C3]]
; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND22]], [[C2]](s32)
; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[AND21]], [[SHL11]]
- ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV11]](s32)
- ; CHECK: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C3]]
- ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[UV12]](s32)
- ; CHECK: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY26]], [[C3]]
+ ; CHECK: [[AND23:%[0-9]+]]:_(s32) = G_AND [[UV11]], [[C3]]
+ ; CHECK: [[AND24:%[0-9]+]]:_(s32) = G_AND [[UV12]], [[C3]]
; CHECK: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND24]], [[C2]](s32)
; CHECK: [[OR13:%[0-9]+]]:_(s32) = G_OR [[AND23]], [[SHL12]]
; CHECK: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR12]](s32), [[OR13]](s32)
- ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
- ; CHECK: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C3]]
- ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[UV13]](s32)
- ; CHECK: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY28]], [[C3]]
+ ; CHECK: [[AND25:%[0-9]+]]:_(s32) = G_AND [[LSHR13]], [[C3]]
+ ; CHECK: [[AND26:%[0-9]+]]:_(s32) = G_AND [[UV13]], [[C3]]
; CHECK: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND26]], [[C2]](s32)
; CHECK: [[OR14:%[0-9]+]]:_(s32) = G_OR [[AND25]], [[SHL13]]
- ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV14]](s32)
- ; CHECK: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C3]]
- ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
- ; CHECK: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY30]], [[C3]]
+ ; CHECK: [[AND27:%[0-9]+]]:_(s32) = G_AND [[UV14]], [[C3]]
+ ; CHECK: [[AND28:%[0-9]+]]:_(s32) = G_AND [[LSHR15]], [[C3]]
; CHECK: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND28]], [[C2]](s32)
; CHECK: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND27]], [[SHL14]]
; CHECK: [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR14]](s32), [[OR15]](s32)
- ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[UV15]](s32)
- ; CHECK: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C3]]
+ ; CHECK: [[AND29:%[0-9]+]]:_(s32) = G_AND [[UV15]], [[C3]]
; CHECK: [[OR16:%[0-9]+]]:_(s32) = G_OR [[AND29]], [[SHL3]]
- ; CHECK: [[OR17:%[0-9]+]]:_(s32) = G_OR [[COPY8]], [[SHL3]]
+ ; CHECK: [[OR17:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[SHL3]]
; CHECK: [[MV8:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR16]](s32), [[OR17]](s32)
; CHECK: [[MV9:%[0-9]+]]:_(s384) = G_MERGE_VALUES [[MV3]](s64), [[MV4]](s64), [[MV5]](s64), [[MV6]](s64), [[MV7]](s64), [[MV8]](s64)
; CHECK: [[TRUNC:%[0-9]+]]:_(s112) = G_TRUNC [[MV9]](s384)
@@ -828,8 +785,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 281474976710655
- ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY [[COPY]](s128)
- ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](s128)
+ ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[UV]], [[C]]
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[C1]]
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[AND]](s64), [[AND1]](s64)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir
index ca61bda6fcea4..417b271c494b0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir
@@ -46,13 +46,11 @@ body: |
; SI-LABEL: name: test_zextload_flat_i31_i8
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
- ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
- ; SI: $vgpr0 = COPY [[COPY1]](s32)
+ ; SI: $vgpr0 = COPY [[ZEXTLOAD]](s32)
; VI-LABEL: name: test_zextload_flat_i31_i8
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
- ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
- ; VI: $vgpr0 = COPY [[COPY1]](s32)
+ ; VI: $vgpr0 = COPY [[ZEXTLOAD]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s31) = G_ZEXTLOAD %0 :: (load (s8), addrspace 0)
%2:_(s32) = G_ANYEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
index c3d3d272b18fc..ac846e122251a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
@@ -174,13 +174,11 @@ body: |
; GFX8-LABEL: name: test_zextload_global_i31_i8
; GFX8: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX8: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
- ; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
- ; GFX8: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX8: $vgpr0 = COPY [[ZEXTLOAD]](s32)
; GFX6-LABEL: name: test_zextload_global_i31_i8
; GFX6: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GFX6: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
- ; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
- ; GFX6: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX6: $vgpr0 = COPY [[ZEXTLOAD]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s31) = G_ZEXTLOAD %0 :: (load (s8), addrspace 1)
%2:_(s32) = G_ANYEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-local.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-local.mir
index 8b7cddb5c14e6..49f1d5d5f601a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-local.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-local.mir
@@ -38,8 +38,7 @@ body: |
; CHECK-LABEL: name: test_zextload_local_i31_i8
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load (s8), addrspace 3)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s31) = G_ZEXTLOAD %0 :: (load (s8), addrspace 3)
%2:_(s32) = G_ANYEXT %1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-private.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-private.mir
index 757255b160fae..c3fb275dc32fd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-private.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-private.mir
@@ -39,8 +39,7 @@ body: |
; CHECK-LABEL: name: test_zextload_private_i31_i8
; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load (s8), addrspace 5)
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+ ; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
%0:_(p5) = COPY $vgpr0
%1:_(s31) = G_ZEXTLOAD %0 :: (load (s8), addrspace 5)
%2:_(s32) = G_ANYEXT %1
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir
index 68a008892e71c..fea02822da8bf 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir
@@ -97,8 +97,7 @@ body: |
; CHECK: [[X:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[BITMASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[XAGAIN:%[0-9]+]]:_(s32) = COPY [[X]]
- ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[XAGAIN]], [[BITMASK]]
+ ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITMASK]]
%0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
@@ -120,8 +119,7 @@ body: |
; CHECK: [[R32:%[0-9]+]]:_(s32) = G_SUB [[COUNT]], [[BITDIFF]]
%2(s16) = G_CTLZ %1
- ; CHECK: [[RAGAIN:%[0-9]+]]:_(s32) = COPY [[R32]]
- ; CHECK: [[SHIFTEDR:%[0-9]+]]:_(s32) = G_SHL [[RAGAIN]], [[BITDIFF]]
+ ; CHECK: [[SHIFTEDR:%[0-9]+]]:_(s32) = G_SHL [[R32]], [[BITDIFF]]
; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDR]], [[BITDIFF]]
; CHECK: $r0 = COPY [[R]]
%3(s32) = G_SEXT %2(s16)
@@ -147,8 +145,7 @@ body: |
; CHECK: [[X:%[0-9]+]]:_(s32) = COPY $r0
; CHECK: [[BITMASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[XAGAIN:%[0-9]+]]:_(s32) = COPY [[X]]
- ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[XAGAIN]], [[BITMASK]]
+ ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITMASK]]
%0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
@@ -166,8 +163,7 @@ body: |
; CHECK: [[R32:%[0-9]+]]:_(s32) = G_SUB [[COUNT]], [[BITDIFF]]
%2(s8) = G_CTLZ_ZERO_UNDEF %1
- ; CHECK: [[RAGAIN:%[0-9]+]]:_(s32) = COPY [[R32]]
- ; CHECK: [[SHIFTEDR:%[0-9]+]]:_(s32) = G_SHL [[RAGAIN]], [[BITDIFF]]
+ ; CHECK: [[SHIFTEDR:%[0-9]+]]:_(s32) = G_SHL [[R32]], [[BITDIFF]]
; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDR]], [[BITDIFF]]
; CHECK: $r0 = COPY [[R]]
%3(s32) = G_SEXT %2(s8)
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-casts.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-casts.mir
index 1a6a0dba1b3f4..dfcea03a5c0b2 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-casts.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-casts.mir
@@ -101,8 +101,7 @@ body: |
; CHECK-NOT: {{%[0-9]+}}(s8) = G_PTRTOINT
; CHECK: [[X32:%[0-9]+]]:_(s32) = G_PTRTOINT {{%[0-9]+}}(p0)
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[X32]]
- ; CHECK: {{%[0-9]+}}:_(s32) = G_AND [[COPY]], [[BITS]]
+ ; CHECK: {{%[0-9]+}}:_(s32) = G_AND [[X32]], [[BITS]]
; CHECK-NOT: {{%[0-9]+}}(s8) = G_PTRTOINT
%2(s32) = G_ZEXT %1(s8)
$r0 = COPY %2(s32)
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-control-flow.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-control-flow.mir
index 6065b771efd71..183f4b54376d0 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-control-flow.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-control-flow.mir
@@ -147,24 +147,20 @@ body: |
%5(s8) = G_TRUNC %4(s32)
; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2
- ; CHECK: [[V1:%[0-9]+]]:_(s32) = COPY [[R1]]
-
G_BRCOND %1(s1), %bb.1
G_BR %bb.2
bb.1:
- ; CHECK: [[V2:%[0-9]+]]:_(s32) = COPY [[R2]]
G_BR %bb.2
bb.2:
%6(s8) = G_PHI %3(s8), %bb.0, %5(s8), %bb.1
; G_PHI with s8 should widen, and all the truncs and exts should be combined
; away into a bunch of redundant copies
- ; CHECK: [[V:%[0-9]+]]:_(s32) = G_PHI [[V1]](s32), %bb.0, [[V2]](s32), %bb.1
+ ; CHECK: [[V:%[0-9]+]]:_(s32) = G_PHI [[R1]](s32), %bb.0, [[R2]](s32), %bb.1
%7(s32) = G_ANYEXT %6(s8)
$r0 = COPY %7(s32)
- ; CHECK: [[R:%[0-9]+]]:_(s32) = COPY [[V]]
- ; CHECK: $r0 = COPY [[R]](s32)
+ ; CHECK: $r0 = COPY [[V]](s32)
BX_RET 14, $noreg, implicit $r0
...
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
index aea81ed04190e..4a3b31313d456 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
@@ -123,11 +123,9 @@ body: |
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK-DAG: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
- ; CHECK-DAG: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]]
+ ; CHECK-DAG: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[R0]], [[BITS]]
; CHECK-DAG: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
- ; CHECK-DAG: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
+ ; CHECK-DAG: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[R1]], [[BITS]]
; CHECK-DAG: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
%0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
@@ -177,10 +175,8 @@ body: |
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
- ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]]
- ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
- ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
+ ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[R0]], [[BITS]]
+ ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[R1]], [[BITS]]
%0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
%2(s32) = COPY $r1
@@ -229,11 +225,9 @@ body: |
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK-DAG: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
- ; CHECK-DAG: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]]
+ ; CHECK-DAG: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[R0]], [[BITS]]
; CHECK-DAG: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
- ; CHECK-DAG: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
+ ; CHECK-DAG: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[R1]], [[BITS]]
; CHECK-DAG: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
%0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
@@ -283,10 +277,8 @@ body: |
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
- ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]]
- ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
- ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
+ ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[R0]], [[BITS]]
+ ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[R1]], [[BITS]]
%0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
%2(s32) = COPY $r1
@@ -415,11 +407,9 @@ body: |
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK-DAG: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
- ; CHECK-DAG: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]]
+ ; CHECK-DAG: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[R0]], [[BITS]]
; CHECK-DAG: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
- ; CHECK-DAG: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
+ ; CHECK-DAG: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[R1]], [[BITS]]
; CHECK-DAG: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
%0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
@@ -472,10 +462,8 @@ body: |
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
- ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]]
- ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
- ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
+ ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[R0]], [[BITS]]
+ ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[R1]], [[BITS]]
%0(s32) = COPY $r0
%1(s16) = G_TRUNC %0(s32)
%2(s32) = COPY $r1
@@ -527,11 +515,9 @@ body: |
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK-DAG: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
- ; CHECK-DAG: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[X]], [[BITS]]
+ ; CHECK-DAG: [[SHIFTEDX:%[0-9]+]]:_(s32) = G_SHL [[R0]], [[BITS]]
; CHECK-DAG: [[X32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDX]], [[BITS]]
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
- ; CHECK-DAG: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[Y]], [[BITS]]
+ ; CHECK-DAG: [[SHIFTEDY:%[0-9]+]]:_(s32) = G_SHL [[R1]], [[BITS]]
; CHECK-DAG: [[Y32:%[0-9]+]]:_(s32) = G_ASHR [[SHIFTEDY]], [[BITS]]
%0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
@@ -584,10 +570,8 @@ body: |
; The G_TRUNC will combine with the extensions introduced by the legalizer,
; leading to the following complicated sequences.
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY [[R0]]
- ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[X]], [[BITS]]
- ; CHECK: [[Y:%[0-9]+]]:_(s32) = COPY [[R1]]
- ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[Y]], [[BITS]]
+ ; CHECK: [[X32:%[0-9]+]]:_(s32) = G_AND [[R0]], [[BITS]]
+ ; CHECK: [[Y32:%[0-9]+]]:_(s32) = G_AND [[R1]], [[BITS]]
%0(s32) = COPY $r0
%1(s8) = G_TRUNC %0(s32)
%2(s32) = COPY $r1
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-exts.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-exts.mir
index 5e6301dc07b65..caf8db442dc53 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-exts.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-exts.mir
@@ -211,9 +211,8 @@ body: |
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[V8]](s8)
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[V8]](s8)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SEXT]]
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[OR]]
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[BITS]](s32)
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[BITS]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[BITS]](s32)
; CHECK: $r0 = COPY [[ASHR]]
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
index 8038d73ddb7f5..beaf8ac472178 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
@@ -1118,8 +1118,7 @@ body: |
; For soft float we just need to return a '-1' constant, but the truncation
; to 1 bit is converted by the combiner to the following masking sequence.
; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]](s32)
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[R]]
+ ; SOFT: [[REXT:%[0-9]+]]:_(s32) = COPY [[R]](s32)
; SOFT-NOT: G_FCMP
; CHECK: $r0 = COPY [[REXT]]
...
@@ -1154,9 +1153,7 @@ body: |
; For soft float we just need to return a '0' constant, but the truncation
; to 1 bit is converted by the combiner to the following masking sequence.
; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]](s32)
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
+ ; SOFT: [[REXT:%[0-9]+]]:_(s32) = COPY [[R]](s32)
; SOFT-NOT: G_FCMP
; CHECK: $r0 = COPY [[REXT]]
...
@@ -1195,8 +1192,7 @@ body: |
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
- ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
@@ -1241,8 +1237,7 @@ body: |
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
@@ -1287,8 +1282,7 @@ body: |
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
@@ -1333,8 +1327,7 @@ body: |
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
@@ -1379,8 +1372,7 @@ body: |
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
@@ -1670,8 +1662,7 @@ body: |
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
@@ -1724,16 +1715,14 @@ body: |
; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]]
- ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]]
- ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
- ; SOFT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_OR [[RET1]], [[RET2]]
+ ; SOFT-DEFAULT:[[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
; The result of the G_OR needs to be truncated, and the combiner turns the
; truncation into the following masking sequence.
; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]]
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
+ ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[R]], [[MASK]]
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32)
@@ -1783,16 +1772,14 @@ body: |
; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]]
- ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]]
- ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
- ; SOFT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_OR [[RET1]], [[RET2]]
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
; The result of the G_OR needs to be truncated, and the combiner turns the
; truncation into the following masking sequence.
; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]]
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
+ ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[R]], [[MASK]]
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
$r0 = COPY %3(s32)
@@ -1839,8 +1826,7 @@ body: |
; The result needs to be truncated, and the combiner turns the truncation
; into the following masking sequence.
; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[MASK]]
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
+ ; SOFT: [[REXT:%[0-9]+]]:_(s32) = COPY [[MASK]]
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
$r0 = COPY %7(s32)
@@ -1887,9 +1873,7 @@ body: |
; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; The result needs to be truncated, and the combiner turns the truncation
; into the following masking sequence.
- ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]]
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
+ ; SOFT: [[REXT:%[0-9]+]]:_(s32) = COPY [[R]]
; SOFT-NOT: G_FCMP
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
@@ -1946,8 +1930,7 @@ body: |
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
- ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
@@ -2006,8 +1989,7 @@ body: |
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
- ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
@@ -2066,8 +2048,7 @@ body: |
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
- ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
@@ -2126,8 +2107,7 @@ body: |
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
- ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
@@ -2186,8 +2166,7 @@ body: |
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
- ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
@@ -2575,8 +2554,7 @@ body: |
; For aeabi, we just need to truncate the result. The combiner changes the
; truncation into the following masking sequence.
; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
- ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RET]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
@@ -2645,16 +2623,14 @@ body: |
; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET2]](s32), [[ZERO]]
- ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]]
- ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
- ; SOFT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_OR [[RET1]], [[RET2]]
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
; The result of the G_OR needs to be truncated, and the combiner turns the
; truncation into the following masking sequence.
; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]]
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
+ ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[R]], [[MASK]]
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
$r0 = COPY %7(s32)
@@ -2720,16 +2696,14 @@ body: |
; SOFT: [[RET2:%[0-9]+]]:_(s32) = COPY $r0
; SOFT: ADJCALLSTACKUP
; SOFT-DEFAULT: [[R2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET2]](s32), [[ZERO]]
- ; SOFT-AEABI: [[R1EXT:%[0-9]+]]:_(s32) = COPY [[RET1]]
- ; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
- ; SOFT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
+ ; SOFT-AEABI:[[R:%[0-9]+]]:_(s32) = G_OR [[RET1]], [[RET2]]
+ ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
; The result of the G_OR needs to be truncated, and the combiner turns the
; truncation into the following masking sequence.
; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]]
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
+ ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[R]], [[MASK]]
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
$r0 = COPY %7(s32)
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
index 1ebaa2a532cc4..ca15f12feaccb 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-load-store.mir
@@ -69,8 +69,7 @@ body: |
; CHECK: [[LD:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load (s8))
; CHECK: [[ONE:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LD]]
- ; CHECK: [[COPYONE:%[0-9]+]]:_(s32) = COPY [[ONE]]
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[EXT]], [[COPYONE]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[EXT]], [[ONE]]
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[AND]]
; CHECK: G_STORE [[TRUNC]](s8), {{%[0-9]+}}(p0) :: (store (s8))
%0:_(p0) = COPY $r0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
index 7e9e3d1f3a4bf..cf6b47ae81f31 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/add.mir
@@ -48,12 +48,9 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
@@ -79,12 +76,9 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -109,11 +103,8 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[ADD]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
@@ -137,12 +128,9 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
@@ -168,12 +156,9 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -198,11 +183,8 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
+ ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[ADD]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
@@ -232,8 +214,7 @@ body: |
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY1]]
; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND]]
; MIPS32: $v0 = COPY [[ADD2]](s32)
; MIPS32: $v1 = COPY [[ADD]](s32)
@@ -282,18 +263,15 @@ body: |
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY]]
; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[COPY1]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[AND]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD2]](s32), [[LOAD1]]
; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LOAD2]], [[COPY2]]
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[AND1]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[LOAD2]]
; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[LOAD3]], [[COPY3]]
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
- ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[C]]
; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND2]]
; MIPS32: $v0 = COPY [[ADD]](s32)
; MIPS32: $v1 = COPY [[ADD2]](s32)
@@ -340,8 +318,7 @@ body: |
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[COPY1]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
; MIPS32: G_STORE [[AND1]](s32), [[COPY3]](p0) :: (store (s8) into %ir.pcarry_flag)
; MIPS32: G_STORE [[ADD]](s32), [[COPY2]](p0) :: (store (s32) into %ir.padd)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
index e02508ffd4fdd..b835634f58281 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
@@ -44,11 +44,8 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %2(s32)
@@ -72,11 +69,8 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
@@ -100,11 +94,8 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
@@ -182,11 +173,8 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
+ ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[OR]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %2(s32)
@@ -210,11 +198,8 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
+ ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[OR]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
@@ -238,11 +223,8 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
+ ; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[OR]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
@@ -320,11 +302,8 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
+ ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[XOR]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %2(s32)
@@ -348,11 +327,8 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
+ ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[XOR]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
@@ -376,11 +352,8 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
+ ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[XOR]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
@@ -613,13 +586,9 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[AND]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; MIPS32: $v0 = COPY [[COPY3]](s32)
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[COPY1]](s32)
+ ; MIPS32: $v0 = COPY [[SHL]](s32)
; MIPS32: RetRA implicit $v0
%1:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %1(s32)
@@ -642,16 +611,12 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
- ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32)
- ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C2]](s32)
- ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[AND]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
- ; MIPS32: $v0 = COPY [[COPY3]](s32)
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32)
+ ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
+ ; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[COPY1]](s32)
+ ; MIPS32: $v0 = COPY [[ASHR1]](s32)
; MIPS32: RetRA implicit $v0
%1:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %1(s32)
@@ -676,12 +641,9 @@ body: |
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
- ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[AND]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; MIPS32: $v0 = COPY [[COPY3]](s32)
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
+ ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
+ ; MIPS32: $v0 = COPY [[LSHR]](s32)
; MIPS32: RetRA implicit $v0
%1:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %1(s32)
@@ -718,14 +680,11 @@ body: |
; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]
; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[SUB]](s32)
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[SHL]], [[C1]]
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[OR]], [[SHL2]]
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C2]]
; MIPS32: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[COPY1]], [[SELECT1]]
; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: $v1 = COPY [[SELECT2]](s32)
@@ -771,14 +730,11 @@ body: |
; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[C2]](s32)
; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[SUB]](s32)
; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[OR]], [[ASHR2]]
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C3]]
; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[COPY]], [[SELECT]]
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
; MIPS32: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ASHR]], [[ASHR1]]
; MIPS32: $v0 = COPY [[SELECT1]](s32)
; MIPS32: $v1 = COPY [[SELECT2]](s32)
@@ -822,14 +778,11 @@ body: |
; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL]]
; MIPS32: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[SUB]](s32)
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[OR]], [[LSHR2]]
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C2]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C2]]
; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[COPY]], [[SELECT]]
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
; MIPS32: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[LSHR]], [[C1]]
; MIPS32: $v0 = COPY [[SELECT1]](s32)
; MIPS32: $v1 = COPY [[SELECT2]](s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir
index 566e2fcbfe545..621f1c478ebde 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/branch.mir
@@ -68,8 +68,7 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.if.then:
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir
index e30870b73635d..c1a20e9a94121 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir
@@ -55,10 +55,7 @@ body: |
; MIPS32-LABEL: name: signed_i16
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32)
- ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
- ; MIPS32: $v0 = COPY [[ASHR]](s32)
+ ; MIPS32: $v0 = COPY [[COPY]](s32)
; MIPS32: RetRA implicit $v0
%0:_(s16) = G_CONSTANT i16 -32768
%1:_(s32) = G_SEXT %0(s16)
@@ -75,10 +72,7 @@ body: |
; MIPS32-LABEL: name: signed_i8
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -128
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]](s32)
- ; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
- ; MIPS32: $v0 = COPY [[ASHR]](s32)
+ ; MIPS32: $v0 = COPY [[COPY]](s32)
; MIPS32: RetRA implicit $v0
%0:_(s8) = G_CONSTANT i8 -128
%1:_(s32) = G_SEXT %0(s8)
@@ -94,10 +88,8 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: unsigned_i16
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
- ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; MIPS32: $v0 = COPY [[AND]](s32)
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32768
+ ; MIPS32: $v0 = COPY [[C1]](s32)
; MIPS32: RetRA implicit $v0
%0:_(s16) = G_CONSTANT i16 -32768
%1:_(s32) = G_ZEXT %0(s16)
@@ -113,10 +105,8 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: unsigned_i8
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -128
- ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; MIPS32: $v0 = COPY [[AND]](s32)
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
+ ; MIPS32: $v0 = COPY [[C1]](s32)
; MIPS32: RetRA implicit $v0
%0:_(s8) = G_CONSTANT i8 -128
%1:_(s32) = G_ZEXT %0(s8)
@@ -133,8 +123,7 @@ body: |
; MIPS32-LABEL: name: i1_true
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; MIPS32: $v0 = COPY [[AND]](s32)
+ ; MIPS32: $v0 = COPY [[COPY]](s32)
; MIPS32: RetRA implicit $v0
%0:_(s1) = G_CONSTANT i1 true
%1:_(s32) = G_ZEXT %0(s1)
@@ -150,10 +139,8 @@ body: |
bb.1.entry:
; MIPS32-LABEL: name: i1_false
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
- ; MIPS32: $v0 = COPY [[AND]](s32)
+ ; MIPS32: $v0 = COPY [[COPY]](s32)
; MIPS32: RetRA implicit $v0
%0:_(s1) = G_CONSTANT i1 false
%1:_(s32) = G_ZEXT %0(s1)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir
index b5741df14fb9f..f3865435873ad 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ctlz.mir
@@ -39,8 +39,7 @@ body: |
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTLZ]], [[C1]]
; MIPS32: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[COPY1]](s32)
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C2]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ADD]], [[CTLZ1]]
; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: $v1 = COPY [[C]](s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir
index 0940d57460847..78a182ff4cfdd 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/cttz.mir
@@ -54,8 +54,7 @@ body: |
; MIPS32: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[AND1]](s32)
; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[CTLZ1]]
; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ADD1]], [[SUB1]]
; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: $v1 = COPY [[C]](s32)
@@ -92,8 +91,7 @@ body: |
; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ]]
; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = nuw nsw G_ADD [[SUB]], [[C]]
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C1]]
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[C1]], [[ADD1]]
; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $v0
@@ -137,22 +135,19 @@ body: |
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[ADD2]]
; MIPS32: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[AND1]](s32)
; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[CTLZ1]]
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND2]](s32), [[ADD1]], [[SUB1]]
; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[SELECT]], [[C]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[C]]
; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[C1]], [[C1]]
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[AND3]]
; MIPS32: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ADD3]](s32), [[ADD5]](s32)
; MIPS32: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C1]]
; MIPS32: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C1]]
; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR2]], [[XOR3]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s32), [[C1]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
- ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[C]]
; MIPS32: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[AND4]](s32), [[MV]], [[MV1]]
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT1]](s64)
; MIPS32: $v0 = COPY [[UV]](s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
index 2f7d043afcc00..00f630bfd1283 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/dyn_stackalloc.mir
@@ -47,15 +47,13 @@ body: |
; MIPS32: [[COPY3:%[0-9]+]]:_(p0) = COPY [[INTTOPTR]](p0)
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[COPY3]](p0)
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: $a1 = COPY [[COPY4]](s32)
+ ; MIPS32: $a1 = COPY [[COPY]](s32)
; MIPS32: $a2 = COPY [[COPY1]](s32)
; MIPS32: JAL &memset, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit $a2
; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY3]], [[COPY1]](s32)
- ; MIPS32: [[COPY5:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; MIPS32: G_STORE [[COPY6]](s32), [[COPY5]](p0) :: (store (s8) into %ir.arrayidx)
+ ; MIPS32: [[COPY4:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
+ ; MIPS32: G_STORE [[C1]](s32), [[COPY4]](p0) :: (store (s8) into %ir.arrayidx)
; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; MIPS32: $a0 = COPY [[COPY3]](p0)
; MIPS32: JAL @puts, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit-def $v0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fcmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fcmp.mir
index 26e8a883081c1..141113b6efa26 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fcmp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fcmp.mir
@@ -20,16 +20,14 @@ body: |
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
- ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
- ; FP32: $v0 = COPY [[COPY2]](s32)
+ ; FP32: $v0 = COPY [[FCMP]](s32)
; FP32: RetRA implicit $v0
; FP64-LABEL: name: oeq_s
; FP64: liveins: $f12, $f14
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
- ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
- ; FP64: $v0 = COPY [[COPY2]](s32)
+ ; FP64: $v0 = COPY [[FCMP]](s32)
; FP64: RetRA implicit $v0
%0:_(s32) = COPY $f12
%1:_(s32) = COPY $f14
@@ -52,16 +50,14 @@ body: |
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]]
- ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
- ; FP32: $v0 = COPY [[COPY2]](s32)
+ ; FP32: $v0 = COPY [[FCMP]](s32)
; FP32: RetRA implicit $v0
; FP64-LABEL: name: oeq_d
; FP64: liveins: $d6, $d7
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64: [[COPY1:%[0-9]+]]:_(s64) = COPY $d7
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]]
- ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
- ; FP64: $v0 = COPY [[COPY2]](s32)
+ ; FP64: $v0 = COPY [[FCMP]](s32)
; FP64: RetRA implicit $v0
%0:_(s64) = COPY $d6
%1:_(s64) = COPY $d7
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
index d47ba8805dbfd..88910e3e19fdf 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir
@@ -99,9 +99,8 @@ body: |
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP32: $v0 = COPY [[ASHR]](s32)
; FP32: RetRA implicit $v0
@@ -109,9 +108,8 @@ body: |
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP64: $v0 = COPY [[ASHR]](s32)
; FP64: RetRA implicit $v0
@@ -134,9 +132,8 @@ body: |
; FP32: liveins: $f12
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP32: $v0 = COPY [[ASHR]](s32)
; FP32: RetRA implicit $v0
@@ -144,9 +141,8 @@ body: |
; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP64: $v0 = COPY [[ASHR]](s32)
; FP64: RetRA implicit $v0
@@ -235,9 +231,8 @@ body: |
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP32: $v0 = COPY [[ASHR]](s32)
; FP32: RetRA implicit $v0
@@ -245,9 +240,8 @@ body: |
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP64: $v0 = COPY [[ASHR]](s32)
; FP64: RetRA implicit $v0
@@ -270,9 +264,8 @@ body: |
; FP32: liveins: $d6
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP32: $v0 = COPY [[ASHR]](s32)
; FP32: RetRA implicit $v0
@@ -280,9 +273,8 @@ body: |
; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FPTOSI]], [[C]](s32)
; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP64: $v0 = COPY [[ASHR]](s32)
; FP64: RetRA implicit $v0
@@ -352,8 +344,7 @@ body: |
; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
- ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP32: $v0 = COPY [[SELECT]](s32)
; FP32: RetRA implicit $v0
@@ -368,8 +359,7 @@ body: |
; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
- ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP64: $v0 = COPY [[SELECT]](s32)
; FP64: RetRA implicit $v0
@@ -398,12 +388,10 @@ body: |
; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
- ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
; FP32: $v0 = COPY [[AND1]](s32)
; FP32: RetRA implicit $v0
; FP64-LABEL: name: f32tou16
@@ -417,12 +405,10 @@ body: |
; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
- ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP64: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
; FP64: $v0 = COPY [[AND1]](s32)
; FP64: RetRA implicit $v0
%0:_(s32) = COPY $f12
@@ -451,12 +437,10 @@ body: |
; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
- ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
; FP32: $v0 = COPY [[AND1]](s32)
; FP32: RetRA implicit $v0
; FP64-LABEL: name: f32tou8
@@ -470,12 +454,10 @@ body: |
; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
- ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP64: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
; FP64: $v0 = COPY [[AND1]](s32)
; FP64: RetRA implicit $v0
%0:_(s32) = COPY $f12
@@ -544,8 +526,7 @@ body: |
; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
- ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP32: $v0 = COPY [[SELECT]](s32)
; FP32: RetRA implicit $v0
@@ -560,8 +541,7 @@ body: |
; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
- ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP64: $v0 = COPY [[SELECT]](s32)
; FP64: RetRA implicit $v0
@@ -590,12 +570,10 @@ body: |
; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
- ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
; FP32: $v0 = COPY [[AND1]](s32)
; FP32: RetRA implicit $v0
; FP64-LABEL: name: f64tou16
@@ -609,12 +587,10 @@ body: |
; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
- ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP64: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
; FP64: $v0 = COPY [[AND1]](s32)
; FP64: RetRA implicit $v0
%0:_(s64) = COPY $d6
@@ -643,12 +619,10 @@ body: |
; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
- ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
; FP32: $v0 = COPY [[AND1]](s32)
; FP32: RetRA implicit $v0
; FP64-LABEL: name: f64tou8
@@ -662,12 +636,10 @@ body: |
; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
- ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
+ ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP64: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
+ ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
; FP64: $v0 = COPY [[AND1]](s32)
; FP64: RetRA implicit $v0
%0:_(s64) = COPY $d6
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
index 7aafb9a3771e2..c7a7a10b3f921 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/icmp.mir
@@ -31,8 +31,7 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: $v0 = COPY [[COPY2]](s32)
+ ; MIPS32: $v0 = COPY [[ICMP]](s32)
; MIPS32: RetRA implicit $v0
%0:_(s32) = COPY $a0
%1:_(s32) = COPY $a1
@@ -55,8 +54,7 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]]
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: $v0 = COPY [[COPY2]](s32)
+ ; MIPS32: $v0 = COPY [[ICMP]](s32)
; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
@@ -79,13 +77,10 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
+ ; MIPS32: $v0 = COPY [[ICMP]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
@@ -109,16 +104,13 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
+ ; MIPS32: $v0 = COPY [[ICMP]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
@@ -149,8 +141,7 @@ body: |
; MIPS32: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY3]]
; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]]
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[OR]](s32), [[C]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
+ ; MIPS32: $v0 = COPY [[ICMP]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
@@ -183,8 +174,7 @@ body: |
; MIPS32: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[COPY3]]
; MIPS32: [[OR:%[0-9]+]]:_(s32) = G_OR [[XOR]], [[XOR1]]
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[OR]](s32), [[C]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
+ ; MIPS32: $v0 = COPY [[ICMP]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
@@ -215,14 +205,10 @@ body: |
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[COPY3]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
- ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
- ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; MIPS32: $v0 = COPY [[COPY7]](s32)
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
@@ -253,14 +239,10 @@ body: |
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY1]](s32), [[COPY3]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY2]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
- ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
- ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; MIPS32: $v0 = COPY [[COPY7]](s32)
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
@@ -291,14 +273,10 @@ body: |
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY1]](s32), [[COPY3]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
- ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
- ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; MIPS32: $v0 = COPY [[COPY7]](s32)
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
@@ -329,14 +307,10 @@ body: |
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[COPY1]](s32), [[COPY3]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY2]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
- ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
- ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; MIPS32: $v0 = COPY [[COPY7]](s32)
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
@@ -367,14 +341,10 @@ body: |
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY3]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
- ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
- ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; MIPS32: $v0 = COPY [[COPY7]](s32)
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
@@ -405,14 +375,10 @@ body: |
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY1]](s32), [[COPY3]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY2]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
- ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
- ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; MIPS32: $v0 = COPY [[COPY7]](s32)
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
@@ -443,14 +409,10 @@ body: |
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY1]](s32), [[COPY3]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
- ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
- ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; MIPS32: $v0 = COPY [[COPY7]](s32)
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
@@ -481,14 +443,10 @@ body: |
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY1]](s32), [[COPY3]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[COPY]](s32), [[COPY2]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
- ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY4]], [[COPY5]]
- ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; MIPS32: $v0 = COPY [[COPY7]](s32)
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%3:_(s32) = COPY $a1
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
index 71332f64b99a9..0c36cf6459b6d 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
@@ -84,8 +84,7 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY2]]
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C3]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.6
; MIPS32: bb.1.entry:
; MIPS32: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
@@ -109,17 +108,16 @@ body: |
; MIPS32: successors: %bb.13(0x40000000), %bb.8(0x40000000)
; MIPS32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C7]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY4]](s32), [[COPY5]]
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
+ ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY3]](s32), [[COPY4]]
; MIPS32: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C8]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C8]]
; MIPS32: G_BRCOND [[AND1]](s32), %bb.13
; MIPS32: bb.8.sw.epilog:
; MIPS32: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
; MIPS32: [[JUMP_TABLE1:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.1
- ; MIPS32: G_BRJT [[JUMP_TABLE1]](p0), %jump-table.1, [[COPY4]](s32)
+ ; MIPS32: G_BRJT [[JUMP_TABLE1]](p0), %jump-table.1, [[COPY3]](s32)
; MIPS32: bb.9.sw.bb4:
; MIPS32: $v0 = COPY [[C4]](s32)
; MIPS32: RetRA implicit $v0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
index f5a7a48e77004..cc2a43d33b289 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/mul.mir
@@ -49,12 +49,9 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
+ ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[MUL]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
@@ -80,12 +77,9 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
+ ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -110,11 +104,8 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
+ ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[MUL]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
@@ -138,12 +129,9 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
+ ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[MUL]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
@@ -169,12 +157,9 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
+ ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -199,11 +184,8 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
+ ; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[MUL]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
@@ -285,12 +267,10 @@ body: |
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL1]], [[MUL2]]
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL2]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[UMULH]]
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; MIPS32: [[MUL3:%[0-9]+]]:_(s32) = G_MUL [[LOAD2]], [[COPY]]
; MIPS32: [[MUL4:%[0-9]+]]:_(s32) = G_MUL [[LOAD1]], [[COPY1]]
@@ -299,27 +279,22 @@ body: |
; MIPS32: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[LOAD]], [[COPY1]]
; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL3]], [[MUL4]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[MUL4]]
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
- ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[C]]
; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[MUL5]]
; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[MUL5]]
- ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP3]](s32)
- ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
+ ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP3]], [[C]]
; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]]
; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[UMULH1]]
; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD6]](s32), [[UMULH1]]
- ; MIPS32: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ICMP4]](s32)
- ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
+ ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP4]], [[C]]
; MIPS32: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND4]]
; MIPS32: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[ADD6]], [[UMULH2]]
; MIPS32: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD8]](s32), [[UMULH2]]
- ; MIPS32: [[COPY9:%[0-9]+]]:_(s32) = COPY [[ICMP5]](s32)
- ; MIPS32: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C]]
+ ; MIPS32: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ICMP5]], [[C]]
; MIPS32: [[ADD9:%[0-9]+]]:_(s32) = G_ADD [[ADD7]], [[AND5]]
; MIPS32: [[ADD10:%[0-9]+]]:_(s32) = G_ADD [[ADD8]], [[ADD2]]
; MIPS32: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD10]](s32), [[ADD2]]
- ; MIPS32: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ICMP6]](s32)
- ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C]]
+ ; MIPS32: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ICMP6]], [[C]]
; MIPS32: [[ADD11:%[0-9]+]]:_(s32) = G_ADD [[ADD9]], [[AND6]]
; MIPS32: [[MUL6:%[0-9]+]]:_(s32) = G_MUL [[LOAD3]], [[COPY]]
; MIPS32: [[MUL7:%[0-9]+]]:_(s32) = G_MUL [[LOAD2]], [[COPY1]]
@@ -383,29 +358,24 @@ body: |
; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[MUL]], [[MUL1]]
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[MUL1]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
; MIPS32: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[UMULH]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD1]](s32), [[UMULH]]
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
; MIPS32: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; MIPS32: [[MUL2:%[0-9]+]]:_(s32) = G_MUL [[COPY3]], [[COPY1]]
; MIPS32: [[UMULH1:%[0-9]+]]:_(s32) = G_UMULH [[COPY3]], [[COPY]]
; MIPS32: [[UMULH2:%[0-9]+]]:_(s32) = G_UMULH [[COPY2]], [[COPY1]]
; MIPS32: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[MUL2]], [[UMULH1]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD3]](s32), [[UMULH1]]
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
- ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ICMP2]], [[C]]
; MIPS32: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[ADD3]], [[UMULH2]]
; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD4]](s32), [[UMULH2]]
- ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP3]](s32)
- ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
+ ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP3]], [[C]]
; MIPS32: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]]
; MIPS32: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[ADD4]], [[ADD2]]
; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD6]](s32), [[ADD2]]
- ; MIPS32: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ICMP4]](s32)
- ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
+ ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ICMP4]], [[C]]
; MIPS32: [[ADD7:%[0-9]+]]:_(s32) = G_ADD [[ADD5]], [[AND4]]
; MIPS32: [[UMULH3:%[0-9]+]]:_(s32) = G_UMULH [[COPY3]], [[COPY1]]
; MIPS32: [[ADD8:%[0-9]+]]:_(s32) = G_ADD [[UMULH3]], [[ADD7]]
@@ -444,8 +414,7 @@ body: |
; MIPS32: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]]
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C1]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C1]]
; MIPS32: G_STORE [[AND1]](s32), [[COPY3]](p0) :: (store (s8) into %ir.pcarry_flag)
; MIPS32: G_STORE [[MUL]](s32), [[COPY2]](p0) :: (store (s32) into %ir.pmul)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir
index 8ebe509ad3351..e5963d6fe4280 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/phi.mir
@@ -157,21 +157,17 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.cond.true:
; MIPS32: successors: %bb.3(0x80000000)
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: G_BR %bb.3
; MIPS32: bb.2.cond.false:
; MIPS32: successors: %bb.3(0x80000000)
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; MIPS32: bb.3.cond.end:
- ; MIPS32: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY4]](s32), %bb.1, [[COPY5]](s32), %bb.2
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[PHI]](s32)
- ; MIPS32: $v0 = COPY [[COPY6]](s32)
+ ; MIPS32: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2
+ ; MIPS32: $v0 = COPY [[PHI]](s32)
; MIPS32: RetRA implicit $v0
bb.1.entry:
liveins: $a0, $a1, $a2
@@ -210,21 +206,17 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.cond.true:
; MIPS32: successors: %bb.3(0x80000000)
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: G_BR %bb.3
; MIPS32: bb.2.cond.false:
; MIPS32: successors: %bb.3(0x80000000)
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; MIPS32: bb.3.cond.end:
- ; MIPS32: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY4]](s32), %bb.1, [[COPY5]](s32), %bb.2
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[PHI]](s32)
- ; MIPS32: $v0 = COPY [[COPY6]](s32)
+ ; MIPS32: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2
+ ; MIPS32: $v0 = COPY [[PHI]](s32)
; MIPS32: RetRA implicit $v0
bb.1.entry:
liveins: $a0, $a1, $a2
@@ -263,21 +255,17 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.cond.true:
; MIPS32: successors: %bb.3(0x80000000)
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: G_BR %bb.3
; MIPS32: bb.2.cond.false:
; MIPS32: successors: %bb.3(0x80000000)
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; MIPS32: bb.3.cond.end:
- ; MIPS32: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY4]](s32), %bb.1, [[COPY5]](s32), %bb.2
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[PHI]](s32)
- ; MIPS32: $v0 = COPY [[COPY6]](s32)
+ ; MIPS32: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2
+ ; MIPS32: $v0 = COPY [[PHI]](s32)
; MIPS32: RetRA implicit $v0
bb.1.entry:
liveins: $a0, $a1, $a2
@@ -316,8 +304,7 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.cond.true:
@@ -372,8 +359,7 @@ body: |
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.1)
; MIPS32: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.cond.true:
@@ -432,8 +418,7 @@ body: |
; MIPS32: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY1]](p0) :: (load (s64) from %ir.i64_ptr_a)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[COPY2]](p0) :: (load (s64) from %ir.i64_ptr_b)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.cond.true:
@@ -482,8 +467,7 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.cond.true:
@@ -532,8 +516,7 @@ body: |
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s32) from %ir.f32_ptr_a)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load (s32) from %ir.f32_ptr_b)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.cond.true:
@@ -585,8 +568,7 @@ body: |
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; MIPS32: G_BRCOND [[AND]](s32), %bb.1
; MIPS32: G_BR %bb.2
; MIPS32: bb.1.cond.true:
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir
index 7acfc9eb71f93..e72836424c44a 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/rem_and_div.mir
@@ -32,16 +32,13 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
- ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SDIV]], [[C]](s32)
; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR2]](s32)
; MIPS32: RetRA implicit $v0
@@ -67,16 +64,13 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
- ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SDIV]], [[C]](s32)
; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR2]](s32)
; MIPS32: RetRA implicit $v0
@@ -163,16 +157,13 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32)
- ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SREM]], [[C]](s32)
; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR2]](s32)
; MIPS32: RetRA implicit $v0
@@ -198,16 +189,13 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)
+ ; MIPS32: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; MIPS32: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
; MIPS32: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[ASHR]], [[ASHR1]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SREM]](s32)
- ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SREM]], [[C]](s32)
; MIPS32: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR2]](s32)
; MIPS32: RetRA implicit $v0
@@ -295,14 +283,11 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UDIV]], [[C1]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
@@ -329,14 +314,11 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UDIV]], [[C1]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
@@ -424,14 +406,11 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UREM]](s32)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UREM]], [[C1]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
@@ -458,14 +437,11 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[AND]], [[AND1]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UREM]](s32)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C1]](s32)
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[UREM]], [[C1]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir
index d67706c1c1f43..60b16cc1f3525 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/select.mir
@@ -25,14 +25,10 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
- ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY3]], [[COPY4]]
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; MIPS32: $v0 = COPY [[COPY6]](s32)
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $v0
%3:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %3(s32)
@@ -59,14 +55,10 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
- ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY3]], [[COPY4]]
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; MIPS32: $v0 = COPY [[COPY6]](s32)
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
+ ; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $v0
%3:_(s32) = COPY $a0
%0:_(s1) = G_TRUNC %3(s32)
@@ -94,8 +86,7 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $v0
@@ -122,8 +113,7 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
; MIPS32: $v0 = COPY [[SELECT]](p0)
; MIPS32: RetRA implicit $v0
@@ -152,11 +142,8 @@ body: |
; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY4]], [[COPY5]]
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C]]
+ ; MIPS32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ICMP]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY2]], [[COPY3]]
; MIPS32: $v0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $v0
@@ -195,8 +182,7 @@ body: |
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (load (s32) from %fixed-stack.1)
; MIPS32: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[MV]], [[MV1]]
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SELECT]](s64)
; MIPS32: $v0 = COPY [[UV]](s32)
@@ -233,8 +219,7 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
; MIPS32: $f0 = COPY [[SELECT]](s32)
; MIPS32: RetRA implicit $f0
@@ -264,8 +249,7 @@ body: |
; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; MIPS32: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
; MIPS32: $d0 = COPY [[SELECT]](s64)
; MIPS32: RetRA implicit $d0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir
index 2e049c4d3ea19..e81883473d88a 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sitofp_and_uitofp.mir
@@ -98,9 +98,8 @@ body: |
; FP32-LABEL: name: i16tof32
; FP32: liveins: $a0
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP32: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
; FP32: $f0 = COPY [[SITOFP]](s32)
@@ -108,9 +107,8 @@ body: |
; FP64-LABEL: name: i16tof32
; FP64: liveins: $a0
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP64: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
; FP64: $f0 = COPY [[SITOFP]](s32)
@@ -133,9 +131,8 @@ body: |
; FP32-LABEL: name: i8tof32
; FP32: liveins: $a0
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP32: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
; FP32: $f0 = COPY [[SITOFP]](s32)
@@ -143,9 +140,8 @@ body: |
; FP64-LABEL: name: i8tof32
; FP64: liveins: $a0
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP64: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
; FP64: $f0 = COPY [[SITOFP]](s32)
@@ -234,9 +230,8 @@ body: |
; FP32-LABEL: name: i16tof64
; FP32: liveins: $a0
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP32: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
; FP32: $d0 = COPY [[SITOFP]](s64)
@@ -244,9 +239,8 @@ body: |
; FP64-LABEL: name: i16tof64
; FP64: liveins: $a0
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP64: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
; FP64: $d0 = COPY [[SITOFP]](s64)
@@ -269,9 +263,8 @@ body: |
; FP32-LABEL: name: i8tof64
; FP32: liveins: $a0
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; FP32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; FP32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP32: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
; FP32: $d0 = COPY [[SITOFP]](s64)
@@ -279,9 +272,8 @@ body: |
; FP64-LABEL: name: i8tof64
; FP64: liveins: $a0
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
+ ; FP64: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; FP64: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; FP64: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
; FP64: $d0 = COPY [[SITOFP]](s64)
@@ -379,8 +371,7 @@ body: |
; FP32: liveins: $a0
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32)
; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
@@ -392,8 +383,7 @@ body: |
; FP64: liveins: $a0
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP64: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32)
; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
@@ -420,8 +410,7 @@ body: |
; FP32: liveins: $a0
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32)
; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
@@ -433,8 +422,7 @@ body: |
; FP64: liveins: $a0
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP64: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32)
; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
@@ -533,8 +521,7 @@ body: |
; FP32: liveins: $a0
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32)
; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
@@ -545,8 +532,7 @@ body: |
; FP64: liveins: $a0
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP64: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32)
; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
@@ -572,8 +558,7 @@ body: |
; FP32: liveins: $a0
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32)
; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
@@ -584,8 +569,7 @@ body: |
; FP64: liveins: $a0
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1127219200
; FP64: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[C1]](s32)
; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_split_because_of_memsize_or_align.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_split_because_of_memsize_or_align.mir
index fb5a53cc5c344..ea242cca1cbbe 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_split_because_of_memsize_or_align.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_split_because_of_memsize_or_align.mir
@@ -218,29 +218,27 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; MIPS32: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s32)
- ; MIPS32: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store (s8) into %ir.0)
+ ; MIPS32: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s8) into %ir.0)
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C2]](s32)
+ ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; MIPS32: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p0) :: (store (s8) into %ir.0 + 1)
; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C3]](s32)
+ ; MIPS32: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C3]](s32)
; MIPS32: G_STORE [[LSHR1]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 2)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store3align1
; MIPS32R6: liveins: $a0, $a1
; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
- ; MIPS32R6: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store (s16) into %ir.0, align 1)
+ ; MIPS32R6: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s16) into %ir.0, align 1)
; MIPS32R6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32R6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C1]](s32)
+ ; MIPS32R6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; MIPS32R6: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 2)
; MIPS32R6: RetRA
%0:_(p0) = COPY $a0
@@ -262,24 +260,22 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
- ; MIPS32: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store (s16) into %ir.0)
+ ; MIPS32: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s16) into %ir.0)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C1]](s32)
+ ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; MIPS32: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 2, align 2)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store3align2
; MIPS32R6: liveins: $a0, $a1
; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
- ; MIPS32R6: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store (s16) into %ir.0)
+ ; MIPS32R6: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s16) into %ir.0)
; MIPS32R6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32R6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C1]](s32)
+ ; MIPS32R6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; MIPS32R6: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 2, align 2)
; MIPS32R6: RetRA
%0:_(p0) = COPY $a0
@@ -301,24 +297,22 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
- ; MIPS32: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store (s16) into %ir.0, align 4)
+ ; MIPS32: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s16) into %ir.0, align 4)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C1]](s32)
+ ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; MIPS32: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 2, align 2, basealign 4)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store3align4
; MIPS32R6: liveins: $a0, $a1
; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
- ; MIPS32R6: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store (s16) into %ir.0, align 4)
+ ; MIPS32R6: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s16) into %ir.0, align 4)
; MIPS32R6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32R6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C1]](s32)
+ ; MIPS32R6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; MIPS32R6: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 2, align 2, basealign 4)
; MIPS32R6: RetRA
%0:_(p0) = COPY $a0
@@ -340,24 +334,22 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
- ; MIPS32: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store (s16) into %ir.0, align 8)
+ ; MIPS32: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s16) into %ir.0, align 8)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C1]](s32)
+ ; MIPS32: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; MIPS32: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 2, align 2, basealign 8)
; MIPS32: RetRA
; MIPS32R6-LABEL: name: store3align8
; MIPS32R6: liveins: $a0, $a1
; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32R6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
- ; MIPS32R6: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store (s16) into %ir.0, align 8)
+ ; MIPS32R6: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s16) into %ir.0, align 8)
; MIPS32R6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32R6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C1]](s32)
+ ; MIPS32R6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; MIPS32R6: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s8) into %ir.0 + 2, align 2, basealign 8)
; MIPS32R6: RetRA
%0:_(p0) = COPY $a0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
index e921f5c544039..98640cbfdea16 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/sub.mir
@@ -47,12 +47,9 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[SUB]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
@@ -78,12 +75,9 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -108,11 +102,8 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[SUB]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s8) = G_TRUNC %2(s32)
@@ -136,12 +127,9 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
- ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)
+ ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[SUB]], [[C]](s32)
; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
; MIPS32: $v0 = COPY [[ASHR]](s32)
; MIPS32: RetRA implicit $v0
@@ -167,12 +155,9 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
@@ -197,11 +182,8 @@ body: |
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
- ; MIPS32: $v0 = COPY [[COPY4]](s32)
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
+ ; MIPS32: $v0 = COPY [[SUB]](s32)
; MIPS32: RetRA implicit $v0
%2:_(s32) = COPY $a0
%0:_(s16) = G_TRUNC %2(s32)
@@ -231,8 +213,7 @@ body: |
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY3]](s32), [[COPY1]]
; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
; MIPS32: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]]
; MIPS32: $v0 = COPY [[SUB2]](s32)
; MIPS32: $v1 = COPY [[SUB]](s32)
@@ -281,30 +262,21 @@ body: |
; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD]](s32), [[COPY]]
; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[LOAD1]], [[COPY1]]
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP]], [[C]]
; MIPS32: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[AND]]
; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD1]](s32), [[COPY1]]
; MIPS32: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD1]](s32), [[COPY1]]
- ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
- ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
- ; MIPS32: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
- ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C]]
- ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[COPY5]], [[COPY6]]
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
+ ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND1]](s32), [[ICMP]], [[ICMP2]]
; MIPS32: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[LOAD2]], [[COPY2]]
- ; MIPS32: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C]]
+ ; MIPS32: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C]]
; MIPS32: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SUB3]], [[AND2]]
; MIPS32: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[LOAD2]](s32), [[COPY2]]
; MIPS32: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[LOAD2]](s32), [[COPY2]]
- ; MIPS32: [[COPY9:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
- ; MIPS32: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ICMP4]](s32)
- ; MIPS32: [[COPY11:%[0-9]+]]:_(s32) = COPY [[ICMP3]](s32)
- ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C]]
- ; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[COPY9]], [[COPY10]]
+ ; MIPS32: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ICMP3]], [[C]]
+ ; MIPS32: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[SELECT]], [[ICMP4]]
; MIPS32: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[LOAD3]], [[COPY3]]
- ; MIPS32: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
- ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C]]
+ ; MIPS32: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C]]
; MIPS32: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SUB5]], [[AND4]]
; MIPS32: $v0 = COPY [[SUB]](s32)
; MIPS32: $v1 = COPY [[SUB2]](s32)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir
index ed31997f0f34c..3b610859fb704 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/truncStore_and_aExtLoad.mir
@@ -64,8 +64,7 @@ body: |
; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s8) from %ir.py)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C]]
; MIPS32: G_STORE [[AND1]](s32), [[COPY]](p0) :: (store (s8) into %ir.px)
; MIPS32: RetRA
@@ -89,8 +88,7 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s8) from %ir.py)
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; MIPS32: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store (s8) into %ir.px)
+ ; MIPS32: G_STORE [[LOAD]](s32), [[COPY]](p0) :: (store (s8) into %ir.px)
; MIPS32: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
@@ -112,8 +110,7 @@ body: |
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s16) from %ir.py)
- ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
- ; MIPS32: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store (s16) into %ir.px)
+ ; MIPS32: G_STORE [[LOAD]](s32), [[COPY]](p0) :: (store (s16) into %ir.px)
; MIPS32: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
index fbc8c4115d0f2..30a7e1a85d35b 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
+++ b/llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
@@ -66,8 +66,7 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32)
- ; MIPS32: $v0 = COPY [[COPY1]](s32)
+ ; MIPS32: $v0 = COPY [[ZEXTLOAD]](s32)
; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0
%2:_(s16) = G_ZEXTLOAD %0(p0) :: (load (s8) from %ir.px)
@@ -172,8 +171,7 @@ body: |
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.px)
- ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SEXTLOAD]](s32)
- ; MIPS32: $v0 = COPY [[COPY1]](s32)
+ ; MIPS32: $v0 = COPY [[SEXTLOAD]](s32)
; MIPS32: RetRA implicit $v0
%0:_(p0) = COPY $a0
%2:_(s16) = G_SEXTLOAD %0(p0) :: (load (s8) from %ir.px)
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll
index 803b76cbc51ab..26816482306a9 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll
@@ -307,7 +307,6 @@ define i16 @shl_i16(i16 %a) {
; MIPS32-LABEL: shl_i16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $1, $zero, 2
-; MIPS32-NEXT: andi $1, $1, 65535
; MIPS32-NEXT: sllv $2, $4, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@@ -319,8 +318,7 @@ entry:
define i8 @ashr_i8(i8 %a) {
; MIPS32-LABEL: ashr_i8:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: ori $1, $zero, 2
-; MIPS32-NEXT: andi $2, $1, 255
+; MIPS32-NEXT: ori $2, $zero, 2
; MIPS32-NEXT: sll $1, $4, 24
; MIPS32-NEXT: sra $1, $1, 24
; MIPS32-NEXT: srav $2, $1, $2
@@ -334,8 +332,7 @@ entry:
define i16 @lshr_i16(i16 %a) {
; MIPS32-LABEL: lshr_i16:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: ori $1, $zero, 2
-; MIPS32-NEXT: andi $2, $1, 65535
+; MIPS32-NEXT: ori $2, $zero, 2
; MIPS32-NEXT: andi $1, $4, 65535
; MIPS32-NEXT: srlv $2, $1, $2
; MIPS32-NEXT: jr $ra
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll
index 0187b72780d7f..1bd65a4196087 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll
@@ -25,9 +25,7 @@ entry:
define signext i16 @signed_i16() {
; MIPS32-LABEL: signed_i16:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $1, $zero, 32768
-; MIPS32-NEXT: sll $1, $1, 16
-; MIPS32-NEXT: sra $2, $1, 16
+; MIPS32-NEXT: addiu $2, $zero, 32768
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@@ -37,9 +35,7 @@ entry:
define signext i8 @signed_i8() {
; MIPS32-LABEL: signed_i8:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $1, $zero, 65408
-; MIPS32-NEXT: sll $1, $1, 24
-; MIPS32-NEXT: sra $2, $1, 24
+; MIPS32-NEXT: addiu $2, $zero, 65408
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@@ -49,8 +45,7 @@ entry:
define zeroext i16 @unsigned_i16() {
; MIPS32-LABEL: unsigned_i16:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $1, $zero, 32768
-; MIPS32-NEXT: andi $2, $1, 65535
+; MIPS32-NEXT: ori $2, $zero, 32768
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@@ -60,8 +55,7 @@ entry:
define zeroext i8 @unsigned_i8() {
; MIPS32-LABEL: unsigned_i8:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $1, $zero, 65408
-; MIPS32-NEXT: andi $2, $1, 255
+; MIPS32-NEXT: ori $2, $zero, 128
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@@ -71,8 +65,7 @@ entry:
define zeroext i1 @i1_true() {
; MIPS32-LABEL: i1_true:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: ori $1, $zero, 1
-; MIPS32-NEXT: andi $2, $1, 1
+; MIPS32-NEXT: ori $2, $zero, 1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@@ -82,8 +75,7 @@ entry:
define zeroext i1 @i1_false() {
; MIPS32-LABEL: i1_false:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: ori $1, $zero, 0
-; MIPS32-NEXT: andi $2, $1, 1
+; MIPS32-NEXT: ori $2, $zero, 0
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll
index c292dba16ce36..7cc62e272ccc4 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll
@@ -57,9 +57,8 @@ define i32 @select_with_negation(i32 %a, i32 %b, i32 %x, i32 %y) {
; MIPS32-LABEL: select_with_negation:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $2, $7
-; MIPS32-NEXT: ori $3, $zero, 1
; MIPS32-NEXT: slt $1, $4, $5
-; MIPS32-NEXT: xor $1, $1, $3
+; MIPS32-NEXT: xori $1, $1, 1
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: movn $2, $6, $1
; MIPS32-NEXT: jr $ra
diff --git a/llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll b/llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll
index 849cf0d4ce4cf..fd096365f0880 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll
@@ -165,11 +165,9 @@ define i1 @test_ashr_i1_imm1(i32 %arg1) {
; X64-LABEL: test_ashr_i1_imm1:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: movb $1, %cl
; X64-NEXT: shlb $7, %al
; X64-NEXT: sarb $7, %al
-; X64-NEXT: andb $1, %cl
-; X64-NEXT: sarb %cl, %al
+; X64-NEXT: sarb %al
; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
%a = trunc i32 %arg1 to i1
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir
index 71d63ffec178a..2f5af5e0951b4 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir
@@ -16,8 +16,7 @@ body: |
; X32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32))
; X32: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load (p0))
; X32: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
- ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY [[LOAD]](s8)
- ; X32: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY]], [[C]]
+ ; X32: [[AND:%[0-9]+]]:_(s8) = G_AND [[LOAD]], [[C]]
; X32: G_STORE [[AND]](s8), [[DEF]](p0) :: (store (s1))
; X32: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store (s8))
; X32: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store (s16))
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir
index 05a6eaea2df7c..1eb082a074514 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir
@@ -16,8 +16,7 @@ body: |
; X64: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load (s32))
; X64: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load (p0))
; X64: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
- ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY [[LOAD]](s8)
- ; X64: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY]], [[C]]
+ ; X64: [[AND:%[0-9]+]]:_(s8) = G_AND [[LOAD]], [[C]]
; X64: G_STORE [[AND]](s8), [[DEF]](p0) :: (store (s1))
; X64: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store (s8))
; X64: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store (s16))
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir
index c82c40dfef1df..1e13f6d3577ea 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir
@@ -39,8 +39,7 @@ body: |
; CHECK: [[MUL:%[0-9]+]]:_(s8) = G_MUL [[TRUNC]], [[TRUNC1]]
; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
- ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[MUL]](s8)
- ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[MUL]], [[C]]
; CHECK: G_STORE [[AND]](s8), [[DEF]](p0) :: (store (s1))
; CHECK: RET 0
%0(s32) = COPY $edx
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir
index fe432f72ec768..d51e032aef18f 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir
@@ -47,8 +47,7 @@ body: |
; CHECK: [[OR:%[0-9]+]]:_(s8) = G_OR [[TRUNC]], [[TRUNC1]]
; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
- ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[OR]](s8)
- ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[OR]], [[C]]
; CHECK: G_STORE [[AND]](s8), [[DEF]](p0) :: (store (s1))
; CHECK: RET 0
%0(s32) = COPY $edx
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir
index e588f156be08d..6f0346d4aaccd 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir
@@ -158,8 +158,7 @@ body: |
; ALL: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
; ALL: bb.2.cond.end:
; ALL: [[PHI:%[0-9]+]]:_(s8) = G_PHI [[TRUNC2]](s8), %bb.1, [[TRUNC1]](s8), %bb.0
- ; ALL: [[COPY3:%[0-9]+]]:_(s8) = COPY [[PHI]](s8)
- ; ALL: $al = COPY [[COPY3]](s8)
+ ; ALL: $al = COPY [[PHI]](s8)
; ALL: RET 0, implicit $al
bb.1.entry:
successors: %bb.3(0x40000000), %bb.2(0x40000000)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir
index 958f2061c7d81..41c50da3615e7 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir
@@ -30,8 +30,7 @@ body: |
; CHECK: [[SUB:%[0-9]+]]:_(s8) = G_SUB [[TRUNC]], [[TRUNC1]]
; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
- ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[SUB]](s8)
- ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[SUB]], [[C]]
; CHECK: G_STORE [[AND]](s8), [[DEF]](p0) :: (store (s1))
; CHECK: RET 0
%0(s32) = COPY $edx
diff --git a/llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll b/llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll
index 5dd53751247f7..8a6215e07ebf6 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll
@@ -164,10 +164,8 @@ define i1 @test_lshr_i1_imm1(i32 %arg1) {
; X64-LABEL: test_lshr_i1_imm1:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: movb $1, %cl
; X64-NEXT: andb $1, %al
-; X64-NEXT: andb $1, %cl
-; X64-NEXT: shrb %cl, %al
+; X64-NEXT: shrb %al
; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
%a = trunc i32 %arg1 to i1
diff --git a/llvm/test/CodeGen/X86/GlobalISel/shl-scalar.ll b/llvm/test/CodeGen/X86/GlobalISel/shl-scalar.ll
index 5ccc0eee59512..c298ed6d106c7 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/shl-scalar.ll
+++ b/llvm/test/CodeGen/X86/GlobalISel/shl-scalar.ll
@@ -161,10 +161,8 @@ define i1 @test_shl_i1(i32 %arg1, i32 %arg2) {
define i1 @test_shl_i1_imm1(i32 %arg1) {
; X64-LABEL: test_shl_i1_imm1:
; X64: # %bb.0:
-; X64-NEXT: movl %edi, %eax
-; X64-NEXT: movb $1, %cl
-; X64-NEXT: andb $1, %cl
-; X64-NEXT: shlb %cl, %al
+; X64-NEXT: # kill: def $edi killed $edi def $rdi
+; X64-NEXT: leal (%rdi,%rdi), %eax
; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
%a = trunc i32 %arg1 to i1
diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fcmp.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fcmp.mir
index 4eabd9a4c1ef1..f2f4037434d41 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fcmp.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fcmp.mir
@@ -166,8 +166,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(oeq), [[TRUNC]](s32), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s32) = G_TRUNC %2(s128)
@@ -201,8 +200,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(ogt), [[TRUNC]](s32), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s32) = G_TRUNC %2(s128)
@@ -236,8 +234,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(oge), [[TRUNC]](s32), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s32) = G_TRUNC %2(s128)
@@ -271,8 +268,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(olt), [[TRUNC]](s32), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s32) = G_TRUNC %2(s128)
@@ -306,8 +302,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(ole), [[TRUNC]](s32), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s32) = G_TRUNC %2(s128)
@@ -341,8 +336,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(one), [[TRUNC]](s32), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s32) = G_TRUNC %2(s128)
@@ -376,8 +370,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(ord), [[TRUNC]](s32), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s32) = G_TRUNC %2(s128)
@@ -411,8 +404,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(uno), [[TRUNC]](s32), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s32) = G_TRUNC %2(s128)
@@ -446,8 +438,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(ueq), [[TRUNC]](s32), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s32) = G_TRUNC %2(s128)
@@ -481,8 +472,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(ugt), [[TRUNC]](s32), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s32) = G_TRUNC %2(s128)
@@ -516,8 +506,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(uge), [[TRUNC]](s32), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s32) = G_TRUNC %2(s128)
@@ -551,8 +540,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(ult), [[TRUNC]](s32), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s32) = G_TRUNC %2(s128)
@@ -586,8 +574,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(ule), [[TRUNC]](s32), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s32) = G_TRUNC %2(s128)
@@ -621,8 +608,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(une), [[TRUNC]](s32), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s32) = G_TRUNC %2(s128)
@@ -656,8 +642,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(oeq), [[TRUNC]](s64), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s64) = G_TRUNC %2(s128)
@@ -691,8 +676,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(ogt), [[TRUNC]](s64), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s64) = G_TRUNC %2(s128)
@@ -726,8 +710,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(oge), [[TRUNC]](s64), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s64) = G_TRUNC %2(s128)
@@ -761,8 +744,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(olt), [[TRUNC]](s64), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s64) = G_TRUNC %2(s128)
@@ -796,8 +778,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(ole), [[TRUNC]](s64), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s64) = G_TRUNC %2(s128)
@@ -831,8 +812,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(one), [[TRUNC]](s64), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s64) = G_TRUNC %2(s128)
@@ -866,8 +846,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(ord), [[TRUNC]](s64), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s64) = G_TRUNC %2(s128)
@@ -901,8 +880,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(uno), [[TRUNC]](s64), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s64) = G_TRUNC %2(s128)
@@ -936,8 +914,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(ueq), [[TRUNC]](s64), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s64) = G_TRUNC %2(s128)
@@ -971,8 +948,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(ugt), [[TRUNC]](s64), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s64) = G_TRUNC %2(s128)
@@ -1006,8 +982,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(uge), [[TRUNC]](s64), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s64) = G_TRUNC %2(s128)
@@ -1041,8 +1016,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(ult), [[TRUNC]](s64), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s64) = G_TRUNC %2(s128)
@@ -1076,8 +1050,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(ule), [[TRUNC]](s64), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s64) = G_TRUNC %2(s128)
@@ -1111,8 +1084,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm1
; CHECK: [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
; CHECK: [[FCMP:%[0-9]+]]:_(s8) = G_FCMP floatpred(une), [[TRUNC]](s64), [[TRUNC1]]
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[FCMP]](s8)
- ; CHECK: $al = COPY [[COPY2]](s8)
+ ; CHECK: $al = COPY [[FCMP]](s8)
; CHECK: RET 0, implicit $al
%2:_(s128) = COPY $xmm0
%0:_(s64) = G_TRUNC %2(s128)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir
index af61a75b5a6a7..64e569cac7602 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir
@@ -88,11 +88,10 @@ body: |
; CHECK-LABEL: name: int8_to_float
; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 24
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s8)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[C]](s8)
- ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY2]](s8)
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s8)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[C]](s8)
+ ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY1]](s8)
; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32)
; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
@@ -121,11 +120,10 @@ body: |
; CHECK-LABEL: name: int16_to_float
; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 16
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s8)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[C]](s8)
- ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY2]](s8)
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s8)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[C]](s8)
+ ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY1]](s8)
; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[ASHR]](s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s32)
; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
@@ -206,11 +204,10 @@ body: |
; CHECK-LABEL: name: int8_to_double
; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 24
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s8)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[C]](s8)
- ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY2]](s8)
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s8)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[C]](s8)
+ ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY1]](s8)
; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s64)
; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
@@ -239,11 +236,10 @@ body: |
; CHECK-LABEL: name: int16_to_double
; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 16
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s8)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s8) = COPY [[C]](s8)
- ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY2]](s8)
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s8)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[C]](s8)
+ ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[COPY1]](s8)
; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[ASHR]](s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[SITOFP]](s64)
; CHECK: $xmm0 = COPY [[ANYEXT]](s128)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir
index 0795539e7c16e..b071c29e0d197 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir
@@ -124,8 +124,7 @@ body: |
; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: $eax = COPY [[AND]](s32)
; CHECK: RET 0, implicit $eax
%1:_(s32) = COPY $edi
@@ -205,8 +204,7 @@ body: |
; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: $eax = COPY [[AND]](s32)
; CHECK: RET 0, implicit $eax
%1:_(s32) = COPY $edi
@@ -259,8 +257,7 @@ body: |
; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: $eax = COPY [[AND]](s32)
; CHECK: RET 0, implicit $eax
%1:_(s32) = COPY $edi
diff --git a/llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp b/llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
index b759b5fecd645..594f0c75b2490 100644
--- a/llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp
@@ -78,9 +78,7 @@ TEST_F(AArch64GISelMITest, BasicLegalizerTest) {
CHECK-NEXT: [[OFFSET_1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
CHECK-NEXT: [[VPTR_1:%[0-9]+]]:_(p0) = G_PTR_ADD %vptr:_, [[OFFSET_1]]:_(s64)
CHECK-NEXT: [[LOAD_1:%[0-9]+]]:_(s16) = G_LOAD [[VPTR_1]]:_(p0) :: (load (s8) from unknown-address + 1)
- CHECK-NEXT: [[V0:%[0-9]+]]:_(s16) = COPY [[LOAD_0]]:_(s16)
- CHECK-NEXT: [[V1:%[0-9]+]]:_(s16) = COPY [[LOAD_1]]:_(s16)
- CHECK-NEXT: %v:_(<2 x s8>) = G_BUILD_VECTOR_TRUNC [[V0]]:_(s16), [[V1]]:_(s16)
+ CHECK-NEXT: %v:_(<2 x s8>) = G_BUILD_VECTOR_TRUNC [[LOAD_0]]:_(s16), [[LOAD_1]]:_(s16)
CHECK-NEXT: $h4 = COPY %v:_(<2 x s8>)
)";
@@ -168,8 +166,7 @@ TEST_F(AArch64GISelMITest, UnorderedArtifactCombiningTest) {
StringRef CheckString = R"(
CHECK: %vptr:_(p0) = COPY $x4
CHECK-NEXT: [[LOAD_0:%[0-9]+]]:_(s16) = G_LOAD %vptr:_(p0) :: (load (s8))
- CHECK: %v0_ext:_(s16) = COPY [[LOAD_0]]:_(s16)
- CHECK-NEXT: $h4 = COPY %v0_ext:_(s16)
+ CHECK: $h4 = COPY [[LOAD_0]]:_(s16)
)";
EXPECT_TRUE(CheckMachineFunction(*MF, CheckString)) << *MF;
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