[llvm] 280a0b7 - [Test][AggressiveInstCombine] Modify shift tests

[Anton Afanasyev via llvm-commits]

Author: Anton Afanasyev
Date: 2021-08-24T10:30:27+03:00
New Revision: 280a0b735fced163c41d119a5d67e4b77c38aa19

URL: https://github.com/llvm/llvm-project/commit/280a0b735fced163c41d119a5d67e4b77c38aa19
DIFF: https://github.com/llvm/llvm-project/commit/280a0b735fced163c41d119a5d67e4b77c38aa19.diff

LOG: [Test][AggressiveInstCombine] Modify shift tests

Add `sext` for `ashr`, remove unrelated tests

Added: 
    

Modified: 
    llvm/test/Transforms/AggressiveInstCombine/trunc_ashr.ll
    llvm/test/Transforms/AggressiveInstCombine/trunc_lshr.ll

Removed: 
    


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diff  --git a/llvm/test/Transforms/AggressiveInstCombine/trunc_ashr.ll b/llvm/test/Transforms/AggressiveInstCombine/trunc_ashr.ll
index af9e608e70625..57f807e677353 100644
--- a/llvm/test/Transforms/AggressiveInstCombine/trunc_ashr.ll
+++ b/llvm/test/Transforms/AggressiveInstCombine/trunc_ashr.ll
@@ -1,8 +1,11 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -aggressive-instcombine -S | FileCheck %s
 
-define i16 @ashr_15(i16 %x) {
-; CHECK-LABEL: @ashr_15(
+; Negative test - could be folded if preceding InstCombine
+; transforms `ashr` to `lshr`
+
+define i16 @ashr_15_zext(i16 %x) {
+; CHECK-LABEL: @ashr_15_zext(
 ; CHECK-NEXT:    [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
 ; CHECK-NEXT:    [[ASHR:%.*]] = ashr i32 [[ZEXT]], 15
 ; CHECK-NEXT:    [[TRUNC:%.*]] = trunc i32 [[ASHR]] to i16
@@ -14,10 +17,23 @@ define i16 @ashr_15(i16 %x) {
   ret i16 %trunc
 }
 
+define i16 @ashr_sext_15(i16 %x) {
+; CHECK-LABEL: @ashr_sext_15(
+; CHECK-NEXT:    [[SEXT:%.*]] = sext i16 [[X:%.*]] to i32
+; CHECK-NEXT:    [[ASHR:%.*]] = ashr i32 [[SEXT]], 15
+; CHECK-NEXT:    [[TRUNC:%.*]] = trunc i32 [[ASHR]] to i16
+; CHECK-NEXT:    ret i16 [[TRUNC]]
+;
+  %sext = sext i16 %x to i32
+  %ashr = ashr i32 %sext, 15
+  %trunc = trunc i32 %ashr to i16
+  ret i16 %trunc
+}
+
 ; Negative test
 
-define i16 @ashr_16(i16 %x) {
-; CHECK-LABEL: @ashr_16(
+define i16 @ashr_sext_16(i16 %x) {
+; CHECK-LABEL: @ashr_sext_16(
 ; CHECK-NEXT:    [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
 ; CHECK-NEXT:    [[ASHR:%.*]] = ashr i32 [[ZEXT]], 16
 ; CHECK-NEXT:    [[TRUNC:%.*]] = trunc i32 [[ASHR]] to i16

diff  --git a/llvm/test/Transforms/AggressiveInstCombine/trunc_lshr.ll b/llvm/test/Transforms/AggressiveInstCombine/trunc_lshr.ll
index 4a05891d1fd28..157b538d420be 100644
--- a/llvm/test/Transforms/AggressiveInstCombine/trunc_lshr.ll
+++ b/llvm/test/Transforms/AggressiveInstCombine/trunc_lshr.ll
@@ -218,23 +218,6 @@ define i16 @lshr_negative_operand(i16 %x) {
   ret i16 %trunc
 }
 
-define i16 @lshr_negative_operand_but_short(i16 %x) {
-; CHECK-LABEL: @lshr_negative_operand_but_short(
-; CHECK-NEXT:    [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
-; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ZEXT]], 32767
-; CHECK-NEXT:    [[XOR:%.*]] = xor i32 -1, [[AND]]
-; CHECK-NEXT:    [[LSHR2:%.*]] = lshr i32 [[XOR]], 2
-; CHECK-NEXT:    [[TRUNC:%.*]] = trunc i32 [[LSHR2]] to i16
-; CHECK-NEXT:    ret i16 [[TRUNC]]
-;
-  %zext = zext i16 %x to i32
-  %and = and i32 %zext, 32767
-  %xor = xor i32 -1, %and
-  %lshr2 = lshr i32 %xor, 2
-  %trunc = trunc i32 %lshr2 to i16
-  ret i16 %trunc
-}
-
 ; We may encounter unoptimized IR as below,
 ; so don't crash by assuming that we can
 ; apply instruction flags (exact) if there