[PATCH] D108578: RegAllocGreedy: Account for reserved registers in num regs heuristic

Dave Green via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Aug 24 00:10:37 PDT 2021


dmgreen added a comment.

> The worst looking regression is likely test/Thumb2/mve-vld4.ll

We likely get the register pressure very wrong, and it looks like less code in total. I have no objections to this patch from an Arm point of view.

Arm MVE has 32 scalar FP `S` regs, 4 (aligned) of which make up the 8 vector `Q` regs (so `q0=s0-s1-s2-s3`, `q1=s4-s5-s6-s7` etc).
4 potentially unaligned `Q` registers make up a `QQQQPR` reg (`q0-q1-q2-q3`, `q1-q2-q3-q4`, `q2-q3-q4-q5`, `q3-q4-q5-q6` and `q4-q5-q6-q7`)
So we have "5" QQQQPR registers, only 2 of which are actually allocatable at once.

> Additionally, I think it would be more appropriate to use the number of disjointly allocatable registers in the class. For the AMDGPU register tuples, there are a large number of registers in each tuple class, but only a small fraction can actually be allocated at the same time since they all overlap with each other. It seems we do not have a query that corresponds to the number of independently allocatable registers.

That sounds very useful.


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