[PATCH] D108607: [RISCV] Optimize (add (mul x, c0), c1)

[Ben Shi via Phabricator via llvm-commits]

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Optimize (add (mul x, c0), c1) -> (ADDI (MUL (ADDI, c1/c0), c0), c1%c0),
if c1/c0 and c1%c0 are simm12, while c1 is not.

Or Optimize (add (mul x, c0), c1) -> (MUL (ADDI, c1/c0), c0),
if c1%c0 is zero, and c1/c0 is simm12 while c1 is not.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108607

Files:
  llvm/test/CodeGen/RISCV/addimm-mulimm.ll

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