[PATCH] D108602: [RISCV] Initial support .insn directive for the assembler.

[Craig Topper via Phabricator via llvm-commits]

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This allows for a custom encoding to be emitted. It can also be
used with inline assembly to allow the custom instruction to be
register allocated like other instructions.

I initially started from SystemZ's implementation, but some of
the formats allow operands to be specified in multiple ways so I
had to add support for matching different operand class lists for
the same format. That implementation is a simplified version of
what is emitted by tablegen for regular instructions.

I've left out the compressed formats. And I haven't supported the
named opcodes like LUI or OP_IMM_32. Those can be added in future
patches.

Documentation can be found here https://sourceware.org/binutils/docs-2.34/as/RISC_002dV_002dFormats.html


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108602

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
  llvm/test/MC/RISCV/insn-invalid.s
  llvm/test/MC/RISCV/insn.s

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