[PATCH] D108598: [ARC] Add codegen for the readcyclecounter intrinsic along with disassembly for associated instructions

[Thomas Johnson via Phabricator via llvm-commits]

thomasjohns added inline comments.


================
Comment at: llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp:322
+  DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder);
+  using Field = decltype(Insn);
+  Field Lower = fieldFromInstruction(Insn, 6, 6);
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This aims to decode either form:
`...ssssssSSSSSS`
or
`...uuuuuu000000`
(S12 or U6). I assumed the leading bit of the S12 marks the sign. Is this correct @marksl ?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108598/new/

https://reviews.llvm.org/D108598