[llvm] a2c8e17 - [AArch64][GlobalISel] Add regbankselect support for G_LLROUND

[Jessica Paquette via llvm-commits]

Author: Jessica Paquette
Date: 2021-08-23T10:32:20-07:00
New Revision: a2c8e176580867bec9897761079343451d0f6287

URL: https://github.com/llvm/llvm-project/commit/a2c8e176580867bec9897761079343451d0f6287
DIFF: https://github.com/llvm/llvm-project/commit/a2c8e176580867bec9897761079343451d0f6287.diff

LOG: [AArch64][GlobalISel] Add regbankselect support for G_LLROUND

Same as G_LROUND: destination should always be a GPR, source should always be
a FPR.

Differential Revision: https://reviews.llvm.org/D108566

Added: 
    llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index 78c9e17dadc2..ffe64c56d419 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -532,6 +532,7 @@ bool AArch64RegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
   case TargetOpcode::G_FPTOUI:
   case TargetOpcode::G_FCMP:
   case TargetOpcode::G_LROUND:
+  case TargetOpcode::G_LLROUND:
     return true;
   default:
     break;
@@ -960,7 +961,8 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     }
     break;
   }
-  case TargetOpcode::G_LROUND: {
+  case TargetOpcode::G_LROUND:
+  case TargetOpcode::G_LLROUND: {
     // Source is always floating point and destination is always integer.
     OpRegBankIdx = {PMI_FirstGPR, PMI_FirstFPR};
     break;

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir
new file mode 100644
index 000000000000..af9f74914f55
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-llround.mir
@@ -0,0 +1,65 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+
+...
+---
+name:            no_cross_bank_copies_needed
+legalized:       true
+regBankSelected: false
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $d0
+    ; CHECK-LABEL: name: no_cross_bank_copies_needed
+    ; CHECK: liveins: $d0
+    ; CHECK: %fpr:fpr(s64) = COPY $d0
+    ; CHECK: %llround:gpr(s64) = G_LLROUND %fpr(s64)
+    ; CHECK: $d0 = COPY %llround(s64)
+    ; CHECK: RET_ReallyLR implicit $s0
+    %fpr:_(s64) = COPY $d0
+    %llround:_(s64) = G_LLROUND %fpr
+    $d0 = COPY %llround:_(s64)
+    RET_ReallyLR implicit $s0
+...
+---
+name:            source_needs_copy
+legalized:       true
+regBankSelected: false
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x0
+    ; CHECK-LABEL: name: source_needs_copy
+    ; CHECK: liveins: $x0
+    ; CHECK: %gpr:gpr(s64) = COPY $x0
+    ; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY %gpr(s64)
+    ; CHECK: %llround:gpr(s64) = G_LLROUND [[COPY]](s64)
+    ; CHECK: $d0 = COPY %llround(s64)
+    ; CHECK: RET_ReallyLR implicit $s0
+    %gpr:_(s64) = COPY $x0
+    %llround:_(s64) = G_LLROUND %gpr
+    $d0 = COPY %llround:_(s64)
+    RET_ReallyLR implicit $s0
+...
+---
+name:            load_gets_fpr
+legalized:       true
+regBankSelected: false
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $x0
+    ; CHECK-LABEL: name: load_gets_fpr
+    ; CHECK: liveins: $x0
+    ; CHECK: %ptr:gpr(p0) = COPY $x0
+    ; CHECK: %load:fpr(s32) = G_LOAD %ptr(p0) :: (load (s32))
+    ; CHECK: %llround:gpr(s64) = G_LLROUND %load(s32)
+    ; CHECK: $d0 = COPY %llround(s64)
+    ; CHECK: RET_ReallyLR implicit $s0
+    %ptr:_(p0) = COPY $x0
+    %load:_(s32) = G_LOAD %ptr(p0) :: (load (s32))
+    %llround:_(s64) = G_LLROUND %load
+    $d0 = COPY %llround:_(s64)
+    RET_ReallyLR implicit $s0
+
+...