[PATCH] D106079: [AMDGPU] Divergence-driven compare operations instruction selection

[Alexander via Phabricator via llvm-commits]

alex-t added a comment.

Following the discussion regarding uniform "setcc" with a divergent use:
In the current implementation of the divergence-driven ISel node is selected only depending on the divergence bit value regardless of VALU or SALU uses.
The latter is not necessarily related to the user divergence. The user may be uniform but selected to VALU just because corresponding SALU instruction does not exist.
As mentioned above, the alternative approach is to select the given node to VALU if it has VALU users. At first, this requires some reasonable heuristic. 
Let's say we have a uniform SDNode that has 1 VALU but 10 SALU users. Is it profitable to select it to VALU? 
The selection hook that looks ahead for the users needs to be controlled by the option to try different heuristics.
Also, the problem in question is common for all the opcodes - not the "setcc" only. Thus, adding such a hook would require changing all the places in the target where the divergence bit is currently checked. That is why I insist this should go to a separate patch.

For the current one, I checked the possible regression related to the "select" pattern by running the OpenCL conformance math_bruteforce with the clean and changed compiler. The timing shows that the new one is on par with the old one.


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https://reviews.llvm.org/D106079