[PATCH] D107677: Prevent machine licm if remattable with a vreg use

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

In D107677#2941702 <https://reviews.llvm.org/D107677#2941702>, @rampitec wrote:

> In D107677#2941270 <https://reviews.llvm.org/D107677#2941270>, @dmgreen wrote:
>
>> And now has a bad day:
>
>     LE       lr,#innerloop
>   ...
>     VCTP lr
>
> Is that after this patch or after D106408 <https://reviews.llvm.org/D106408>? It looks more like rematerialization and not hoisting.

Oh I meant

    VCTP r0
  outerloop:

It's hoisting out of the outer loop. I don't consider the regressions to be the fault of this patch though.

If there are no other comments, LGTM



================
Comment at: llvm/lib/CodeGen/MachineLICM.cpp:668
+/// rematerialize it in this scenario. In that case we do not want to hoist such
+/// instruction out of the loop in a believe RA will sink it back if needed.
+bool MachineLICMBase::isTriviallyReMaterializable(const MachineInstr &MI,
----------------
believe -> belief


================
Comment at: llvm/lib/CodeGen/MachineLICM.cpp:1179
 
   // Rematerializable instructions should always be hoisted since the register
   // allocator can just pull them down again when needed.
----------------
since the register allocator -> providing the register allocator


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107677/new/

https://reviews.llvm.org/D107677