[PATCH] D108139: [X86] Freeze vXi8 shl(x,1) -> add(x,x) vector fold (PR50468)

Sun Aug 22 18:49:35 PDT 2021

pengfei added inline comments.

================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:28729

-    // Simple i8 add case
-    if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
+    // Simple i8 add case (freeze to handle add(undef, undef) case).
+    if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1) {
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craig.topper wrote:
> pengfei wrote:
> > Sorry, I don't quite understand the background. My question is why don't we check the oprand is a undef?
> > The affected tests seem all reasonable values, though they seem not have regressions.
> It’s not enough to check for undef at the time of the fold. You need to know that no future DAGCombine can make the input undef.
> 
> (shl X, 1) must produce an even number even if X is undef. computeKnownBits will look at the shift amount and tell downstream code that the lsb is 0 without looking at the left hand side. And the value may not be undef at the time computeKnownBits is called but could be simplified to undef later.
> 
> (add undef, undef) does not produce an even number. Register allocation is free to pick different registers for undef.
> 
> The freeze forces register allocation to use the same register.
> 
> 
Nice answer! I'm clear now. Thanks Craig.

Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108139/new/

https://reviews.llvm.org/D108139