[llvm] 7e91c59 - [AArch64][GlobalISel] Legalize 32-bit + narrow G_SMULO + G_UMULO
Jessica Paquette via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 20 14:41:07 PDT 2021
Author: Jessica Paquette
Date: 2021-08-20T14:37:46-07:00
New Revision: 7e91c59844a389c70040c36a9afad15fcb48dfd2
URL: https://github.com/llvm/llvm-project/commit/7e91c59844a389c70040c36a9afad15fcb48dfd2
DIFF: https://github.com/llvm/llvm-project/commit/7e91c59844a389c70040c36a9afad15fcb48dfd2.diff
LOG: [AArch64][GlobalISel] Legalize 32-bit + narrow G_SMULO + G_UMULO
SDAG lowers 32-bit and 64-bit G_SMULO + G_UMULO. We were missing the 32-bit
case.
For other sizes, make the 0th type a power of 2 and clamp it to either 32 bits
or 64 bits.
Right now, this will allow us to handle narrow types (e.g. s4, s24, etc.). The
LegalizerHelper doesn't support narrowing G_SMULO or G_UMULO right now. I think
we want clamping behaviour either way, so we might as well include it now to
be explicit.
Differential Revision: https://reviews.llvm.org/D108240
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 98307aa3822e..c40a288c8623 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -169,7 +169,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder({G_SREM, G_UREM, G_SDIVREM, G_UDIVREM})
.lowerFor({s1, s8, s16, s32, s64});
- getActionDefinitionsBuilder({G_SMULO, G_UMULO}).lowerFor({{s64, s1}});
+ getActionDefinitionsBuilder({G_SMULO, G_UMULO})
+ .widenScalarToNextPow2(0, /*Min = */ 32)
+ .clampScalar(0, s32, s64)
+ .lowerIf(typeIs(1, s1));
getActionDefinitionsBuilder({G_SMULH, G_UMULH}).legalFor({s32, s64});
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
index 530fbdf932b2..2da155797fa9 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
@@ -136,6 +136,19 @@ entry:
ret void
}
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %4:_(s128), %5:_(s1) = G_UMULO %0:_, %6:_ (in function: umul_s128)
+; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for umul_s128
+; FALLBACK-WITH-REPORT-OUT-LABEL: umul_s128
+declare {i128, i1} @llvm.umul.with.overflow.i128(i128, i128) nounwind readnone
+define zeroext i1 @umul_s128(i128 %v1, i128* %res) {
+entry:
+ %t = call {i128, i1} @llvm.umul.with.overflow.i128(i128 %v1, i128 2)
+ %val = extractvalue {i128, i1} %t, 0
+ %obit = extractvalue {i128, i1} %t, 1
+ store i128 %val, i128* %res
+ ret i1 %obit
+}
+
attributes #1 = { "target-features"="+sve" }
attributes #2 = { "target-features"="+ls64" }
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
index c9c0c9f9fe4c..d674b0d12ffe 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
@@ -65,6 +65,93 @@ body: |
%4:_(s32) = G_ANYEXT %3(s1)
$w0 = COPY %4(s32)
+...
+---
+name: test_smul_overflow_s32
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_smul_overflow_s32
+ ; CHECK: %lhs:_(s32) = COPY $w0
+ ; CHECK: %rhs:_(s32) = COPY $w1
+ ; CHECK: [[SMULH:%[0-9]+]]:_(s32) = G_SMULH %lhs, %rhs
+ ; CHECK: %mul:_(s32) = G_MUL %lhs, %rhs
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
+ ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR %mul, [[C]](s64)
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SMULH]](s32), [[ASHR]]
+ ; CHECK: $w0 = COPY %mul(s32)
+ ; CHECK: %ext_overflow:_(s32) = COPY [[ICMP]](s32)
+ ; CHECK: $w0 = COPY %ext_overflow(s32)
+ ; CHECK: RET_ReallyLR implicit $w0
+ %lhs:_(s32) = COPY $w0
+ %rhs:_(s32) = COPY $w1
+ %mul:_(s32), %overflow:_(s1) = G_SMULO %lhs, %rhs
+ $w0 = COPY %mul(s32)
+ %ext_overflow:_(s32) = G_ANYEXT %overflow(s1)
+ $w0 = COPY %ext_overflow(s32)
+ RET_ReallyLR implicit $w0
+
+...
+---
+name: test_umul_overflow_s32
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_umul_overflow_s32
+ ; CHECK: %lhs:_(s32) = COPY $w0
+ ; CHECK: %rhs:_(s32) = COPY $w1
+ ; CHECK: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH %lhs, %rhs
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: %mul:_(s32) = G_MUL %lhs, %rhs
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C]]
+ ; CHECK: $w0 = COPY %mul(s32)
+ ; CHECK: %ext_overflow:_(s32) = COPY [[ICMP]](s32)
+ ; CHECK: $w0 = COPY %ext_overflow(s32)
+ ; CHECK: RET_ReallyLR implicit $w0
+ %lhs:_(s32) = COPY $w0
+ %rhs:_(s32) = COPY $w1
+ %mul:_(s32), %overflow:_(s1) = G_UMULO %lhs, %rhs
+ $w0 = COPY %mul(s32)
+ %ext_overflow:_(s32) = G_ANYEXT %overflow(s1)
+ $w0 = COPY %ext_overflow(s32)
+ RET_ReallyLR implicit $w0
+
+...
+---
+name: test_umul_overflow_s24
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: test_umul_overflow_s24
+ ; CHECK: %lhs_wide:_(s32) = COPY $w0
+ ; CHECK: %rhs_wide:_(s32) = COPY $w1
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %lhs_wide(s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %rhs_wide(s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
+ ; CHECK: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[AND]], [[AND1]]
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND]], [[AND1]]
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[UMULH]](s32), [[C1]]
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C]]
+ ; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[MUL]](s32), [[AND2]]
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+ ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
+ ; CHECK: %ext_mul:_(s32) = COPY [[MUL]](s32)
+ ; CHECK: $w0 = COPY %ext_mul(s32)
+ ; CHECK: %ext_overflow:_(s32) = COPY [[OR]](s32)
+ ; CHECK: $w0 = COPY %ext_overflow(s32)
+ ; CHECK: RET_ReallyLR implicit $w0
+ %lhs_wide:_(s32) = COPY $w0
+ %rhs_wide:_(s32) = COPY $w1
+ %lhs:_(s24) = G_TRUNC %lhs_wide
+ %rhs:_(s24) = G_TRUNC %rhs_wide
+ %mul:_(s24), %overflow:_(s1) = G_UMULO %lhs, %rhs
+ %ext_mul:_(s32) = G_ANYEXT %mul
+ $w0 = COPY %ext_mul(s32)
+ %ext_overflow:_(s32) = G_ANYEXT %overflow(s1)
+ $w0 = COPY %ext_overflow(s32)
+ RET_ReallyLR implicit $w0
+
...
---
name: vector_mul_scalarize
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 244ed98dcc2f..3cd0e7add9db 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -341,11 +341,11 @@
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: G_UMULO (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
-# DEBUG-NEXT: .. the first uncovered type index: 2, OK
-# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_SMULO (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
-# DEBUG-NEXT: .. the first uncovered type index: 2, OK
-# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_UMULH (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
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