[PATCH] D108447: [RISCV] Implement BuildSDIVPow2, use cmov to lower sdiv pow2.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Can you add test cases for dividing by power of 2 larger than 4096/-4096? Those will cause the add with pow2-1 to not fit in the an ADDI anymore. So I think that would be worse code?

I'm not sure it is worth doing this right now given that Zbt is not up for ratification and there has been a lot of discussion about how much encoding space cmov uses.



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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2184
+  // Only support i64 in RV64.
+  if (VT == MVT::i64 && !Subtarget.is64Bit())
+    return SDValue();
----------------
What about i128 and larger? Or is that already blocked by the caller?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D108447/new/

https://reviews.llvm.org/D108447