[PATCH] D108372: [X86][SchedModels] Fix missing ReadAdvance for MULX and ADCX/ADOX (PR51494)

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


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Comment at: llvm/lib/Target/X86/X86ScheduleZnver3.td:631
   let Latency = !add(Znver3Model.LoadLatency, Zn3MULX32rr.Latency);
   let ResourceCycles = [1, 1, 2];
   let NumMicroOps = Zn3MULX32rr.NumMicroOps;
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lebedev.ri wrote:
> andreadb wrote:
> > RKSimon wrote:
> > > its weird that the rm variant uses the Zn3Multiplier pipe for an extra cycle......
> > Yeah. That is basically the reason why I couldn't remove the InstRW from the znver3 model.
> > 
> > I also wonder why there is an extra Zn3Multiplier cycle only for the RM variants. Normally, you would expect the RM variants to semantically behave like a Load+RR sequence.
> > 
> > Maybe it was done intentionally, to artificially decrease the throughput of the MULX RM variants only (in order to better match the exegesis report).
> > 
> Yes, but i'm pretty sure this is not a typo.
> There might be modelling problems in mca/exegesis, so it //might// be spurious.
> Maybe it was done intentionally, to artificially decrease the throughput of the MULX RM variants only (in order to better match the exegesis report).

Yep, that was my comment precisely.



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https://reviews.llvm.org/D108372