[PATCH] D108355: [AggressiveInstCombine] Add arithmetic shift right instr to `TruncInstCombine` DAG

[Anton Afanasyev via Phabricator via llvm-commits]

anton-afanasyev updated this revision to Diff 367782.
anton-afanasyev marked 4 inline comments as done.
anton-afanasyev added a comment.

Make step back, leaving `lshr` untouched and counting sign bits for `ashr` only.
The motivation is such that for natural cases unsigned values are
`zext`ed and `lshr`ed whereas signed values are `sext`ed and `ashr`ed.
So it is naturally to grasp only these two cases. We miss here cases like truncation of `ashr(zext(*))`,
but it is transformed for AIC by preceding IC to `lshr(zext(*))`. Also remove unrelated tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108355/new/

https://reviews.llvm.org/D108355

Files:
  llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
  llvm/test/Transforms/AggressiveInstCombine/trunc_ashr.ll

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