[PATCH] D108206: [RISCV] Fix reporting of incorrect commutable operand indices

[Fraser Cormack via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5b06cbac11e5: [RISCV] Fix reporting of incorrect commutable operand indices (authored by frasercrmck).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108206/new/

https://reviews.llvm.org/D108206

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir


Index: llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir
@@ -0,0 +1,45 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=riscv64 -mattr=+experimental-v -run-pass=simple-register-coalescing %s -o - 2>&1 | FileCheck %s
+
+# This test used to crash in the register coalescer when the target would
+# return the out-of-bounds CommuteAnyOperandIndex for one of its commutable
+# operand indices.
+
+--- |
+  target triple = "riscv64"
+  target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
+
+  define void @commuted_op_indices() {
+    unreachable
+  }
+...
+---
+name:            commuted_op_indices
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vr, preferred-register: '' }
+  - { id: 1, class: vrnov0, preferred-register: '' }
+  - { id: 2, class: vrnov0, preferred-register: '' }
+  - { id: 3, class: vr, preferred-register: '' }
+body:             |
+  bb.0:
+    liveins: $v0, $v1, $v2
+    ; CHECK-LABEL: name: commuted_op_indices
+    ; CHECK: liveins: $v0, $v1, $v2
+    ; CHECK: [[COPY:%[0-9]+]]:vr = COPY $v0
+    ; CHECK: [[COPY1:%[0-9]+]]:vrnov0 = COPY $v1
+    ; CHECK: [[COPY2:%[0-9]+]]:vrnov0 = COPY $v2
+    ; CHECK: [[PseudoVNMSUB_VV_M1_:%[0-9]+]]:vr = PseudoVNMSUB_VV_M1 [[PseudoVNMSUB_VV_M1_]], [[COPY1]], [[COPY2]], $x0, 6, 1, implicit $vl, implicit $vtype
+    ; CHECK: [[COPY2:%[0-9]+]]:vr = COPY [[PseudoVNMSUB_VV_M1_]]
+    ; CHECK: dead [[COPY2]]:vr = PseudoVSLL_VI_M1 [[COPY2]], 11, $noreg, 6, implicit $vl, implicit $vtype
+    ; CHECK: $v0 = COPY [[PseudoVNMSUB_VV_M1_]]
+    ; CHECK: PseudoRET implicit $v0
+    %0:vr = COPY $v0
+    %1:vrnov0 = COPY $v1
+    %2:vrnov0 = COPY $v2
+    %0:vr = PseudoVNMSUB_VV_M1 %0, %1, killed %2, $x0, 6, 1, implicit $vl, implicit $vtype
+    %3:vr = COPY %0
+    %3:vr = PseudoVSLL_VI_M1 %3, 11, $noreg, 6, implicit $vl, implicit $vtype
+    $v0 = COPY %0
+    PseudoRET implicit $v0
+...
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1273,7 +1273,7 @@
         // Both of operands are not fixed. Set one of commutable
         // operands to the tied source.
         CommutableOpIdx1 = 1;
-      } else if (SrcOpIdx1 == CommutableOpIdx1) {
+      } else if (SrcOpIdx1 == CommuteAnyOperandIndex) {
         // Only one of the operands is not fixed.
         CommutableOpIdx1 = SrcOpIdx2;
       }


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