[llvm] 2eefe4b - [Test][AggressiveInstCombine] Split shift tests to `shl`, `lshr` and `ashr`
Anton Afanasyev via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 19 20:34:48 PDT 2021
Author: Anton Afanasyev
Date: 2021-08-20T06:33:19+03:00
New Revision: 2eefe4bd173dbe9d4317cb321aa77ec7353294b3
URL: https://github.com/llvm/llvm-project/commit/2eefe4bd173dbe9d4317cb321aa77ec7353294b3
DIFF: https://github.com/llvm/llvm-project/commit/2eefe4bd173dbe9d4317cb321aa77ec7353294b3.diff
LOG: [Test][AggressiveInstCombine] Split shift tests to `shl`, `lshr` and `ashr`
Added:
llvm/test/Transforms/AggressiveInstCombine/trunc_ashr.ll
llvm/test/Transforms/AggressiveInstCombine/trunc_lshr.ll
llvm/test/Transforms/AggressiveInstCombine/trunc_shl.ll
Modified:
Removed:
llvm/test/Transforms/AggressiveInstCombine/trunc_shifts.ll
################################################################################
diff --git a/llvm/test/Transforms/AggressiveInstCombine/trunc_ashr.ll b/llvm/test/Transforms/AggressiveInstCombine/trunc_ashr.ll
new file mode 100644
index 000000000000..af9e608e7062
--- /dev/null
+++ b/llvm/test/Transforms/AggressiveInstCombine/trunc_ashr.ll
@@ -0,0 +1,245 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -aggressive-instcombine -S | FileCheck %s
+
+define i16 @ashr_15(i16 %x) {
+; CHECK-LABEL: @ashr_15(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
+; CHECK-NEXT: [[ASHR:%.*]] = ashr i32 [[ZEXT]], 15
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[ASHR]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext = zext i16 %x to i32
+ %ashr = ashr i32 %zext, 15
+ %trunc = trunc i32 %ashr to i16
+ ret i16 %trunc
+}
+
+; Negative test
+
+define i16 @ashr_16(i16 %x) {
+; CHECK-LABEL: @ashr_16(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
+; CHECK-NEXT: [[ASHR:%.*]] = ashr i32 [[ZEXT]], 16
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[ASHR]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext = zext i16 %x to i32
+ %ashr = ashr i32 %zext, 16
+ %trunc = trunc i32 %ashr to i16
+ ret i16 %trunc
+}
+
+; Negative test
+
+define i16 @ashr_var_shift_amount(i8 %x, i8 %amt) {
+; CHECK-LABEL: @ashr_var_shift_amount(
+; CHECK-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i32
+; CHECK-NEXT: [[ZA:%.*]] = zext i8 [[AMT:%.*]] to i32
+; CHECK-NEXT: [[S:%.*]] = ashr i32 [[Z]], [[ZA]]
+; CHECK-NEXT: [[A:%.*]] = add i32 [[S]], [[Z]]
+; CHECK-NEXT: [[S2:%.*]] = ashr i32 [[A]], 2
+; CHECK-NEXT: [[T:%.*]] = trunc i32 [[S2]] to i16
+; CHECK-NEXT: ret i16 [[T]]
+;
+ %z = zext i8 %x to i32
+ %za = zext i8 %amt to i32
+ %s = ashr i32 %z, %za
+ %a = add i32 %s, %z
+ %s2 = ashr i32 %a, 2
+ %t = trunc i32 %s2 to i16
+ ret i16 %t
+}
+
+define i16 @ashr_var_bounded_shift_amount(i8 %x, i8 %amt) {
+; CHECK-LABEL: @ashr_var_bounded_shift_amount(
+; CHECK-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i32
+; CHECK-NEXT: [[ZA:%.*]] = zext i8 [[AMT:%.*]] to i32
+; CHECK-NEXT: [[ZA2:%.*]] = and i32 [[ZA]], 15
+; CHECK-NEXT: [[S:%.*]] = ashr i32 [[Z]], [[ZA2]]
+; CHECK-NEXT: [[A:%.*]] = add i32 [[S]], [[Z]]
+; CHECK-NEXT: [[S2:%.*]] = ashr i32 [[A]], 2
+; CHECK-NEXT: [[T:%.*]] = trunc i32 [[S2]] to i16
+; CHECK-NEXT: ret i16 [[T]]
+;
+ %z = zext i8 %x to i32
+ %za = zext i8 %amt to i32
+ %za2 = and i32 %za, 15
+ %s = ashr i32 %z, %za2
+ %a = add i32 %s, %z
+ %s2 = ashr i32 %a, 2
+ %t = trunc i32 %s2 to i16
+ ret i16 %t
+}
+
+; Negative test
+
+define i32 @ashr_check_no_overflow(i32 %x, i16 %amt) {
+; CHECK-LABEL: @ashr_check_no_overflow(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[X:%.*]] to i64
+; CHECK-NEXT: [[SEXT:%.*]] = sext i16 [[AMT:%.*]] to i64
+; CHECK-NEXT: [[AND:%.*]] = and i64 [[SEXT]], 4294967295
+; CHECK-NEXT: [[SHL:%.*]] = ashr i64 [[ZEXT]], [[AND]]
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[SHL]] to i32
+; CHECK-NEXT: ret i32 [[TRUNC]]
+;
+ %zext = zext i32 %x to i64
+ %sext = sext i16 %amt to i64
+ %and = and i64 %sext, 4294967295
+ %shl = ashr i64 %zext, %and
+ %trunc = trunc i64 %shl to i32
+ ret i32 %trunc
+}
+
+define void @ashr_big_dag(i16* %a, i8 %b, i8 %c) {
+; CHECK-LABEL: @ashr_big_dag(
+; CHECK-NEXT: [[ZEXT1:%.*]] = zext i8 [[B:%.*]] to i32
+; CHECK-NEXT: [[ZEXT2:%.*]] = zext i8 [[C:%.*]] to i32
+; CHECK-NEXT: [[ADD1:%.*]] = add i32 [[ZEXT1]], [[ZEXT2]]
+; CHECK-NEXT: [[SFT1:%.*]] = and i32 [[ADD1]], 15
+; CHECK-NEXT: [[SHR1:%.*]] = ashr i32 [[ADD1]], [[SFT1]]
+; CHECK-NEXT: [[ADD2:%.*]] = add i32 [[ADD1]], [[SHR1]]
+; CHECK-NEXT: [[SFT2:%.*]] = and i32 [[ADD2]], 7
+; CHECK-NEXT: [[SHR2:%.*]] = ashr i32 [[ADD2]], [[SFT2]]
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SHR2]] to i16
+; CHECK-NEXT: store i16 [[TRUNC]], i16* [[A:%.*]], align 2
+; CHECK-NEXT: ret void
+;
+ %zext1 = zext i8 %b to i32
+ %zext2 = zext i8 %c to i32
+ %add1 = add i32 %zext1, %zext2
+ %sft1 = and i32 %add1, 15
+ %shr1 = ashr i32 %add1, %sft1
+ %add2 = add i32 %add1, %shr1
+ %sft2 = and i32 %add2, 7
+ %shr2 = ashr i32 %add2, %sft2
+ %trunc = trunc i32 %shr2 to i16
+ store i16 %trunc, i16* %a, align 2
+ ret void
+}
+
+; Negative test
+
+define i8 @ashr_check_not_i8_trunc(i16 %x) {
+; CHECK-LABEL: @ashr_check_not_i8_trunc(
+; CHECK-NEXT: [[ASHR:%.*]] = ashr i16 [[X:%.*]], 1
+; CHECK-NEXT: [[ZEXT2:%.*]] = zext i16 [[ASHR]] to i32
+; CHECK-NEXT: [[ASHR2:%.*]] = ashr i32 [[ZEXT2]], 2
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[ASHR2]] to i8
+; CHECK-NEXT: ret i8 [[TRUNC]]
+;
+ %ashr = ashr i16 %x, 1
+ %zext2 = zext i16 %ashr to i32
+ %ashr2 = ashr i32 %zext2, 2
+ %trunc = trunc i32 %ashr2 to i8
+ ret i8 %trunc
+}
+
+define <2 x i16> @ashr_vector(<2 x i8> %x) {
+; CHECK-LABEL: @ashr_vector(
+; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
+; CHECK-NEXT: [[ZA:%.*]] = and <2 x i32> [[Z]], <i32 7, i32 8>
+; CHECK-NEXT: [[S:%.*]] = ashr <2 x i32> [[Z]], [[ZA]]
+; CHECK-NEXT: [[A:%.*]] = add <2 x i32> [[S]], [[Z]]
+; CHECK-NEXT: [[S2:%.*]] = ashr <2 x i32> [[A]], <i32 4, i32 5>
+; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S2]] to <2 x i16>
+; CHECK-NEXT: ret <2 x i16> [[T]]
+;
+ %z = zext <2 x i8> %x to <2 x i32>
+ %za = and <2 x i32> %z, <i32 7, i32 8>
+ %s = ashr <2 x i32> %z, %za
+ %a = add <2 x i32> %s, %z
+ %s2 = ashr <2 x i32> %a, <i32 4, i32 5>
+ %t = trunc <2 x i32> %s2 to <2 x i16>
+ ret <2 x i16> %t
+}
+
+; Negative test - can only fold to <2 x i16>, requiring new vector type
+
+define <2 x i8> @ashr_vector_no_new_vector_type(<2 x i8> %x) {
+; CHECK-LABEL: @ashr_vector_no_new_vector_type(
+; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
+; CHECK-NEXT: [[ZA:%.*]] = and <2 x i32> [[Z]], <i32 7, i32 8>
+; CHECK-NEXT: [[S:%.*]] = ashr <2 x i32> [[Z]], [[ZA]]
+; CHECK-NEXT: [[A:%.*]] = add <2 x i32> [[S]], [[Z]]
+; CHECK-NEXT: [[S2:%.*]] = ashr <2 x i32> [[A]], <i32 4, i32 5>
+; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S2]] to <2 x i8>
+; CHECK-NEXT: ret <2 x i8> [[T]]
+;
+ %z = zext <2 x i8> %x to <2 x i32>
+ %za = and <2 x i32> %z, <i32 7, i32 8>
+ %s = ashr <2 x i32> %z, %za
+ %a = add <2 x i32> %s, %z
+ %s2 = ashr <2 x i32> %a, <i32 4, i32 5>
+ %t = trunc <2 x i32> %s2 to <2 x i8>
+ ret <2 x i8> %t
+}
+
+; Negative test
+
+define <2 x i16> @ashr_vector_large_shift_amount(<2 x i8> %x) {
+; CHECK-LABEL: @ashr_vector_large_shift_amount(
+; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
+; CHECK-NEXT: [[ZA:%.*]] = and <2 x i32> [[Z]], <i32 7, i32 8>
+; CHECK-NEXT: [[S:%.*]] = ashr <2 x i32> [[Z]], [[ZA]]
+; CHECK-NEXT: [[A:%.*]] = add <2 x i32> [[S]], [[Z]]
+; CHECK-NEXT: [[S2:%.*]] = ashr <2 x i32> [[A]], <i32 16, i32 5>
+; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S2]] to <2 x i16>
+; CHECK-NEXT: ret <2 x i16> [[T]]
+;
+ %z = zext <2 x i8> %x to <2 x i32>
+ %za = and <2 x i32> %z, <i32 7, i32 8>
+ %s = ashr <2 x i32> %z, %za
+ %a = add <2 x i32> %s, %z
+ %s2 = ashr <2 x i32> %a, <i32 16, i32 5>
+ %t = trunc <2 x i32> %s2 to <2 x i16>
+ ret <2 x i16> %t
+}
+
+define i16 @ashr_exact(i16 %x) {
+; CHECK-LABEL: @ashr_exact(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[ZEXT]], 32767
+; CHECK-NEXT: [[ASHR:%.*]] = ashr exact i32 [[AND]], 15
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[ASHR]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext = zext i16 %x to i32
+ %and = and i32 %zext, 32767
+ %ashr = ashr exact i32 %and, 15
+ %trunc = trunc i32 %ashr to i16
+ ret i16 %trunc
+}
+
+; Negative test
+
+define i16 @ashr_negative_operand(i16 %x) {
+; CHECK-LABEL: @ashr_negative_operand(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 -1, [[ZEXT]]
+; CHECK-NEXT: [[LSHR2:%.*]] = ashr i32 [[XOR]], 2
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[LSHR2]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext = zext i16 %x to i32
+ %xor = xor i32 -1, %zext
+ %lshr2 = ashr i32 %xor, 2
+ %trunc = trunc i32 %lshr2 to i16
+ ret i16 %trunc
+}
+
+define i16 @ashr_negative_operand_but_short(i16 %x) {
+; CHECK-LABEL: @ashr_negative_operand_but_short(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[ZEXT]], 32767
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 -1, [[AND]]
+; CHECK-NEXT: [[LSHR2:%.*]] = ashr i32 [[XOR]], 2
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[LSHR2]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext = zext i16 %x to i32
+ %and = and i32 %zext, 32767
+ %xor = xor i32 -1, %and
+ %lshr2 = ashr i32 %xor, 2
+ %trunc = trunc i32 %lshr2 to i16
+ ret i16 %trunc
+}
diff --git a/llvm/test/Transforms/AggressiveInstCombine/trunc_lshr.ll b/llvm/test/Transforms/AggressiveInstCombine/trunc_lshr.ll
new file mode 100644
index 000000000000..df0018d19312
--- /dev/null
+++ b/llvm/test/Transforms/AggressiveInstCombine/trunc_lshr.ll
@@ -0,0 +1,236 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -aggressive-instcombine -S | FileCheck %s
+
+define i16 @lshr_15(i16 %x) {
+; CHECK-LABEL: @lshr_15(
+; CHECK-NEXT: [[LSHR:%.*]] = lshr i16 [[X:%.*]], 15
+; CHECK-NEXT: ret i16 [[LSHR]]
+;
+ %zext = zext i16 %x to i32
+ %lshr = lshr i32 %zext, 15
+ %trunc = trunc i32 %lshr to i16
+ ret i16 %trunc
+}
+
+; Negative test
+
+define i16 @lshr_16(i16 %x) {
+; CHECK-LABEL: @lshr_16(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
+; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[ZEXT]], 16
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[LSHR]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext = zext i16 %x to i32
+ %lshr = lshr i32 %zext, 16
+ %trunc = trunc i32 %lshr to i16
+ ret i16 %trunc
+}
+
+; Negative test
+
+define i16 @lshr_var_shift_amount(i8 %x, i8 %amt) {
+; CHECK-LABEL: @lshr_var_shift_amount(
+; CHECK-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i32
+; CHECK-NEXT: [[ZA:%.*]] = zext i8 [[AMT:%.*]] to i32
+; CHECK-NEXT: [[S:%.*]] = lshr i32 [[Z]], [[ZA]]
+; CHECK-NEXT: [[A:%.*]] = add i32 [[S]], [[Z]]
+; CHECK-NEXT: [[S2:%.*]] = lshr i32 [[A]], 2
+; CHECK-NEXT: [[T:%.*]] = trunc i32 [[S2]] to i16
+; CHECK-NEXT: ret i16 [[T]]
+;
+ %z = zext i8 %x to i32
+ %za = zext i8 %amt to i32
+ %s = lshr i32 %z, %za
+ %a = add i32 %s, %z
+ %s2 = lshr i32 %a, 2
+ %t = trunc i32 %s2 to i16
+ ret i16 %t
+}
+
+define i16 @lshr_var_bounded_shift_amount(i8 %x, i8 %amt) {
+; CHECK-LABEL: @lshr_var_bounded_shift_amount(
+; CHECK-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i16
+; CHECK-NEXT: [[ZA:%.*]] = zext i8 [[AMT:%.*]] to i16
+; CHECK-NEXT: [[ZA2:%.*]] = and i16 [[ZA]], 15
+; CHECK-NEXT: [[S:%.*]] = lshr i16 [[Z]], [[ZA2]]
+; CHECK-NEXT: [[A:%.*]] = add i16 [[S]], [[Z]]
+; CHECK-NEXT: [[S2:%.*]] = lshr i16 [[A]], 2
+; CHECK-NEXT: ret i16 [[S2]]
+;
+ %z = zext i8 %x to i32
+ %za = zext i8 %amt to i32
+ %za2 = and i32 %za, 15
+ %s = lshr i32 %z, %za2
+ %a = add i32 %s, %z
+ %s2 = lshr i32 %a, 2
+ %t = trunc i32 %s2 to i16
+ ret i16 %t
+}
+
+; Negative test
+
+define i32 @lshr_check_no_overflow(i32 %x, i16 %amt) {
+; CHECK-LABEL: @lshr_check_no_overflow(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[X:%.*]] to i64
+; CHECK-NEXT: [[SEXT:%.*]] = sext i16 [[AMT:%.*]] to i64
+; CHECK-NEXT: [[AND:%.*]] = and i64 [[SEXT]], 4294967295
+; CHECK-NEXT: [[SHL:%.*]] = lshr i64 [[ZEXT]], [[AND]]
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[SHL]] to i32
+; CHECK-NEXT: ret i32 [[TRUNC]]
+;
+ %zext = zext i32 %x to i64
+ %sext = sext i16 %amt to i64
+ %and = and i64 %sext, 4294967295
+ %shl = lshr i64 %zext, %and
+ %trunc = trunc i64 %shl to i32
+ ret i32 %trunc
+}
+
+define void @lshr_big_dag(i16* %a, i8 %b, i8 %c) {
+; CHECK-LABEL: @lshr_big_dag(
+; CHECK-NEXT: [[ZEXT1:%.*]] = zext i8 [[B:%.*]] to i16
+; CHECK-NEXT: [[ZEXT2:%.*]] = zext i8 [[C:%.*]] to i16
+; CHECK-NEXT: [[ADD1:%.*]] = add i16 [[ZEXT1]], [[ZEXT2]]
+; CHECK-NEXT: [[SFT1:%.*]] = and i16 [[ADD1]], 15
+; CHECK-NEXT: [[SHR1:%.*]] = lshr i16 [[ADD1]], [[SFT1]]
+; CHECK-NEXT: [[ADD2:%.*]] = add i16 [[ADD1]], [[SHR1]]
+; CHECK-NEXT: [[SFT2:%.*]] = and i16 [[ADD2]], 7
+; CHECK-NEXT: [[SHR2:%.*]] = lshr i16 [[ADD2]], [[SFT2]]
+; CHECK-NEXT: store i16 [[SHR2]], i16* [[A:%.*]], align 2
+; CHECK-NEXT: ret void
+;
+ %zext1 = zext i8 %b to i32
+ %zext2 = zext i8 %c to i32
+ %add1 = add i32 %zext1, %zext2
+ %sft1 = and i32 %add1, 15
+ %shr1 = lshr i32 %add1, %sft1
+ %add2 = add i32 %add1, %shr1
+ %sft2 = and i32 %add2, 7
+ %shr2 = lshr i32 %add2, %sft2
+ %trunc = trunc i32 %shr2 to i16
+ store i16 %trunc, i16* %a, align 2
+ ret void
+}
+
+; Negative test
+
+define i8 @lshr_check_not_i8_trunc(i16 %x) {
+; CHECK-LABEL: @lshr_check_not_i8_trunc(
+; CHECK-NEXT: [[LSHR:%.*]] = lshr i16 [[X:%.*]], 1
+; CHECK-NEXT: [[ZEXT2:%.*]] = zext i16 [[LSHR]] to i32
+; CHECK-NEXT: [[LSHR2:%.*]] = lshr i32 [[ZEXT2]], 2
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[LSHR2]] to i8
+; CHECK-NEXT: ret i8 [[TRUNC]]
+;
+ %lshr = lshr i16 %x, 1
+ %zext2 = zext i16 %lshr to i32
+ %lshr2 = lshr i32 %zext2, 2
+ %trunc = trunc i32 %lshr2 to i8
+ ret i8 %trunc
+}
+
+define <2 x i16> @lshr_vector(<2 x i8> %x) {
+; CHECK-LABEL: @lshr_vector(
+; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
+; CHECK-NEXT: [[ZA:%.*]] = and <2 x i16> [[Z]], <i16 7, i16 8>
+; CHECK-NEXT: [[S:%.*]] = lshr <2 x i16> [[Z]], [[ZA]]
+; CHECK-NEXT: [[A:%.*]] = add <2 x i16> [[S]], [[Z]]
+; CHECK-NEXT: [[S2:%.*]] = lshr <2 x i16> [[A]], <i16 4, i16 5>
+; CHECK-NEXT: ret <2 x i16> [[S2]]
+;
+ %z = zext <2 x i8> %x to <2 x i32>
+ %za = and <2 x i32> %z, <i32 7, i32 8>
+ %s = lshr <2 x i32> %z, %za
+ %a = add <2 x i32> %s, %z
+ %s2 = lshr <2 x i32> %a, <i32 4, i32 5>
+ %t = trunc <2 x i32> %s2 to <2 x i16>
+ ret <2 x i16> %t
+}
+
+; Negative test - can only fold to <2 x i16>, requiring new vector type
+
+define <2 x i8> @lshr_vector_no_new_vector_type(<2 x i8> %x) {
+; CHECK-LABEL: @lshr_vector_no_new_vector_type(
+; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
+; CHECK-NEXT: [[ZA:%.*]] = and <2 x i32> [[Z]], <i32 7, i32 8>
+; CHECK-NEXT: [[S:%.*]] = lshr <2 x i32> [[Z]], [[ZA]]
+; CHECK-NEXT: [[A:%.*]] = add <2 x i32> [[S]], [[Z]]
+; CHECK-NEXT: [[S2:%.*]] = lshr <2 x i32> [[A]], <i32 4, i32 5>
+; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S2]] to <2 x i8>
+; CHECK-NEXT: ret <2 x i8> [[T]]
+;
+ %z = zext <2 x i8> %x to <2 x i32>
+ %za = and <2 x i32> %z, <i32 7, i32 8>
+ %s = lshr <2 x i32> %z, %za
+ %a = add <2 x i32> %s, %z
+ %s2 = lshr <2 x i32> %a, <i32 4, i32 5>
+ %t = trunc <2 x i32> %s2 to <2 x i8>
+ ret <2 x i8> %t
+}
+
+; Negative test
+
+define <2 x i16> @lshr_vector_large_shift_amount(<2 x i8> %x) {
+; CHECK-LABEL: @lshr_vector_large_shift_amount(
+; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
+; CHECK-NEXT: [[ZA:%.*]] = and <2 x i32> [[Z]], <i32 7, i32 8>
+; CHECK-NEXT: [[S:%.*]] = lshr <2 x i32> [[Z]], [[ZA]]
+; CHECK-NEXT: [[A:%.*]] = add <2 x i32> [[S]], [[Z]]
+; CHECK-NEXT: [[S2:%.*]] = lshr <2 x i32> [[A]], <i32 16, i32 5>
+; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S2]] to <2 x i16>
+; CHECK-NEXT: ret <2 x i16> [[T]]
+;
+ %z = zext <2 x i8> %x to <2 x i32>
+ %za = and <2 x i32> %z, <i32 7, i32 8>
+ %s = lshr <2 x i32> %z, %za
+ %a = add <2 x i32> %s, %z
+ %s2 = lshr <2 x i32> %a, <i32 16, i32 5>
+ %t = trunc <2 x i32> %s2 to <2 x i16>
+ ret <2 x i16> %t
+}
+
+define i16 @lshr_exact(i16 %x) {
+; CHECK-LABEL: @lshr_exact(
+; CHECK-NEXT: [[LSHR:%.*]] = lshr exact i16 [[X:%.*]], 15
+; CHECK-NEXT: ret i16 [[LSHR]]
+;
+ %zext = zext i16 %x to i32
+ %lshr = lshr exact i32 %zext, 15
+ %trunc = trunc i32 %lshr to i16
+ ret i16 %trunc
+}
+
+; Negative test
+
+define i16 @lshr_negative_operand(i16 %x) {
+; CHECK-LABEL: @lshr_negative_operand(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 -1, [[ZEXT]]
+; CHECK-NEXT: [[LSHR2:%.*]] = lshr i32 [[XOR]], 2
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[LSHR2]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext = zext i16 %x to i32
+ %xor = xor i32 -1, %zext
+ %lshr2 = lshr i32 %xor, 2
+ %trunc = trunc i32 %lshr2 to i16
+ ret i16 %trunc
+}
+
+define i16 @lshr_negative_operand_but_short(i16 %x) {
+; CHECK-LABEL: @lshr_negative_operand_but_short(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
+; CHECK-NEXT: [[AND:%.*]] = and i32 [[ZEXT]], 32767
+; CHECK-NEXT: [[XOR:%.*]] = xor i32 -1, [[AND]]
+; CHECK-NEXT: [[LSHR2:%.*]] = lshr i32 [[XOR]], 2
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[LSHR2]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext = zext i16 %x to i32
+ %and = and i32 %zext, 32767
+ %xor = xor i32 -1, %and
+ %lshr2 = lshr i32 %xor, 2
+ %trunc = trunc i32 %lshr2 to i16
+ ret i16 %trunc
+}
diff --git a/llvm/test/Transforms/AggressiveInstCombine/trunc_shifts.ll b/llvm/test/Transforms/AggressiveInstCombine/trunc_shifts.ll
deleted file mode 100644
index f03c2135b678..000000000000
--- a/llvm/test/Transforms/AggressiveInstCombine/trunc_shifts.ll
+++ /dev/null
@@ -1,636 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -aggressive-instcombine -S | FileCheck %s
-
-define i16 @shl_1(i8 %x) {
-; CHECK-LABEL: @shl_1(
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[X:%.*]] to i16
-; CHECK-NEXT: [[SHL:%.*]] = shl i16 [[ZEXT]], 1
-; CHECK-NEXT: ret i16 [[SHL]]
-;
- %zext = zext i8 %x to i32
- %shl = shl i32 %zext, 1
- %trunc = trunc i32 %shl to i16
- ret i16 %trunc
-}
-
-define i16 @shl_15(i8 %x) {
-; CHECK-LABEL: @shl_15(
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[X:%.*]] to i16
-; CHECK-NEXT: [[SHL:%.*]] = shl i16 [[ZEXT]], 15
-; CHECK-NEXT: ret i16 [[SHL]]
-;
- %zext = zext i8 %x to i32
- %shl = shl i32 %zext, 15
- %trunc = trunc i32 %shl to i16
- ret i16 %trunc
-}
-
-; Negative test - shift amount isn't less than target bitwidth
-
-define i16 @shl_16(i8 %x) {
-; CHECK-LABEL: @shl_16(
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[X:%.*]] to i32
-; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[ZEXT]], 16
-; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SHL]] to i16
-; CHECK-NEXT: ret i16 [[TRUNC]]
-;
- %zext = zext i8 %x to i32
- %shl = shl i32 %zext, 16
- %trunc = trunc i32 %shl to i16
- ret i16 %trunc
-}
-
-; Negative test -- variable shift amount
-
-define i16 @shl_var_shift_amount(i8 %x, i8 %y) {
-; CHECK-LABEL: @shl_var_shift_amount(
-; CHECK-NEXT: [[ZEXT_X:%.*]] = zext i8 [[X:%.*]] to i32
-; CHECK-NEXT: [[ZEXT_Y:%.*]] = zext i8 [[Y:%.*]] to i32
-; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[ZEXT_X]], [[ZEXT_Y]]
-; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SHL]] to i16
-; CHECK-NEXT: ret i16 [[TRUNC]]
-;
- %zext.x = zext i8 %x to i32
- %zext.y = zext i8 %y to i32
- %shl = shl i32 %zext.x, %zext.y
- %trunc = trunc i32 %shl to i16
- ret i16 %trunc
-}
-
-define i16 @shl_var_bounded_shift_amount(i8 %x, i8 %y) {
-; CHECK-LABEL: @shl_var_bounded_shift_amount(
-; CHECK-NEXT: [[ZEXT_X:%.*]] = zext i8 [[X:%.*]] to i16
-; CHECK-NEXT: [[ZEXT_Y:%.*]] = zext i8 [[Y:%.*]] to i16
-; CHECK-NEXT: [[AND:%.*]] = and i16 [[ZEXT_Y]], 15
-; CHECK-NEXT: [[SHL:%.*]] = shl i16 [[ZEXT_X]], [[AND]]
-; CHECK-NEXT: ret i16 [[SHL]]
-;
- %zext.x = zext i8 %x to i32
- %zext.y = zext i8 %y to i32
- %and = and i32 %zext.y, 15
- %shl = shl i32 %zext.x, %and
- %trunc = trunc i32 %shl to i16
- ret i16 %trunc
-}
-
-; Negative test (https://reviews.llvm.org/D108091#2950930)
-
-define i32 @shl_check_no_overflow(i32 %x, i16 %amt) {
-; CHECK-LABEL: @shl_check_no_overflow(
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[X:%.*]] to i64
-; CHECK-NEXT: [[SEXT:%.*]] = sext i16 [[AMT:%.*]] to i64
-; CHECK-NEXT: [[AND:%.*]] = and i64 [[SEXT]], 4294967295
-; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[ZEXT]], [[AND]]
-; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[SHL]] to i32
-; CHECK-NEXT: ret i32 [[TRUNC]]
-;
- %zext = zext i32 %x to i64
- %sext = sext i16 %amt to i64
- %and = and i64 %sext, 4294967295
- %shl = shl i64 %zext, %and
- %trunc = trunc i64 %shl to i32
- ret i32 %trunc
-}
-
-define <2 x i16> @shl_vector(<2 x i8> %x) {
-; CHECK-LABEL: @shl_vector(
-; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
-; CHECK-NEXT: [[S:%.*]] = shl <2 x i16> [[Z]], <i16 4, i16 10>
-; CHECK-NEXT: ret <2 x i16> [[S]]
-;
- %z = zext <2 x i8> %x to <2 x i32>
- %s = shl <2 x i32> %z, <i32 4, i32 10>
- %t = trunc <2 x i32> %s to <2 x i16>
- ret <2 x i16> %t
-}
-
-; Negative test - can only fold to <2 x i16>, requiring new vector type
-
-define <2 x i8> @shl_vector_no_new_vector_type(<2 x i8> %x) {
-; CHECK-LABEL: @shl_vector_no_new_vector_type(
-; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
-; CHECK-NEXT: [[S:%.*]] = shl <2 x i32> [[Z]], <i32 4, i32 10>
-; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S]] to <2 x i8>
-; CHECK-NEXT: ret <2 x i8> [[T]]
-;
- %z = zext <2 x i8> %x to <2 x i32>
- %s = shl <2 x i32> %z, <i32 4, i32 10>
- %t = trunc <2 x i32> %s to <2 x i8>
- ret <2 x i8> %t
-}
-
-; Negative test
-
-define <2 x i16> @shl_vector_large_shift_amount(<2 x i8> %x) {
-; CHECK-LABEL: @shl_vector_large_shift_amount(
-; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
-; CHECK-NEXT: [[S:%.*]] = shl <2 x i32> [[Z]], <i32 16, i32 5>
-; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S]] to <2 x i16>
-; CHECK-NEXT: ret <2 x i16> [[T]]
-;
- %z = zext <2 x i8> %x to <2 x i32>
- %s = shl <2 x i32> %z, <i32 16, i32 5>
- %t = trunc <2 x i32> %s to <2 x i16>
- ret <2 x i16> %t
-}
-
-define i16 @shl_nuw(i8 %x) {
-; CHECK-LABEL: @shl_nuw(
-; CHECK-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i16
-; CHECK-NEXT: [[S:%.*]] = shl i16 [[Z]], 15
-; CHECK-NEXT: ret i16 [[S]]
-;
- %z = zext i8 %x to i32
- %s = shl nuw i32 %z, 15
- %t = trunc i32 %s to i16
- ret i16 %t
-}
-
-define i16 @shl_nsw(i8 %x) {
-; CHECK-LABEL: @shl_nsw(
-; CHECK-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i16
-; CHECK-NEXT: [[S:%.*]] = shl i16 [[Z]], 15
-; CHECK-NEXT: ret i16 [[S]]
-;
- %z = zext i8 %x to i32
- %s = shl nsw i32 %z, 15
- %t = trunc i32 %s to i16
- ret i16 %t
-}
-
-define i16 @lshr_15(i16 %x) {
-; CHECK-LABEL: @lshr_15(
-; CHECK-NEXT: [[LSHR:%.*]] = lshr i16 [[X:%.*]], 15
-; CHECK-NEXT: ret i16 [[LSHR]]
-;
- %zext = zext i16 %x to i32
- %lshr = lshr i32 %zext, 15
- %trunc = trunc i32 %lshr to i16
- ret i16 %trunc
-}
-
-; Negative test
-
-define i16 @lshr_16(i16 %x) {
-; CHECK-LABEL: @lshr_16(
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
-; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[ZEXT]], 16
-; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[LSHR]] to i16
-; CHECK-NEXT: ret i16 [[TRUNC]]
-;
- %zext = zext i16 %x to i32
- %lshr = lshr i32 %zext, 16
- %trunc = trunc i32 %lshr to i16
- ret i16 %trunc
-}
-
-; Negative test
-
-define i16 @lshr_var_shift_amount(i8 %x, i8 %amt) {
-; CHECK-LABEL: @lshr_var_shift_amount(
-; CHECK-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i32
-; CHECK-NEXT: [[ZA:%.*]] = zext i8 [[AMT:%.*]] to i32
-; CHECK-NEXT: [[S:%.*]] = lshr i32 [[Z]], [[ZA]]
-; CHECK-NEXT: [[A:%.*]] = add i32 [[S]], [[Z]]
-; CHECK-NEXT: [[S2:%.*]] = lshr i32 [[A]], 2
-; CHECK-NEXT: [[T:%.*]] = trunc i32 [[S2]] to i16
-; CHECK-NEXT: ret i16 [[T]]
-;
- %z = zext i8 %x to i32
- %za = zext i8 %amt to i32
- %s = lshr i32 %z, %za
- %a = add i32 %s, %z
- %s2 = lshr i32 %a, 2
- %t = trunc i32 %s2 to i16
- ret i16 %t
-}
-
-define i16 @lshr_var_bounded_shift_amount(i8 %x, i8 %amt) {
-; CHECK-LABEL: @lshr_var_bounded_shift_amount(
-; CHECK-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i16
-; CHECK-NEXT: [[ZA:%.*]] = zext i8 [[AMT:%.*]] to i16
-; CHECK-NEXT: [[ZA2:%.*]] = and i16 [[ZA]], 15
-; CHECK-NEXT: [[S:%.*]] = lshr i16 [[Z]], [[ZA2]]
-; CHECK-NEXT: [[A:%.*]] = add i16 [[S]], [[Z]]
-; CHECK-NEXT: [[S2:%.*]] = lshr i16 [[A]], 2
-; CHECK-NEXT: ret i16 [[S2]]
-;
- %z = zext i8 %x to i32
- %za = zext i8 %amt to i32
- %za2 = and i32 %za, 15
- %s = lshr i32 %z, %za2
- %a = add i32 %s, %z
- %s2 = lshr i32 %a, 2
- %t = trunc i32 %s2 to i16
- ret i16 %t
-}
-
-; Negative test
-
-define i32 @lshr_check_no_overflow(i32 %x, i16 %amt) {
-; CHECK-LABEL: @lshr_check_no_overflow(
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[X:%.*]] to i64
-; CHECK-NEXT: [[SEXT:%.*]] = sext i16 [[AMT:%.*]] to i64
-; CHECK-NEXT: [[AND:%.*]] = and i64 [[SEXT]], 4294967295
-; CHECK-NEXT: [[SHL:%.*]] = lshr i64 [[ZEXT]], [[AND]]
-; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[SHL]] to i32
-; CHECK-NEXT: ret i32 [[TRUNC]]
-;
- %zext = zext i32 %x to i64
- %sext = sext i16 %amt to i64
- %and = and i64 %sext, 4294967295
- %shl = lshr i64 %zext, %and
- %trunc = trunc i64 %shl to i32
- ret i32 %trunc
-}
-
-define void @lshr_big_dag(i16* %a, i8 %b, i8 %c) {
-; CHECK-LABEL: @lshr_big_dag(
-; CHECK-NEXT: [[ZEXT1:%.*]] = zext i8 [[B:%.*]] to i16
-; CHECK-NEXT: [[ZEXT2:%.*]] = zext i8 [[C:%.*]] to i16
-; CHECK-NEXT: [[ADD1:%.*]] = add i16 [[ZEXT1]], [[ZEXT2]]
-; CHECK-NEXT: [[SFT1:%.*]] = and i16 [[ADD1]], 15
-; CHECK-NEXT: [[SHR1:%.*]] = lshr i16 [[ADD1]], [[SFT1]]
-; CHECK-NEXT: [[ADD2:%.*]] = add i16 [[ADD1]], [[SHR1]]
-; CHECK-NEXT: [[SFT2:%.*]] = and i16 [[ADD2]], 7
-; CHECK-NEXT: [[SHR2:%.*]] = lshr i16 [[ADD2]], [[SFT2]]
-; CHECK-NEXT: store i16 [[SHR2]], i16* [[A:%.*]], align 2
-; CHECK-NEXT: ret void
-;
- %zext1 = zext i8 %b to i32
- %zext2 = zext i8 %c to i32
- %add1 = add i32 %zext1, %zext2
- %sft1 = and i32 %add1, 15
- %shr1 = lshr i32 %add1, %sft1
- %add2 = add i32 %add1, %shr1
- %sft2 = and i32 %add2, 7
- %shr2 = lshr i32 %add2, %sft2
- %trunc = trunc i32 %shr2 to i16
- store i16 %trunc, i16* %a, align 2
- ret void
-}
-
-; Negative test
-
-define i8 @lshr_check_not_i8_trunc(i16 %x) {
-; CHECK-LABEL: @lshr_check_not_i8_trunc(
-; CHECK-NEXT: [[LSHR:%.*]] = lshr i16 [[X:%.*]], 1
-; CHECK-NEXT: [[ZEXT2:%.*]] = zext i16 [[LSHR]] to i32
-; CHECK-NEXT: [[LSHR2:%.*]] = lshr i32 [[ZEXT2]], 2
-; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[LSHR2]] to i8
-; CHECK-NEXT: ret i8 [[TRUNC]]
-;
- %lshr = lshr i16 %x, 1
- %zext2 = zext i16 %lshr to i32
- %lshr2 = lshr i32 %zext2, 2
- %trunc = trunc i32 %lshr2 to i8
- ret i8 %trunc
-}
-
-define <2 x i16> @lshr_vector(<2 x i8> %x) {
-; CHECK-LABEL: @lshr_vector(
-; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
-; CHECK-NEXT: [[ZA:%.*]] = and <2 x i16> [[Z]], <i16 7, i16 8>
-; CHECK-NEXT: [[S:%.*]] = lshr <2 x i16> [[Z]], [[ZA]]
-; CHECK-NEXT: [[A:%.*]] = add <2 x i16> [[S]], [[Z]]
-; CHECK-NEXT: [[S2:%.*]] = lshr <2 x i16> [[A]], <i16 4, i16 5>
-; CHECK-NEXT: ret <2 x i16> [[S2]]
-;
- %z = zext <2 x i8> %x to <2 x i32>
- %za = and <2 x i32> %z, <i32 7, i32 8>
- %s = lshr <2 x i32> %z, %za
- %a = add <2 x i32> %s, %z
- %s2 = lshr <2 x i32> %a, <i32 4, i32 5>
- %t = trunc <2 x i32> %s2 to <2 x i16>
- ret <2 x i16> %t
-}
-
-; Negative test - can only fold to <2 x i16>, requiring new vector type
-
-define <2 x i8> @lshr_vector_no_new_vector_type(<2 x i8> %x) {
-; CHECK-LABEL: @lshr_vector_no_new_vector_type(
-; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
-; CHECK-NEXT: [[ZA:%.*]] = and <2 x i32> [[Z]], <i32 7, i32 8>
-; CHECK-NEXT: [[S:%.*]] = lshr <2 x i32> [[Z]], [[ZA]]
-; CHECK-NEXT: [[A:%.*]] = add <2 x i32> [[S]], [[Z]]
-; CHECK-NEXT: [[S2:%.*]] = lshr <2 x i32> [[A]], <i32 4, i32 5>
-; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S2]] to <2 x i8>
-; CHECK-NEXT: ret <2 x i8> [[T]]
-;
- %z = zext <2 x i8> %x to <2 x i32>
- %za = and <2 x i32> %z, <i32 7, i32 8>
- %s = lshr <2 x i32> %z, %za
- %a = add <2 x i32> %s, %z
- %s2 = lshr <2 x i32> %a, <i32 4, i32 5>
- %t = trunc <2 x i32> %s2 to <2 x i8>
- ret <2 x i8> %t
-}
-
-; Negative test
-
-define <2 x i16> @lshr_vector_large_shift_amount(<2 x i8> %x) {
-; CHECK-LABEL: @lshr_vector_large_shift_amount(
-; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
-; CHECK-NEXT: [[ZA:%.*]] = and <2 x i32> [[Z]], <i32 7, i32 8>
-; CHECK-NEXT: [[S:%.*]] = lshr <2 x i32> [[Z]], [[ZA]]
-; CHECK-NEXT: [[A:%.*]] = add <2 x i32> [[S]], [[Z]]
-; CHECK-NEXT: [[S2:%.*]] = lshr <2 x i32> [[A]], <i32 16, i32 5>
-; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S2]] to <2 x i16>
-; CHECK-NEXT: ret <2 x i16> [[T]]
-;
- %z = zext <2 x i8> %x to <2 x i32>
- %za = and <2 x i32> %z, <i32 7, i32 8>
- %s = lshr <2 x i32> %z, %za
- %a = add <2 x i32> %s, %z
- %s2 = lshr <2 x i32> %a, <i32 16, i32 5>
- %t = trunc <2 x i32> %s2 to <2 x i16>
- ret <2 x i16> %t
-}
-
-define i16 @lshr_exact(i16 %x) {
-; CHECK-LABEL: @lshr_exact(
-; CHECK-NEXT: [[LSHR:%.*]] = lshr exact i16 [[X:%.*]], 15
-; CHECK-NEXT: ret i16 [[LSHR]]
-;
- %zext = zext i16 %x to i32
- %lshr = lshr exact i32 %zext, 15
- %trunc = trunc i32 %lshr to i16
- ret i16 %trunc
-}
-
-define i16 @ashr_15(i16 %x) {
-; CHECK-LABEL: @ashr_15(
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
-; CHECK-NEXT: [[ASHR:%.*]] = ashr i32 [[ZEXT]], 15
-; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[ASHR]] to i16
-; CHECK-NEXT: ret i16 [[TRUNC]]
-;
- %zext = zext i16 %x to i32
- %ashr = ashr i32 %zext, 15
- %trunc = trunc i32 %ashr to i16
- ret i16 %trunc
-}
-
-; Negative test
-
-define i16 @ashr_16(i16 %x) {
-; CHECK-LABEL: @ashr_16(
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
-; CHECK-NEXT: [[ASHR:%.*]] = ashr i32 [[ZEXT]], 16
-; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[ASHR]] to i16
-; CHECK-NEXT: ret i16 [[TRUNC]]
-;
- %zext = zext i16 %x to i32
- %ashr = ashr i32 %zext, 16
- %trunc = trunc i32 %ashr to i16
- ret i16 %trunc
-}
-
-; Negative test
-
-define i16 @ashr_var_shift_amount(i8 %x, i8 %amt) {
-; CHECK-LABEL: @ashr_var_shift_amount(
-; CHECK-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i32
-; CHECK-NEXT: [[ZA:%.*]] = zext i8 [[AMT:%.*]] to i32
-; CHECK-NEXT: [[S:%.*]] = ashr i32 [[Z]], [[ZA]]
-; CHECK-NEXT: [[A:%.*]] = add i32 [[S]], [[Z]]
-; CHECK-NEXT: [[S2:%.*]] = ashr i32 [[A]], 2
-; CHECK-NEXT: [[T:%.*]] = trunc i32 [[S2]] to i16
-; CHECK-NEXT: ret i16 [[T]]
-;
- %z = zext i8 %x to i32
- %za = zext i8 %amt to i32
- %s = ashr i32 %z, %za
- %a = add i32 %s, %z
- %s2 = ashr i32 %a, 2
- %t = trunc i32 %s2 to i16
- ret i16 %t
-}
-
-define i16 @ashr_var_bounded_shift_amount(i8 %x, i8 %amt) {
-; CHECK-LABEL: @ashr_var_bounded_shift_amount(
-; CHECK-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i32
-; CHECK-NEXT: [[ZA:%.*]] = zext i8 [[AMT:%.*]] to i32
-; CHECK-NEXT: [[ZA2:%.*]] = and i32 [[ZA]], 15
-; CHECK-NEXT: [[S:%.*]] = ashr i32 [[Z]], [[ZA2]]
-; CHECK-NEXT: [[A:%.*]] = add i32 [[S]], [[Z]]
-; CHECK-NEXT: [[S2:%.*]] = ashr i32 [[A]], 2
-; CHECK-NEXT: [[T:%.*]] = trunc i32 [[S2]] to i16
-; CHECK-NEXT: ret i16 [[T]]
-;
- %z = zext i8 %x to i32
- %za = zext i8 %amt to i32
- %za2 = and i32 %za, 15
- %s = ashr i32 %z, %za2
- %a = add i32 %s, %z
- %s2 = ashr i32 %a, 2
- %t = trunc i32 %s2 to i16
- ret i16 %t
-}
-
-; Negative test
-
-define i32 @ashr_check_no_overflow(i32 %x, i16 %amt) {
-; CHECK-LABEL: @ashr_check_no_overflow(
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[X:%.*]] to i64
-; CHECK-NEXT: [[SEXT:%.*]] = sext i16 [[AMT:%.*]] to i64
-; CHECK-NEXT: [[AND:%.*]] = and i64 [[SEXT]], 4294967295
-; CHECK-NEXT: [[SHL:%.*]] = ashr i64 [[ZEXT]], [[AND]]
-; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[SHL]] to i32
-; CHECK-NEXT: ret i32 [[TRUNC]]
-;
- %zext = zext i32 %x to i64
- %sext = sext i16 %amt to i64
- %and = and i64 %sext, 4294967295
- %shl = ashr i64 %zext, %and
- %trunc = trunc i64 %shl to i32
- ret i32 %trunc
-}
-
-define void @ashr_big_dag(i16* %a, i8 %b, i8 %c) {
-; CHECK-LABEL: @ashr_big_dag(
-; CHECK-NEXT: [[ZEXT1:%.*]] = zext i8 [[B:%.*]] to i32
-; CHECK-NEXT: [[ZEXT2:%.*]] = zext i8 [[C:%.*]] to i32
-; CHECK-NEXT: [[ADD1:%.*]] = add i32 [[ZEXT1]], [[ZEXT2]]
-; CHECK-NEXT: [[SFT1:%.*]] = and i32 [[ADD1]], 15
-; CHECK-NEXT: [[SHR1:%.*]] = ashr i32 [[ADD1]], [[SFT1]]
-; CHECK-NEXT: [[ADD2:%.*]] = add i32 [[ADD1]], [[SHR1]]
-; CHECK-NEXT: [[SFT2:%.*]] = and i32 [[ADD2]], 7
-; CHECK-NEXT: [[SHR2:%.*]] = ashr i32 [[ADD2]], [[SFT2]]
-; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SHR2]] to i16
-; CHECK-NEXT: store i16 [[TRUNC]], i16* [[A:%.*]], align 2
-; CHECK-NEXT: ret void
-;
- %zext1 = zext i8 %b to i32
- %zext2 = zext i8 %c to i32
- %add1 = add i32 %zext1, %zext2
- %sft1 = and i32 %add1, 15
- %shr1 = ashr i32 %add1, %sft1
- %add2 = add i32 %add1, %shr1
- %sft2 = and i32 %add2, 7
- %shr2 = ashr i32 %add2, %sft2
- %trunc = trunc i32 %shr2 to i16
- store i16 %trunc, i16* %a, align 2
- ret void
-}
-
-; Negative test
-
-define i8 @ashr_check_not_i8_trunc(i16 %x) {
-; CHECK-LABEL: @ashr_check_not_i8_trunc(
-; CHECK-NEXT: [[ASHR:%.*]] = ashr i16 [[X:%.*]], 1
-; CHECK-NEXT: [[ZEXT2:%.*]] = zext i16 [[ASHR]] to i32
-; CHECK-NEXT: [[ASHR2:%.*]] = ashr i32 [[ZEXT2]], 2
-; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[ASHR2]] to i8
-; CHECK-NEXT: ret i8 [[TRUNC]]
-;
- %ashr = ashr i16 %x, 1
- %zext2 = zext i16 %ashr to i32
- %ashr2 = ashr i32 %zext2, 2
- %trunc = trunc i32 %ashr2 to i8
- ret i8 %trunc
-}
-
-define <2 x i16> @ashr_vector(<2 x i8> %x) {
-; CHECK-LABEL: @ashr_vector(
-; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
-; CHECK-NEXT: [[ZA:%.*]] = and <2 x i32> [[Z]], <i32 7, i32 8>
-; CHECK-NEXT: [[S:%.*]] = ashr <2 x i32> [[Z]], [[ZA]]
-; CHECK-NEXT: [[A:%.*]] = add <2 x i32> [[S]], [[Z]]
-; CHECK-NEXT: [[S2:%.*]] = ashr <2 x i32> [[A]], <i32 4, i32 5>
-; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S2]] to <2 x i16>
-; CHECK-NEXT: ret <2 x i16> [[T]]
-;
- %z = zext <2 x i8> %x to <2 x i32>
- %za = and <2 x i32> %z, <i32 7, i32 8>
- %s = ashr <2 x i32> %z, %za
- %a = add <2 x i32> %s, %z
- %s2 = ashr <2 x i32> %a, <i32 4, i32 5>
- %t = trunc <2 x i32> %s2 to <2 x i16>
- ret <2 x i16> %t
-}
-
-; Negative test - can only fold to <2 x i16>, requiring new vector type
-
-define <2 x i8> @ashr_vector_no_new_vector_type(<2 x i8> %x) {
-; CHECK-LABEL: @ashr_vector_no_new_vector_type(
-; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
-; CHECK-NEXT: [[ZA:%.*]] = and <2 x i32> [[Z]], <i32 7, i32 8>
-; CHECK-NEXT: [[S:%.*]] = ashr <2 x i32> [[Z]], [[ZA]]
-; CHECK-NEXT: [[A:%.*]] = add <2 x i32> [[S]], [[Z]]
-; CHECK-NEXT: [[S2:%.*]] = ashr <2 x i32> [[A]], <i32 4, i32 5>
-; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S2]] to <2 x i8>
-; CHECK-NEXT: ret <2 x i8> [[T]]
-;
- %z = zext <2 x i8> %x to <2 x i32>
- %za = and <2 x i32> %z, <i32 7, i32 8>
- %s = ashr <2 x i32> %z, %za
- %a = add <2 x i32> %s, %z
- %s2 = ashr <2 x i32> %a, <i32 4, i32 5>
- %t = trunc <2 x i32> %s2 to <2 x i8>
- ret <2 x i8> %t
-}
-
-; Negative test
-
-define <2 x i16> @ashr_vector_large_shift_amount(<2 x i8> %x) {
-; CHECK-LABEL: @ashr_vector_large_shift_amount(
-; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
-; CHECK-NEXT: [[ZA:%.*]] = and <2 x i32> [[Z]], <i32 7, i32 8>
-; CHECK-NEXT: [[S:%.*]] = ashr <2 x i32> [[Z]], [[ZA]]
-; CHECK-NEXT: [[A:%.*]] = add <2 x i32> [[S]], [[Z]]
-; CHECK-NEXT: [[S2:%.*]] = ashr <2 x i32> [[A]], <i32 16, i32 5>
-; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S2]] to <2 x i16>
-; CHECK-NEXT: ret <2 x i16> [[T]]
-;
- %z = zext <2 x i8> %x to <2 x i32>
- %za = and <2 x i32> %z, <i32 7, i32 8>
- %s = ashr <2 x i32> %z, %za
- %a = add <2 x i32> %s, %z
- %s2 = ashr <2 x i32> %a, <i32 16, i32 5>
- %t = trunc <2 x i32> %s2 to <2 x i16>
- ret <2 x i16> %t
-}
-
-define i16 @ashr_exact(i16 %x) {
-; CHECK-LABEL: @ashr_exact(
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[ZEXT]], 32767
-; CHECK-NEXT: [[ASHR:%.*]] = ashr exact i32 [[AND]], 15
-; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[ASHR]] to i16
-; CHECK-NEXT: ret i16 [[TRUNC]]
-;
- %zext = zext i16 %x to i32
- %and = and i32 %zext, 32767
- %ashr = ashr exact i32 %and, 15
- %trunc = trunc i32 %ashr to i16
- ret i16 %trunc
-}
-
-; Negative test
-
-define i16 @lshr_negative_operand(i16 %x) {
-; CHECK-LABEL: @lshr_negative_operand(
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
-; CHECK-NEXT: [[XOR:%.*]] = xor i32 -1, [[ZEXT]]
-; CHECK-NEXT: [[LSHR2:%.*]] = lshr i32 [[XOR]], 2
-; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[LSHR2]] to i16
-; CHECK-NEXT: ret i16 [[TRUNC]]
-;
- %zext = zext i16 %x to i32
- %xor = xor i32 -1, %zext
- %lshr2 = lshr i32 %xor, 2
- %trunc = trunc i32 %lshr2 to i16
- ret i16 %trunc
-}
-
-define i16 @lshr_negative_operand_but_short(i16 %x) {
-; CHECK-LABEL: @lshr_negative_operand_but_short(
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[ZEXT]], 32767
-; CHECK-NEXT: [[XOR:%.*]] = xor i32 -1, [[AND]]
-; CHECK-NEXT: [[LSHR2:%.*]] = lshr i32 [[XOR]], 2
-; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[LSHR2]] to i16
-; CHECK-NEXT: ret i16 [[TRUNC]]
-;
- %zext = zext i16 %x to i32
- %and = and i32 %zext, 32767
- %xor = xor i32 -1, %and
- %lshr2 = lshr i32 %xor, 2
- %trunc = trunc i32 %lshr2 to i16
- ret i16 %trunc
-}
-
-; Negative test
-
-define i16 @ashr_negative_operand(i16 %x) {
-; CHECK-LABEL: @ashr_negative_operand(
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
-; CHECK-NEXT: [[XOR:%.*]] = xor i32 -1, [[ZEXT]]
-; CHECK-NEXT: [[LSHR2:%.*]] = ashr i32 [[XOR]], 2
-; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[LSHR2]] to i16
-; CHECK-NEXT: ret i16 [[TRUNC]]
-;
- %zext = zext i16 %x to i32
- %xor = xor i32 -1, %zext
- %lshr2 = ashr i32 %xor, 2
- %trunc = trunc i32 %lshr2 to i16
- ret i16 %trunc
-}
-
-define i16 @ashr_negative_operand_but_short(i16 %x) {
-; CHECK-LABEL: @ashr_negative_operand_but_short(
-; CHECK-NEXT: [[ZEXT:%.*]] = zext i16 [[X:%.*]] to i32
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[ZEXT]], 32767
-; CHECK-NEXT: [[XOR:%.*]] = xor i32 -1, [[AND]]
-; CHECK-NEXT: [[LSHR2:%.*]] = ashr i32 [[XOR]], 2
-; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[LSHR2]] to i16
-; CHECK-NEXT: ret i16 [[TRUNC]]
-;
- %zext = zext i16 %x to i32
- %and = and i32 %zext, 32767
- %xor = xor i32 -1, %and
- %lshr2 = ashr i32 %xor, 2
- %trunc = trunc i32 %lshr2 to i16
- ret i16 %trunc
-}
diff --git a/llvm/test/Transforms/AggressiveInstCombine/trunc_shl.ll b/llvm/test/Transforms/AggressiveInstCombine/trunc_shl.ll
new file mode 100644
index 000000000000..0b2a26a6d0e2
--- /dev/null
+++ b/llvm/test/Transforms/AggressiveInstCombine/trunc_shl.ll
@@ -0,0 +1,159 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -aggressive-instcombine -S | FileCheck %s
+
+define i16 @shl_1(i8 %x) {
+; CHECK-LABEL: @shl_1(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[X:%.*]] to i16
+; CHECK-NEXT: [[SHL:%.*]] = shl i16 [[ZEXT]], 1
+; CHECK-NEXT: ret i16 [[SHL]]
+;
+ %zext = zext i8 %x to i32
+ %shl = shl i32 %zext, 1
+ %trunc = trunc i32 %shl to i16
+ ret i16 %trunc
+}
+
+define i16 @shl_15(i8 %x) {
+; CHECK-LABEL: @shl_15(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[X:%.*]] to i16
+; CHECK-NEXT: [[SHL:%.*]] = shl i16 [[ZEXT]], 15
+; CHECK-NEXT: ret i16 [[SHL]]
+;
+ %zext = zext i8 %x to i32
+ %shl = shl i32 %zext, 15
+ %trunc = trunc i32 %shl to i16
+ ret i16 %trunc
+}
+
+; Negative test - shift amount isn't less than target bitwidth
+
+define i16 @shl_16(i8 %x) {
+; CHECK-LABEL: @shl_16(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[X:%.*]] to i32
+; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[ZEXT]], 16
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SHL]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext = zext i8 %x to i32
+ %shl = shl i32 %zext, 16
+ %trunc = trunc i32 %shl to i16
+ ret i16 %trunc
+}
+
+; Negative test -- variable shift amount
+
+define i16 @shl_var_shift_amount(i8 %x, i8 %y) {
+; CHECK-LABEL: @shl_var_shift_amount(
+; CHECK-NEXT: [[ZEXT_X:%.*]] = zext i8 [[X:%.*]] to i32
+; CHECK-NEXT: [[ZEXT_Y:%.*]] = zext i8 [[Y:%.*]] to i32
+; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[ZEXT_X]], [[ZEXT_Y]]
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[SHL]] to i16
+; CHECK-NEXT: ret i16 [[TRUNC]]
+;
+ %zext.x = zext i8 %x to i32
+ %zext.y = zext i8 %y to i32
+ %shl = shl i32 %zext.x, %zext.y
+ %trunc = trunc i32 %shl to i16
+ ret i16 %trunc
+}
+
+define i16 @shl_var_bounded_shift_amount(i8 %x, i8 %y) {
+; CHECK-LABEL: @shl_var_bounded_shift_amount(
+; CHECK-NEXT: [[ZEXT_X:%.*]] = zext i8 [[X:%.*]] to i16
+; CHECK-NEXT: [[ZEXT_Y:%.*]] = zext i8 [[Y:%.*]] to i16
+; CHECK-NEXT: [[AND:%.*]] = and i16 [[ZEXT_Y]], 15
+; CHECK-NEXT: [[SHL:%.*]] = shl i16 [[ZEXT_X]], [[AND]]
+; CHECK-NEXT: ret i16 [[SHL]]
+;
+ %zext.x = zext i8 %x to i32
+ %zext.y = zext i8 %y to i32
+ %and = and i32 %zext.y, 15
+ %shl = shl i32 %zext.x, %and
+ %trunc = trunc i32 %shl to i16
+ ret i16 %trunc
+}
+
+; Negative test (https://reviews.llvm.org/D108091#2950930)
+
+define i32 @shl_check_no_overflow(i32 %x, i16 %amt) {
+; CHECK-LABEL: @shl_check_no_overflow(
+; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[X:%.*]] to i64
+; CHECK-NEXT: [[SEXT:%.*]] = sext i16 [[AMT:%.*]] to i64
+; CHECK-NEXT: [[AND:%.*]] = and i64 [[SEXT]], 4294967295
+; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[ZEXT]], [[AND]]
+; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[SHL]] to i32
+; CHECK-NEXT: ret i32 [[TRUNC]]
+;
+ %zext = zext i32 %x to i64
+ %sext = sext i16 %amt to i64
+ %and = and i64 %sext, 4294967295
+ %shl = shl i64 %zext, %and
+ %trunc = trunc i64 %shl to i32
+ ret i32 %trunc
+}
+
+define <2 x i16> @shl_vector(<2 x i8> %x) {
+; CHECK-LABEL: @shl_vector(
+; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i16>
+; CHECK-NEXT: [[S:%.*]] = shl <2 x i16> [[Z]], <i16 4, i16 10>
+; CHECK-NEXT: ret <2 x i16> [[S]]
+;
+ %z = zext <2 x i8> %x to <2 x i32>
+ %s = shl <2 x i32> %z, <i32 4, i32 10>
+ %t = trunc <2 x i32> %s to <2 x i16>
+ ret <2 x i16> %t
+}
+
+; Negative test - can only fold to <2 x i16>, requiring new vector type
+
+define <2 x i8> @shl_vector_no_new_vector_type(<2 x i8> %x) {
+; CHECK-LABEL: @shl_vector_no_new_vector_type(
+; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
+; CHECK-NEXT: [[S:%.*]] = shl <2 x i32> [[Z]], <i32 4, i32 10>
+; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S]] to <2 x i8>
+; CHECK-NEXT: ret <2 x i8> [[T]]
+;
+ %z = zext <2 x i8> %x to <2 x i32>
+ %s = shl <2 x i32> %z, <i32 4, i32 10>
+ %t = trunc <2 x i32> %s to <2 x i8>
+ ret <2 x i8> %t
+}
+
+; Negative test
+
+define <2 x i16> @shl_vector_large_shift_amount(<2 x i8> %x) {
+; CHECK-LABEL: @shl_vector_large_shift_amount(
+; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
+; CHECK-NEXT: [[S:%.*]] = shl <2 x i32> [[Z]], <i32 16, i32 5>
+; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S]] to <2 x i16>
+; CHECK-NEXT: ret <2 x i16> [[T]]
+;
+ %z = zext <2 x i8> %x to <2 x i32>
+ %s = shl <2 x i32> %z, <i32 16, i32 5>
+ %t = trunc <2 x i32> %s to <2 x i16>
+ ret <2 x i16> %t
+}
+
+define i16 @shl_nuw(i8 %x) {
+; CHECK-LABEL: @shl_nuw(
+; CHECK-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i16
+; CHECK-NEXT: [[S:%.*]] = shl i16 [[Z]], 15
+; CHECK-NEXT: ret i16 [[S]]
+;
+ %z = zext i8 %x to i32
+ %s = shl nuw i32 %z, 15
+ %t = trunc i32 %s to i16
+ ret i16 %t
+}
+
+define i16 @shl_nsw(i8 %x) {
+; CHECK-LABEL: @shl_nsw(
+; CHECK-NEXT: [[Z:%.*]] = zext i8 [[X:%.*]] to i16
+; CHECK-NEXT: [[S:%.*]] = shl i16 [[Z]], 15
+; CHECK-NEXT: ret i16 [[S]]
+;
+ %z = zext i8 %x to i32
+ %s = shl nsw i32 %z, 15
+ %t = trunc i32 %s to i16
+ ret i16 %t
+}
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