[llvm] 3118926 - [GlobalISel] Add a G_LROUND instruction
Jessica Paquette via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 19 17:06:34 PDT 2021
Author: Jessica Paquette
Date: 2021-08-19T17:06:24-07:00
New Revision: 311892648391ad8dce19d605f7b6c7b8a89d2430
URL: https://github.com/llvm/llvm-project/commit/311892648391ad8dce19d605f7b6c7b8a89d2430
DIFF: https://github.com/llvm/llvm-project/commit/311892648391ad8dce19d605f7b6c7b8a89d2430.diff
LOG: [GlobalISel] Add a G_LROUND instruction
Meant to represent the `@llvm.lround.*` family.
Add the opcode, docs, and verification.
Differential Revision: https://reviews.llvm.org/D108417
Added:
llvm/test/MachineVerifier/test_g_lround.mir
Modified:
llvm/docs/GlobalISel/GenericOpcode.rst
llvm/include/llvm/Support/TargetOpcodes.def
llvm/include/llvm/Target/GenericOpcodes.td
llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
llvm/lib/CodeGen/MachineVerifier.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
Removed:
################################################################################
diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst
index 4abe069b10e7a..e08e59e1dd2b4 100644
--- a/llvm/docs/GlobalISel/GenericOpcode.rst
+++ b/llvm/docs/GlobalISel/GenericOpcode.rst
@@ -573,6 +573,19 @@ G_INTRINSIC_ROUND
Returns the operand rounded to the nearest integer.
+G_LROUND
+^^^^^^^^
+
+Returns the source operand rounded to the nearest integer with ties away from
+zero.
+
+See the LLVM LangRef entry on '``llvm.lround.*'`` for details on behaviour.
+
+.. code-block:: none
+
+ %rounded_32:_(s32) = G_LROUND %round_me:_(s64)
+ %rounded_64:_(s64) = G_LROUND %round_me:_(s64)
+
Vector Specific Operations
--------------------------
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index 6ba679b3d2a77..99603b914a264 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -652,6 +652,8 @@ HANDLE_TARGET_OPCODE(G_UMAX)
/// Generic integer absolute value.
HANDLE_TARGET_OPCODE(G_ABS)
+HANDLE_TARGET_OPCODE(G_LROUND)
+
/// Generic BRANCH instruction. This is an unconditional branch.
HANDLE_TARGET_OPCODE(G_BR)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index 4d0b91e3b6be2..28aecd40a7cf0 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -232,6 +232,12 @@ def G_ISNAN: GenericInstruction {
let hasSideEffects = false;
}
+def G_LROUND: GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type1:$src);
+ let hasSideEffects = false;
+}
+
//------------------------------------------------------------------------------
// Binary ops.
//------------------------------------------------------------------------------
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index 8a5052401e9b3..647b694b1ba1c 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -144,6 +144,7 @@ def : GINodeEquiv<G_FMAXNUM_IEEE, fmaxnum_ieee>;
def : GINodeEquiv<G_READCYCLECOUNTER, readcyclecounter>;
def : GINodeEquiv<G_ROTR, rotr>;
def : GINodeEquiv<G_ROTL, rotl>;
+def : GINodeEquiv<G_LROUND, lround>;
def : GINodeEquiv<G_STRICT_FADD, strict_fadd>;
def : GINodeEquiv<G_STRICT_FSUB, strict_fsub>;
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index b527833e8f3ac..b15e4881f807d 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1615,6 +1615,13 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
break;
}
+ case TargetOpcode::G_LROUND: {
+ if (!MRI->getType(MI->getOperand(0).getReg()).isScalar() ||
+ !MRI->getType(MI->getOperand(1).getReg()).isScalar())
+ report("lround only supports scalars", MI);
+ break;
+ }
+
default:
break;
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index ea35308197794..3bf999e7d82ab 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -526,6 +526,9 @@
# DEBUG-NEXT: G_ABS (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: G_LROUND (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: G_BR (opcode {{[0-9]+}}): 0 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
diff --git a/llvm/test/MachineVerifier/test_g_lround.mir b/llvm/test/MachineVerifier/test_g_lround.mir
new file mode 100644
index 0000000000000..2f999b4823161
--- /dev/null
+++ b/llvm/test/MachineVerifier/test_g_lround.mir
@@ -0,0 +1,23 @@
+#RUN: not --crash llc -march=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: aarch64-registered-target
+
+---
+name: test_lround
+legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+liveins:
+body: |
+ bb.0:
+ liveins: $x0, $q0
+ %ptr:_(p0) = COPY $x0
+ %vector:_(<2 x s64>) = COPY $q0
+
+ ; CHECK: Bad machine code: lround only supports scalars
+ ; CHECK: instruction: %no_ptrs:_(s32) = G_LROUND %ptr:_(p0)
+ %no_ptrs:_(s32) = G_LROUND %ptr:_(p0)
+
+ ; CHECK: Bad machine code: lround only supports scalars
+ ; CHECK: instruction: %no_vectors:_(s32) = G_LROUND %vector:_(<2 x s64>)
+ %no_vectors:_(s32) = G_LROUND %vector:_(<2 x s64>)
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