[PATCH] D108276: [AArch64][GlobalISel] Add G_VECREDUCE fewerElements support for full scalarization.

[Amara Emerson via Phabricator via llvm-commits]

aemerson added inline comments.


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Comment at: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:4690
+  unsigned Opc = MI.getOpcode();
+  assert(Opc != TargetOpcode::G_VECREDUCE_SEQ_FADD &&
+         Opc != TargetOpcode::G_VECREDUCE_SEQ_FMUL &&
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paquette wrote:
> Maybe in a later patch it would be good to add a wrapper for these instructions which has an `isSequential` function
Sure.


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Comment at: llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp:701
+            LLT SrcTy = Q.Types[1];
+            if (SrcTy.isScalar())
+              return false;
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paquette wrote:
> Can this happen? Looks like the MachineVerifier doesn't permit scalar sources?
In this patch I'm also relaxing that constraint in the verifier, because <1 x sN> vectors are indistinguishable from scalars in LLT.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108276/new/

https://reviews.llvm.org/D108276