[llvm] be6c49e - [WebAssembly] Add explicit casts to silence -Wc++11-narrowing

[Thomas Lively via llvm-commits]

Author: Thomas Lively
Date: 2021-08-19T16:00:07-07:00
New Revision: be6c49e743d5ceaced202d29d51d94b2d210240a

URL: https://github.com/llvm/llvm-project/commit/be6c49e743d5ceaced202d29d51d94b2d210240a
DIFF: https://github.com/llvm/llvm-project/commit/be6c49e743d5ceaced202d29d51d94b2d210240a.diff

LOG: [WebAssembly] Add explicit casts to silence -Wc++11-narrowing

Added: 
    

Modified: 
    llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 59b4812dc056..29f68d476e47 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -1836,8 +1836,9 @@ static SDValue LowerConvertLow(SDValue Op, SelectionDAG &DAG) {
   auto Src = LHSSrcVec;
   if (LHSIndex != 0 || RHSIndex != 1 || LHSSrcVec != RHSSrcVec) {
     // Shuffle the source vector so that the converted lanes are the low lanes.
-    Src = DAG.getVectorShuffle(ExpectedSrcVT, DL, LHSSrcVec, RHSSrcVec,
-                               {LHSIndex, RHSIndex + 4, -1, -1});
+    Src = DAG.getVectorShuffle(
+        ExpectedSrcVT, DL, LHSSrcVec, RHSSrcVec,
+        {static_cast<int>(LHSIndex), static_cast<int>(RHSIndex) + 4, -1, -1});
   }
   return DAG.getNode(LHSOpcode, DL, MVT::v2f64, Src);
 }