[llvm] 9e40a32 - [RISCV][test] Add new tests for add optimization in the zba extension

[Ben Shi via llvm-commits]

Author: Ben Shi
Date: 2021-08-19T19:59:23+08:00
New Revision: 9e40a326208254ddf288b5f735794a7ee1e8dbc4

URL: https://github.com/llvm/llvm-project/commit/9e40a326208254ddf288b5f735794a7ee1e8dbc4
DIFF: https://github.com/llvm/llvm-project/commit/9e40a326208254ddf288b5f735794a7ee1e8dbc4.diff

LOG: [RISCV][test] Add new tests for add optimization in the zba extension

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D108188

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rv32zba.ll
    llvm/test/CodeGen/RISCV/rv64zba.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rv32zba.ll b/llvm/test/CodeGen/RISCV/rv32zba.ll
index 4a42bb056fd1..f0a030045176 100644
--- a/llvm/test/CodeGen/RISCV/rv32zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zba.ll
@@ -739,3 +739,53 @@ define i32 @mul4104(i32 %a) {
   %c = mul i32 %a, 4104
   ret i32 %c
 }
+
+define i32 @add4104(i32 %a) {
+; RV32I-LABEL: add4104:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 1
+; RV32I-NEXT:    addi a1, a1, 8
+; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32B-LABEL: add4104:
+; RV32B:       # %bb.0:
+; RV32B-NEXT:    lui a1, 1
+; RV32B-NEXT:    addi a1, a1, 8
+; RV32B-NEXT:    add a0, a0, a1
+; RV32B-NEXT:    ret
+;
+; RV32ZBA-LABEL: add4104:
+; RV32ZBA:       # %bb.0:
+; RV32ZBA-NEXT:    lui a1, 1
+; RV32ZBA-NEXT:    addi a1, a1, 8
+; RV32ZBA-NEXT:    add a0, a0, a1
+; RV32ZBA-NEXT:    ret
+  %c = add i32 %a, 4104
+  ret i32 %c
+}
+
+define i32 @add8208(i32 %a) {
+; RV32I-LABEL: add8208:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 2
+; RV32I-NEXT:    addi a1, a1, 16
+; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32B-LABEL: add8208:
+; RV32B:       # %bb.0:
+; RV32B-NEXT:    lui a1, 2
+; RV32B-NEXT:    addi a1, a1, 16
+; RV32B-NEXT:    add a0, a0, a1
+; RV32B-NEXT:    ret
+;
+; RV32ZBA-LABEL: add8208:
+; RV32ZBA:       # %bb.0:
+; RV32ZBA-NEXT:    lui a1, 2
+; RV32ZBA-NEXT:    addi a1, a1, 16
+; RV32ZBA-NEXT:    add a0, a0, a1
+; RV32ZBA-NEXT:    ret
+  %c = add i32 %a, 8208
+  ret i32 %c
+}

diff  --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
index 1cf572d50881..16ce6196d836 100644
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -1310,3 +1310,53 @@ define signext i32 @mulw576(i32 signext %a) {
   %c = mul i32 %a, 576
   ret i32 %c
 }
+
+define i64 @add4104(i64 %a) {
+; RV64I-LABEL: add4104:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 1
+; RV64I-NEXT:    addiw a1, a1, 8
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64B-LABEL: add4104:
+; RV64B:       # %bb.0:
+; RV64B-NEXT:    lui a1, 1
+; RV64B-NEXT:    addiw a1, a1, 8
+; RV64B-NEXT:    add a0, a0, a1
+; RV64B-NEXT:    ret
+;
+; RV64ZBA-LABEL: add4104:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    lui a1, 1
+; RV64ZBA-NEXT:    addiw a1, a1, 8
+; RV64ZBA-NEXT:    add a0, a0, a1
+; RV64ZBA-NEXT:    ret
+  %c = add i64 %a, 4104
+  ret i64 %c
+}
+
+define i64 @add8208(i64 %a) {
+; RV64I-LABEL: add8208:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 2
+; RV64I-NEXT:    addiw a1, a1, 16
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64B-LABEL: add8208:
+; RV64B:       # %bb.0:
+; RV64B-NEXT:    lui a1, 2
+; RV64B-NEXT:    addiw a1, a1, 16
+; RV64B-NEXT:    add a0, a0, a1
+; RV64B-NEXT:    ret
+;
+; RV64ZBA-LABEL: add8208:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    lui a1, 2
+; RV64ZBA-NEXT:    addiw a1, a1, 16
+; RV64ZBA-NEXT:    add a0, a0, a1
+; RV64ZBA-NEXT:    ret
+  %c = add i64 %a, 8208
+  ret i64 %c
+}