[PATCH] D108355: [AggressiveInstCombine] Add arithmetic shift right instr to `TruncInstCombine` DAG

[Anton Afanasyev via Phabricator via llvm-commits]

anton-afanasyev created this revision.
anton-afanasyev added reviewers: lebedev.ri, spatel, RKSimon.
Herald added a subscriber: hiraditya.
anton-afanasyev requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Add `ashr` instruction to the DAG post-dominated by `trunc`, allowing
`TruncInstCombine` to reduce bitwidth of expressions containing
these instructions.

We should be shifting by less than the target bitwidth.
Also it is sufficient to require that all truncated bits
of the value-to-be-shifted are zeros, and we can replace
truncated `ashr` with `lshr`: https://alive2.llvm.org/ce/z/iQZfji

Part of https://reviews.llvm.org/D107766


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108355

Files:
  llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp
  llvm/test/Transforms/AggressiveInstCombine/trunc_shifts.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D108355.367427.patch
Type: text/x-patch
Size: 8963 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210819/c92d4c83/attachment.bin>