[PATCH] D105267: [X86] AVX512FP16 instructions enabling 4/6

[Pengfei Wang via Phabricator via llvm-commits]

pengfei added a comment.

Thanks Yuanke and Craig.



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Comment at: llvm/lib/Target/X86/X86InstrAVX512.td:9279
 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
+                         X86FoldableSchedWrite sched, X86VectorVTInfo _,
----------------
LuoYuanke wrote:
> The name is not precise now. We now support non-fp14 node. Also update the comments.
The precision of FP16 happens to 2-14 too, so the name is precise.


================
Comment at: llvm/lib/Target/X86/X86InstrAVX512.td:13476
+
+multiclass avx512_fp16_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode,
+                                   X86SchedWriteWidths sched> {
----------------
LuoYuanke wrote:
> Why not merge this class to avx512_fp14_p_vl_all? Is it because it doesn't use MXCSR?
Not only the use of MXCSR but also naming. Anyway, I merged them.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D105267/new/

https://reviews.llvm.org/D105267