[PATCH] D105853: [ISel] Expand saddsat and ssubsat via asr and xor

[Dave Green via Phabricator via llvm-commits]

dmgreen updated this revision to Diff 367258.
dmgreen added a comment.

Custom lower v2i64 too, under at least SSE4.1, which seems to be an improvement and reduces a lot of the remaining vector size increases. It does mean changing another isOperationLegalOrCustom -> isOperationLegal to prevent an infinite loop between custom lowering saddsat and saddo.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105853/new/

https://reviews.llvm.org/D105853

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sadd_sat.ll
  llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
  llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/ssub_sat.ll
  llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
  llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
  llvm/test/CodeGen/AMDGPU/saddsat.ll
  llvm/test/CodeGen/AMDGPU/ssubsat.ll
  llvm/test/CodeGen/ARM/qdadd.ll
  llvm/test/CodeGen/ARM/sadd_sat.ll
  llvm/test/CodeGen/ARM/sadd_sat_plus.ll
  llvm/test/CodeGen/ARM/ssub_sat.ll
  llvm/test/CodeGen/ARM/ssub_sat_plus.ll
  llvm/test/CodeGen/PowerPC/sat-add.ll
  llvm/test/CodeGen/RISCV/sadd_sat.ll
  llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
  llvm/test/CodeGen/RISCV/ssub_sat.ll
  llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
  llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
  llvm/test/CodeGen/X86/combine-add-ssat.ll
  llvm/test/CodeGen/X86/sadd_sat.ll
  llvm/test/CodeGen/X86/sadd_sat_plus.ll
  llvm/test/CodeGen/X86/sadd_sat_vec.ll
  llvm/test/CodeGen/X86/ssub_sat.ll
  llvm/test/CodeGen/X86/ssub_sat_plus.ll
  llvm/test/CodeGen/X86/ssub_sat_vec.ll

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