[llvm] 6d7ea59 - [RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 18 10:44:31 PDT 2021
Author: Craig Topper
Date: 2021-08-18T10:44:25-07:00
New Revision: 6d7ea597efee6398c4bf09a0d60a870c67ef2764
URL: https://github.com/llvm/llvm-project/commit/6d7ea597efee6398c4bf09a0d60a870c67ef2764
DIFF: https://github.com/llvm/llvm-project/commit/6d7ea597efee6398c4bf09a0d60a870c67ef2764.diff
LOG: [RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS.
We already do this for non-constants RHS. This just removes the
special case. I believe the special case may have been needed
because the ANY_EXTEND of a constant used to create zero extended
constants, but we recently changed that to produce sign extended
constants.
D107658 is needed to prevent some regressions.
Reviewed By: luismarques
Differential Revision: https://reviews.llvm.org/D107697
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/add-imm.ll
llvm/test/CodeGen/RISCV/alu32.ll
llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
llvm/test/CodeGen/RISCV/mul.ll
llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
llvm/test/CodeGen/RISCV/setcc-logic.ll
llvm/test/CodeGen/RISCV/split-offsets.ll
llvm/test/CodeGen/RISCV/vararg.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 8da71a1695a0..ec82e6ea927a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -5053,8 +5053,6 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
case ISD::SUB:
assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
"Unexpected custom legalisation");
- if (N->getOperand(1).getOpcode() == ISD::Constant)
- return;
Results.push_back(customLegalizeToWOpWithSExt(N, DAG));
break;
case ISD::SHL:
diff --git a/llvm/test/CodeGen/RISCV/add-imm.ll b/llvm/test/CodeGen/RISCV/add-imm.ll
index c6727e79d394..970f8098ded0 100644
--- a/llvm/test/CodeGen/RISCV/add-imm.ll
+++ b/llvm/test/CodeGen/RISCV/add-imm.ll
@@ -14,7 +14,7 @@ define i32 @add_positive_low_bound_reject(i32 %a) nounwind {
;
; RV64I-LABEL: add_positive_low_bound_reject:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 2047
+; RV64I-NEXT: addiw a0, a0, 2047
; RV64I-NEXT: ret
%1 = add i32 %a, 2047
ret i32 %1
@@ -29,8 +29,8 @@ define i32 @add_positive_low_bound_accept(i32 %a) nounwind {
;
; RV64I-LABEL: add_positive_low_bound_accept:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 1024
-; RV64I-NEXT: addi a0, a0, 1024
+; RV64I-NEXT: addiw a0, a0, 1024
+; RV64I-NEXT: addiw a0, a0, 1024
; RV64I-NEXT: ret
%1 = add i32 %a, 2048
ret i32 %1
@@ -45,8 +45,8 @@ define i32 @add_positive_high_bound_accept(i32 %a) nounwind {
;
; RV64I-LABEL: add_positive_high_bound_accept:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 2047
-; RV64I-NEXT: addi a0, a0, 2047
+; RV64I-NEXT: addiw a0, a0, 2047
+; RV64I-NEXT: addiw a0, a0, 2047
; RV64I-NEXT: ret
%1 = add i32 %a, 4094
ret i32 %1
@@ -64,7 +64,7 @@ define i32 @add_positive_high_bound_reject(i32 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1
; RV64I-NEXT: addiw a1, a1, -1
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
%1 = add i32 %a, 4095
ret i32 %1
@@ -78,7 +78,7 @@ define i32 @add_negative_high_bound_reject(i32 %a) nounwind {
;
; RV64I-LABEL: add_negative_high_bound_reject:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, -2048
+; RV64I-NEXT: addiw a0, a0, -2048
; RV64I-NEXT: ret
%1 = add i32 %a, -2048
ret i32 %1
@@ -93,8 +93,8 @@ define i32 @add_negative_high_bound_accept(i32 %a) nounwind {
;
; RV64I-LABEL: add_negative_high_bound_accept:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, -1025
-; RV64I-NEXT: addi a0, a0, -1024
+; RV64I-NEXT: addiw a0, a0, -1025
+; RV64I-NEXT: addiw a0, a0, -1024
; RV64I-NEXT: ret
%1 = add i32 %a, -2049
ret i32 %1
@@ -109,8 +109,8 @@ define i32 @add_negative_low_bound_accept(i32 %a) nounwind {
;
; RV64I-LABEL: add_negative_low_bound_accept:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, -2048
-; RV64I-NEXT: addi a0, a0, -2048
+; RV64I-NEXT: addiw a0, a0, -2048
+; RV64I-NEXT: addiw a0, a0, -2048
; RV64I-NEXT: ret
%1 = add i32 %a, -4096
ret i32 %1
@@ -128,7 +128,7 @@ define i32 @add_negative_low_bound_reject(i32 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 1048575
; RV64I-NEXT: addiw a1, a1, -1
-; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: ret
%1 = add i32 %a, -4097
ret i32 %1
@@ -143,8 +143,8 @@ define i32 @add32_accept(i32 %a) nounwind {
;
; RV64I-LABEL: add32_accept:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 1500
-; RV64I-NEXT: addi a0, a0, 1499
+; RV64I-NEXT: addiw a0, a0, 1500
+; RV64I-NEXT: addiw a0, a0, 1499
; RV64I-NEXT: ret
%1 = add i32 %a, 2999
ret i32 %1
diff --git a/llvm/test/CodeGen/RISCV/alu32.ll b/llvm/test/CodeGen/RISCV/alu32.ll
index b7cba24a43cd..f498ff4973a2 100644
--- a/llvm/test/CodeGen/RISCV/alu32.ll
+++ b/llvm/test/CodeGen/RISCV/alu32.ll
@@ -18,7 +18,7 @@ define i32 @addi(i32 %a) nounwind {
;
; RV64I-LABEL: addi:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 1
+; RV64I-NEXT: addiw a0, a0, 1
; RV64I-NEXT: ret
%1 = add i32 %a, 1
ret i32 %1
diff --git a/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll b/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
index 7fe7e8eb01cf..f612b533008e 100644
--- a/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
+++ b/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
@@ -41,7 +41,7 @@ define double @func(double %d, i32 %n) nounwind {
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: beqz a2, .LBB0_2
; RV64IFD-NEXT: # %bb.1: # %if.else
-; RV64IFD-NEXT: addi a1, a1, -1
+; RV64IFD-NEXT: addiw a1, a1, -1
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: fsd ft0, 0(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call func at plt
diff --git a/llvm/test/CodeGen/RISCV/mul.ll b/llvm/test/CodeGen/RISCV/mul.ll
index d26eb1065332..9be5cb1b6d14 100644
--- a/llvm/test/CodeGen/RISCV/mul.ll
+++ b/llvm/test/CodeGen/RISCV/mul.ll
@@ -782,7 +782,7 @@ define i32 @muli32_p384(i32 %a) nounwind {
; RV64IM-LABEL: muli32_p384:
; RV64IM: # %bb.0:
; RV64IM-NEXT: addi a1, zero, 384
-; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: ret
%1 = mul i32 %a, 384
ret i32 %1
@@ -818,7 +818,7 @@ define i32 @muli32_p12288(i32 %a) nounwind {
; RV64IM-LABEL: muli32_p12288:
; RV64IM: # %bb.0:
; RV64IM-NEXT: lui a1, 3
-; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: ret
%1 = mul i32 %a, 12288
ret i32 %1
@@ -954,7 +954,7 @@ define i32 @muli32_m4352(i32 %a) nounwind {
; RV64IM: # %bb.0:
; RV64IM-NEXT: lui a1, 1048575
; RV64IM-NEXT: addiw a1, a1, -256
-; RV64IM-NEXT: mul a0, a0, a1
+; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: ret
%1 = mul i32 %a, -4352
ret i32 %1
diff --git a/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll b/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
index 54d9aeabfc73..31d59ea1367b 100644
--- a/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
@@ -1333,7 +1333,7 @@ define zeroext i32 @zext_sraw_zext_zext(i32 zeroext %a, i32 zeroext %b) nounwind
define i32 @aext_addiw_aext(i32 %a) nounwind {
; RV64I-LABEL: aext_addiw_aext:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 1
+; RV64I-NEXT: addiw a0, a0, 1
; RV64I-NEXT: ret
%1 = add i32 %a, 1
ret i32 %1
@@ -1342,7 +1342,7 @@ define i32 @aext_addiw_aext(i32 %a) nounwind {
define i32 @aext_addiw_sext(i32 signext %a) nounwind {
; RV64I-LABEL: aext_addiw_sext:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 2
+; RV64I-NEXT: addiw a0, a0, 2
; RV64I-NEXT: ret
%1 = add i32 %a, 2
ret i32 %1
@@ -1351,7 +1351,7 @@ define i32 @aext_addiw_sext(i32 signext %a) nounwind {
define i32 @aext_addiw_zext(i32 zeroext %a) nounwind {
; RV64I-LABEL: aext_addiw_zext:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, 3
+; RV64I-NEXT: addiw a0, a0, 3
; RV64I-NEXT: ret
%1 = add i32 %a, 3
ret i32 %1
diff --git a/llvm/test/CodeGen/RISCV/setcc-logic.ll b/llvm/test/CodeGen/RISCV/setcc-logic.ll
index 23c0129e168b..2107c17d1ec0 100644
--- a/llvm/test/CodeGen/RISCV/setcc-logic.ll
+++ b/llvm/test/CodeGen/RISCV/setcc-logic.ll
@@ -84,9 +84,8 @@ define i1 @and_icmps_const_1bit_
diff (i32 %x) nounwind {
;
; RV64I-LABEL: and_icmps_const_1bit_
diff :
; RV64I: # %bb.0:
-; RV64I-NEXT: addi a0, a0, -44
+; RV64I-NEXT: addiw a0, a0, -44
; RV64I-NEXT: andi a0, a0, -17
-; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
%a = icmp ne i32 %x, 44
diff --git a/llvm/test/CodeGen/RISCV/split-offsets.ll b/llvm/test/CodeGen/RISCV/split-offsets.ll
index 2d943ae71cd4..9f92edcce167 100644
--- a/llvm/test/CodeGen/RISCV/split-offsets.ll
+++ b/llvm/test/CodeGen/RISCV/split-offsets.ll
@@ -87,7 +87,7 @@ define void @test2([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
; RV64I-NEXT: bge a4, a2, .LBB1_2
; RV64I-NEXT: .LBB1_1: # %while_body
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: addi a4, a3, 1
+; RV64I-NEXT: addiw a4, a3, 1
; RV64I-NEXT: sw a4, 0(a1)
; RV64I-NEXT: sw a3, 4(a1)
; RV64I-NEXT: sw a4, 0(a0)
diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll
index 59782bd448b6..219494b0ea6d 100644
--- a/llvm/test/CodeGen/RISCV/vararg.ll
+++ b/llvm/test/CodeGen/RISCV/vararg.ll
@@ -567,7 +567,7 @@ define i64 @va2(i8 *%fmt, ...) nounwind {
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, sp, 24
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 8(sp)
-; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 7
+; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, 7
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a0, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: srli a1, a1, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a1, a1, 8
@@ -596,7 +596,7 @@ define i64 @va2(i8 *%fmt, ...) nounwind {
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, s0, 8
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, -24(s0)
-; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 7
+; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a0, a0, 7
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a0, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: srli a1, a1, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a1, a1, 8
@@ -893,7 +893,7 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: lw a0, 8(sp)
; LP64-LP64F-LP64D-FPELIM-NEXT: sd a2, 16(sp)
-; LP64-LP64F-LP64D-FPELIM-NEXT: addi a0, a0, 7
+; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, 7
; LP64-LP64F-LP64D-FPELIM-NEXT: slli a2, a0, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: srli a2, a2, 32
; LP64-LP64F-LP64D-FPELIM-NEXT: addi a2, a2, 8
@@ -922,7 +922,7 @@ define i64 @va3(i32 %a, i64 %b, ...) nounwind {
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: lw a0, -24(s0)
; LP64-LP64F-LP64D-WITHFP-NEXT: sd a2, 0(s0)
-; LP64-LP64F-LP64D-WITHFP-NEXT: addi a0, a0, 7
+; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a0, a0, 7
; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a0, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: srli a2, a2, 32
; LP64-LP64F-LP64D-WITHFP-NEXT: addi a2, a2, 8
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