[PATCH] D108201: [AggressiveInstCombine] Add logical shift right instr to `TruncInstCombine` DAG

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In D108201#2951907 <https://reviews.llvm.org/D108201#2951907>, @anton-afanasyev wrote:

> Rebase after `shl` bugfix

Add tests similar to 0988488ed461 <https://reviews.llvm.org/rG0988488ed461f5a862f23f9840e0750bef07f11c> (multiple widths) and 803270c0c691 <https://reviews.llvm.org/rG803270c0c691ad0dbf8ac91492c79aad9e0d023d> (64-bit) for lshr patterns?



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Comment at: llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp:295-296
+        KnownBits KnownLHS = computeKnownBits(I->getOperand(0), DL);
+        MinBitWidth = std::max(MinBitWidth,
+                               SrcBitWidth - KnownLHS.countMinLeadingZeros());
+      }
----------------
This wasn't updated with the suggested change to use getActiveBits().
IIUC, we can make this more efficient (avoid computeKnownBits in some cases) by hoisting the common check for MinBitWidth >= OrigBitWidth above the extra check for lshr:
      unsigned MinBitWidth = KnownRHS.getMaxValue()
                                 .uadd_sat(APInt(SrcBitWidth, 1))
                                 .getLimitedValue(SrcBitWidth);
      if (MinBitWidth >= OrigBitWidth)
        return nullptr;
      if (I->getOpcode() == Instruction::LShr) {
        KnownBits KnownLHS = computeKnownBits(I->getOperand(0), DL);
        if (KnownLHS.getMaxValue().getActiveBits() >= OrigBitWidth)
          return nullptr;
      }
      Itr.second.MinBitWidth = MinBitWidth;



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Comment at: llvm/test/Transforms/AggressiveInstCombine/trunc_shifts.ll:163
   %zext = zext i16 %x to i32
   %lshr = lshr i32 %zext, 16
   %trunc = trunc i32 %lshr to i16
----------------
Similar to the previous `shl` example - this is another simplification to 0 that isn't handled by -instsimplify (but regular -instcombine gets it).


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https://reviews.llvm.org/D108201