[PATCH] D107658: [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:1552
+      // we use SLLI+SRLI for zext.w.
+      if (Bits != 32 ||
+          cast<ConstantSDNode>(User->getOperand(1))->getZExtValue() < 32)
----------------
This != 32 is a bit weird, would expect it to be at least < 32. But I think you can instead do something more general (and I think also clearer) like:
```
if (Bits < XLen - cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
  return false;
```
(don't know if we need to care about SLLI with an immediate >= XLen; it's an illegal instruction so presumably shouldn't come out of *CodeGen* no matter what the input is?)


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:1566-1574
+      if (UI.getOperandNo() != 0 || Bits < 8)
+        return false;
+      break;
+    case RISCV::SH:
+      if (UI.getOperandNo() != 0 || Bits < 16)
+        return false;
+      break;
----------------
luismarques wrote:
> Are these Bits inequality comparisons correct?
Hm, indeed, I believe this one is wrong, and the others are correct? (Bits being how many bits you want to truncate the value to).

This just happens to work because x > 32 and x < 32 behave identically when you only use x=32.


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  https://reviews.llvm.org/D107658/new/

https://reviews.llvm.org/D107658