[PATCH] D108288: [LegalizeTypes][VP] Add promotion support for binary VP ops

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck created this revision.
frasercrmck added reviewers: RKSimon, craig.topper, spatel, simoll.
Herald added subscribers: rogfer01, luismarques, apazos, sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
frasercrmck requested review of this revision.
Herald added subscribers: llvm-commits, vkmr, MaskRay.
Herald added a project: LLVM.

This patch extends the preliminary support for vector-predicated (VP)
operation legalization to include promotion of illegal integer vector
types.

Integer promotion of binary VP operations is relatively simple and
piggy-backs on the non-VP logic, but passing the two extra mask and VP
operands through to the promoted operation.

Tests have been added to the RISC-V target to cover the basic scenarios
for integer promotion for both fixed- and scalable-vector types.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108288

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsra-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll

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