[llvm] a7ebc4d - [DAGCombiner] Teach isKnownToBeAPowerOfTwo handle SPLAT_VECTOR
Ben Shi via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 17 19:10:57 PDT 2021
Author: jacquesguan
Date: 2021-08-18T10:10:40+08:00
New Revision: a7ebc4d145892fd22442832549cb12c4b6920dea
URL: https://github.com/llvm/llvm-project/commit/a7ebc4d145892fd22442832549cb12c4b6920dea
DIFF: https://github.com/llvm/llvm-project/commit/a7ebc4d145892fd22442832549cb12c4b6920dea.diff
LOG: [DAGCombiner] Teach isKnownToBeAPowerOfTwo handle SPLAT_VECTOR
Make DAGCombine turn mul by power of 2 into shl for scalable vector.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D107883
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 1450bf0eafca3..59a3243742c28 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -3647,6 +3647,12 @@ bool SelectionDAG::isKnownToBeAPowerOfTwo(SDValue Val) const {
}))
return true;
+ // Is the operand of a splat vector a constant power of two?
+ if (Val.getOpcode() == ISD::SPLAT_VECTOR)
+ if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val->getOperand(0)))
+ if (C->getAPIntValue().zextOrTrunc(BitWidth).isPowerOf2())
+ return true;
+
// More could be done here, though the above checks are enough
// to handle some common cases.
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
index 644b84a3c88f0..bd01a919638c1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
@@ -736,6 +736,33 @@ define <vscale x 1 x i64> @vdivu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
ret <vscale x 1 x i64> %vc
}
+define <vscale x 1 x i64> @vdivu_vi_nxv1i64_1(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vdivu_vi_nxv1i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT: vsrl.vi v8, v8, 1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 2, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = udiv <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2
+define <vscale x 1 x i64> @vdivu_vi_nxv1i64_2(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
+; CHECK-LABEL: vdivu_vi_nxv1i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT: vadd.vi v25, v9, 4
+; CHECK-NEXT: vsrl.vv v8, v8, v25
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = shl <vscale x 1 x i64> %splat, %vb
+ %vd = udiv <vscale x 1 x i64> %va, %vc
+ ret <vscale x 1 x i64> %vd
+}
+
define <vscale x 2 x i64> @vdivu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-LABEL: vdivu_vv_nxv2i64:
; CHECK: # %bb.0:
@@ -788,6 +815,33 @@ define <vscale x 2 x i64> @vdivu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
ret <vscale x 2 x i64> %vc
}
+define <vscale x 2 x i64> @vdivu_vi_nxv2i64_1(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vdivu_vi_nxv2i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT: vsrl.vi v8, v8, 1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 2, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = udiv <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2
+define <vscale x 2 x i64> @vdivu_vi_nxv2i64_2(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
+; CHECK-LABEL: vdivu_vi_nxv2i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT: vadd.vi v26, v10, 4
+; CHECK-NEXT: vsrl.vv v8, v8, v26
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = shl <vscale x 2 x i64> %splat, %vb
+ %vd = udiv <vscale x 2 x i64> %va, %vc
+ ret <vscale x 2 x i64> %vd
+}
+
define <vscale x 4 x i64> @vdivu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-LABEL: vdivu_vv_nxv4i64:
; CHECK: # %bb.0:
@@ -840,6 +894,33 @@ define <vscale x 4 x i64> @vdivu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
ret <vscale x 4 x i64> %vc
}
+define <vscale x 4 x i64> @vdivu_vi_nxv4i64_1(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vdivu_vi_nxv4i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT: vsrl.vi v8, v8, 1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 2, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = udiv <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2
+define <vscale x 4 x i64> @vdivu_vi_nxv4i64_2(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
+; CHECK-LABEL: vdivu_vi_nxv4i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT: vadd.vi v28, v12, 4
+; CHECK-NEXT: vsrl.vv v8, v8, v28
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = shl <vscale x 4 x i64> %splat, %vb
+ %vd = udiv <vscale x 4 x i64> %va, %vc
+ ret <vscale x 4 x i64> %vd
+}
+
define <vscale x 8 x i64> @vdivu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-LABEL: vdivu_vv_nxv8i64:
; CHECK: # %bb.0:
@@ -892,3 +973,29 @@ define <vscale x 8 x i64> @vdivu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
ret <vscale x 8 x i64> %vc
}
+define <vscale x 8 x i64> @vdivu_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vdivu_vi_nxv8i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT: vsrl.vi v8, v8, 1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 2, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = udiv <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2
+define <vscale x 8 x i64> @vdivu_vi_nxv8i64_2(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: vdivu_vi_nxv8i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT: vadd.vi v16, v16, 4
+; CHECK-NEXT: vsrl.vv v8, v8, v16
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = shl <vscale x 8 x i64> %splat, %vb
+ %vd = udiv <vscale x 8 x i64> %va, %vc
+ ret <vscale x 8 x i64> %vd
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
index 2553832fd82fc..a351185ea6510 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
@@ -699,6 +699,33 @@ define <vscale x 1 x i64> @vdivu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
ret <vscale x 1 x i64> %vc
}
+define <vscale x 1 x i64> @vdivu_vi_nxv1i64_1(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vdivu_vi_nxv1i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT: vsrl.vi v8, v8, 1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 2, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = udiv <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2
+define <vscale x 1 x i64> @vdivu_vi_nxv1i64_2(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
+; CHECK-LABEL: vdivu_vi_nxv1i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT: vadd.vi v25, v9, 4
+; CHECK-NEXT: vsrl.vv v8, v8, v25
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = shl <vscale x 1 x i64> %splat, %vb
+ %vd = udiv <vscale x 1 x i64> %va, %vc
+ ret <vscale x 1 x i64> %vd
+}
+
define <vscale x 2 x i64> @vdivu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-LABEL: vdivu_vv_nxv2i64:
; CHECK: # %bb.0:
@@ -738,6 +765,33 @@ define <vscale x 2 x i64> @vdivu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
ret <vscale x 2 x i64> %vc
}
+define <vscale x 2 x i64> @vdivu_vi_nxv2i64_1(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vdivu_vi_nxv2i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT: vsrl.vi v8, v8, 1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 2, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = udiv <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2
+define <vscale x 2 x i64> @vdivu_vi_nxv2i64_2(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
+; CHECK-LABEL: vdivu_vi_nxv2i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT: vadd.vi v26, v10, 4
+; CHECK-NEXT: vsrl.vv v8, v8, v26
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = shl <vscale x 2 x i64> %splat, %vb
+ %vd = udiv <vscale x 2 x i64> %va, %vc
+ ret <vscale x 2 x i64> %vd
+}
+
define <vscale x 4 x i64> @vdivu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-LABEL: vdivu_vv_nxv4i64:
; CHECK: # %bb.0:
@@ -777,6 +831,33 @@ define <vscale x 4 x i64> @vdivu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
ret <vscale x 4 x i64> %vc
}
+define <vscale x 4 x i64> @vdivu_vi_nxv4i64_1(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vdivu_vi_nxv4i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT: vsrl.vi v8, v8, 1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 2, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = udiv <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2
+define <vscale x 4 x i64> @vdivu_vi_nxv4i64_2(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
+; CHECK-LABEL: vdivu_vi_nxv4i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT: vadd.vi v28, v12, 4
+; CHECK-NEXT: vsrl.vv v8, v8, v28
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = shl <vscale x 4 x i64> %splat, %vb
+ %vd = udiv <vscale x 4 x i64> %va, %vc
+ ret <vscale x 4 x i64> %vd
+}
+
define <vscale x 8 x i64> @vdivu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-LABEL: vdivu_vv_nxv8i64:
; CHECK: # %bb.0:
@@ -816,3 +897,29 @@ define <vscale x 8 x i64> @vdivu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
ret <vscale x 8 x i64> %vc
}
+define <vscale x 8 x i64> @vdivu_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vdivu_vi_nxv8i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT: vsrl.vi v8, v8, 1
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 2, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = udiv <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+; fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) if c is power of 2
+define <vscale x 8 x i64> @vdivu_vi_nxv8i64_2(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: vdivu_vi_nxv8i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT: vadd.vi v16, v16, 4
+; CHECK-NEXT: vsrl.vv v8, v8, v16
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = shl <vscale x 8 x i64> %splat, %vb
+ %vd = udiv <vscale x 8 x i64> %va, %vc
+ ret <vscale x 8 x i64> %vd
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll
index 787ded5b7bc08..c2ac91c7651cc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll
@@ -673,6 +673,30 @@ define <vscale x 1 x i64> @vmul_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
ret <vscale x 1 x i64> %vc
}
+define <vscale x 1 x i64> @vmul_vi_nxv1i64_1(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vmul_vi_nxv1i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 2, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = mul <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vmul_vi_nxv1i64_2(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vmul_vi_nxv1i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = mul <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
define <vscale x 2 x i64> @vmul_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-LABEL: vmul_vv_nxv2i64:
; CHECK: # %bb.0:
@@ -715,6 +739,30 @@ define <vscale x 2 x i64> @vmul_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
ret <vscale x 2 x i64> %vc
}
+define <vscale x 2 x i64> @vmul_vi_nxv2i64_1(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vmul_vi_nxv2i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 2, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = mul <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vmul_vi_nxv2i64_2(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vmul_vi_nxv2i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = mul <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
define <vscale x 4 x i64> @vmul_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-LABEL: vmul_vv_nxv4i64:
; CHECK: # %bb.0:
@@ -757,6 +805,30 @@ define <vscale x 4 x i64> @vmul_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
ret <vscale x 4 x i64> %vc
}
+define <vscale x 4 x i64> @vmul_vi_nxv4i64_1(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vmul_vi_nxv4i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 2, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = mul <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vmul_vi_nxv4i64_2(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vmul_vi_nxv4i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = mul <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
define <vscale x 8 x i64> @vmul_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-LABEL: vmul_vv_nxv8i64:
; CHECK: # %bb.0:
@@ -799,3 +871,26 @@ define <vscale x 8 x i64> @vmul_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
ret <vscale x 8 x i64> %vc
}
+define <vscale x 8 x i64> @vmul_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vmul_vi_nxv8i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 2, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = mul <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vmul_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vmul_vi_nxv8i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = mul <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv64.ll
index 51cae34ce648c..471442b8fee0f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv64.ll
@@ -666,6 +666,30 @@ define <vscale x 1 x i64> @vmul_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
ret <vscale x 1 x i64> %vc
}
+define <vscale x 1 x i64> @vmul_vi_nxv1i64_1(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vmul_vi_nxv1i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 2, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = mul <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vmul_vi_nxv1i64_2(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vmul_vi_nxv1i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = mul <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
define <vscale x 2 x i64> @vmul_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-LABEL: vmul_vv_nxv2i64:
; CHECK: # %bb.0:
@@ -701,6 +725,30 @@ define <vscale x 2 x i64> @vmul_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
ret <vscale x 2 x i64> %vc
}
+define <vscale x 2 x i64> @vmul_vi_nxv2i64_1(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vmul_vi_nxv2i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 2, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = mul <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vmul_vi_nxv2i64_2(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vmul_vi_nxv2i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = mul <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
define <vscale x 4 x i64> @vmul_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-LABEL: vmul_vv_nxv4i64:
; CHECK: # %bb.0:
@@ -736,6 +784,30 @@ define <vscale x 4 x i64> @vmul_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
ret <vscale x 4 x i64> %vc
}
+define <vscale x 4 x i64> @vmul_vi_nxv4i64_1(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vmul_vi_nxv4i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 2, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = mul <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vmul_vi_nxv4i64_2(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vmul_vi_nxv4i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = mul <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
define <vscale x 8 x i64> @vmul_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-LABEL: vmul_vv_nxv8i64:
; CHECK: # %bb.0:
@@ -771,3 +843,26 @@ define <vscale x 8 x i64> @vmul_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
ret <vscale x 8 x i64> %vc
}
+define <vscale x 8 x i64> @vmul_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vmul_vi_nxv8i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT: vadd.vv v8, v8, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 2, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = mul <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vmul_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vmul_vi_nxv8i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT: vsll.vi v8, v8, 4
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = mul <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll
index adea0f92dc334..a1c7920f5b6d9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll
@@ -750,6 +750,37 @@ define <vscale x 1 x i64> @vremu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
ret <vscale x 1 x i64> %vc
}
+; fold (urem x, pow2) -> (and x, pow2-1)
+define <vscale x 1 x i64> @vremu_vi_nxv1i64_1(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vremu_vi_nxv1i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT: vand.vi v8, v8, 15
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = urem <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+; fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
+define <vscale x 1 x i64> @vremu_vi_nxv1i64_2(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
+; CHECK-LABEL: vremu_vi_nxv1i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vsll.vv v25, v25, v9
+; CHECK-NEXT: vadd.vi v25, v25, -1
+; CHECK-NEXT: vand.vv v8, v8, v25
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = shl <vscale x 1 x i64> %splat, %vb
+ %vd = urem <vscale x 1 x i64> %va, %vc
+ ret <vscale x 1 x i64> %vd
+}
+
define <vscale x 2 x i64> @vremu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-LABEL: vremu_vv_nxv2i64:
; CHECK: # %bb.0:
@@ -804,6 +835,37 @@ define <vscale x 2 x i64> @vremu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
ret <vscale x 2 x i64> %vc
}
+; fold (urem x, pow2) -> (and x, pow2-1)
+define <vscale x 2 x i64> @vremu_vi_nxv2i64_1(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vremu_vi_nxv2i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT: vand.vi v8, v8, 15
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = urem <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+; fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
+define <vscale x 2 x i64> @vremu_vi_nxv2i64_2(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
+; CHECK-LABEL: vremu_vi_nxv2i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vsll.vv v26, v26, v10
+; CHECK-NEXT: vadd.vi v26, v26, -1
+; CHECK-NEXT: vand.vv v8, v8, v26
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = shl <vscale x 2 x i64> %splat, %vb
+ %vd = urem <vscale x 2 x i64> %va, %vc
+ ret <vscale x 2 x i64> %vd
+}
+
define <vscale x 4 x i64> @vremu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-LABEL: vremu_vv_nxv4i64:
; CHECK: # %bb.0:
@@ -858,6 +920,37 @@ define <vscale x 4 x i64> @vremu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
ret <vscale x 4 x i64> %vc
}
+; fold (urem x, pow2) -> (and x, pow2-1)
+define <vscale x 4 x i64> @vremu_vi_nxv4i64_1(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vremu_vi_nxv4i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT: vand.vi v8, v8, 15
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = urem <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+;fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
+define <vscale x 4 x i64> @vremu_vi_nxv4i64_2(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
+; CHECK-LABEL: vremu_vi_nxv4i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; CHECK-NEXT: vmv.v.x v28, a0
+; CHECK-NEXT: vsll.vv v28, v28, v12
+; CHECK-NEXT: vadd.vi v28, v28, -1
+; CHECK-NEXT: vand.vv v8, v8, v28
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = shl <vscale x 4 x i64> %splat, %vb
+ %vd = urem <vscale x 4 x i64> %va, %vc
+ ret <vscale x 4 x i64> %vd
+}
+
define <vscale x 8 x i64> @vremu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-LABEL: vremu_vv_nxv8i64:
; CHECK: # %bb.0:
@@ -911,3 +1004,34 @@ define <vscale x 8 x i64> @vremu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
%vc = urem <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i64> %vc
}
+
+; fold (urem x, pow2) -> (and x, pow2-1)
+define <vscale x 8 x i64> @vremu_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vremu_vi_nxv8i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT: vand.vi v8, v8, 15
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = urem <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+; fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
+define <vscale x 8 x i64> @vremu_vi_nxv8i64_2(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: vremu_vi_nxv8i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vsll.vv v16, v24, v16
+; CHECK-NEXT: vadd.vi v16, v16, -1
+; CHECK-NEXT: vand.vv v8, v8, v16
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = shl <vscale x 8 x i64> %splat, %vb
+ %vd = urem <vscale x 8 x i64> %va, %vc
+ ret <vscale x 8 x i64> %vd
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll
index 077b4597037c8..70bebb1fcf168 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll
@@ -737,6 +737,37 @@ define <vscale x 1 x i64> @vremu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
ret <vscale x 1 x i64> %vc
}
+; fold (urem x, pow2) -> (and x, pow2-1)
+define <vscale x 1 x i64> @vremu_vi_nxv1i64_1(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vremu_vi_nxv1i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT: vand.vi v8, v8, 15
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = urem <vscale x 1 x i64> %va, %splat
+ ret <vscale x 1 x i64> %vc
+}
+
+; fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
+define <vscale x 1 x i64> @vremu_vi_nxv1i64_2(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {
+; CHECK-LABEL: vremu_vi_nxv1i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, mu
+; CHECK-NEXT: vmv.v.x v25, a0
+; CHECK-NEXT: vsll.vv v25, v25, v9
+; CHECK-NEXT: vadd.vi v25, v25, -1
+; CHECK-NEXT: vand.vv v8, v8, v25
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+ %vc = shl <vscale x 1 x i64> %splat, %vb
+ %vd = urem <vscale x 1 x i64> %va, %vc
+ ret <vscale x 1 x i64> %vd
+}
+
define <vscale x 2 x i64> @vremu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
; CHECK-LABEL: vremu_vv_nxv2i64:
; CHECK: # %bb.0:
@@ -778,6 +809,37 @@ define <vscale x 2 x i64> @vremu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
ret <vscale x 2 x i64> %vc
}
+; fold (urem x, pow2) -> (and x, pow2-1)
+define <vscale x 2 x i64> @vremu_vi_nxv2i64_1(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vremu_vi_nxv2i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT: vand.vi v8, v8, 15
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = urem <vscale x 2 x i64> %va, %splat
+ ret <vscale x 2 x i64> %vc
+}
+
+; fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
+define <vscale x 2 x i64> @vremu_vi_nxv2i64_2(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {
+; CHECK-LABEL: vremu_vi_nxv2i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, mu
+; CHECK-NEXT: vmv.v.x v26, a0
+; CHECK-NEXT: vsll.vv v26, v26, v10
+; CHECK-NEXT: vadd.vi v26, v26, -1
+; CHECK-NEXT: vand.vv v8, v8, v26
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+ %vc = shl <vscale x 2 x i64> %splat, %vb
+ %vd = urem <vscale x 2 x i64> %va, %vc
+ ret <vscale x 2 x i64> %vd
+}
+
define <vscale x 4 x i64> @vremu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
; CHECK-LABEL: vremu_vv_nxv4i64:
; CHECK: # %bb.0:
@@ -819,6 +881,37 @@ define <vscale x 4 x i64> @vremu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
ret <vscale x 4 x i64> %vc
}
+; fold (urem x, pow2) -> (and x, pow2-1)
+define <vscale x 4 x i64> @vremu_vi_nxv4i64_1(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vremu_vi_nxv4i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT: vand.vi v8, v8, 15
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = urem <vscale x 4 x i64> %va, %splat
+ ret <vscale x 4 x i64> %vc
+}
+
+;fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
+define <vscale x 4 x i64> @vremu_vi_nxv4i64_2(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {
+; CHECK-LABEL: vremu_vi_nxv4i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
+; CHECK-NEXT: vmv.v.x v28, a0
+; CHECK-NEXT: vsll.vv v28, v28, v12
+; CHECK-NEXT: vadd.vi v28, v28, -1
+; CHECK-NEXT: vand.vv v8, v8, v28
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+ %vc = shl <vscale x 4 x i64> %splat, %vb
+ %vd = urem <vscale x 4 x i64> %va, %vc
+ ret <vscale x 4 x i64> %vd
+}
+
define <vscale x 8 x i64> @vremu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
; CHECK-LABEL: vremu_vv_nxv8i64:
; CHECK: # %bb.0:
@@ -860,3 +953,33 @@ define <vscale x 8 x i64> @vremu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
ret <vscale x 8 x i64> %vc
}
+; fold (urem x, pow2) -> (and x, pow2-1)
+define <vscale x 8 x i64> @vremu_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vremu_vi_nxv8i64_1:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT: vand.vi v8, v8, 15
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = urem <vscale x 8 x i64> %va, %splat
+ ret <vscale x 8 x i64> %vc
+}
+
+; fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
+define <vscale x 8 x i64> @vremu_vi_nxv8i64_2(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
+; CHECK-LABEL: vremu_vi_nxv8i64_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, zero, 16
+; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu
+; CHECK-NEXT: vmv.v.x v24, a0
+; CHECK-NEXT: vsll.vv v16, v24, v16
+; CHECK-NEXT: vadd.vi v16, v16, -1
+; CHECK-NEXT: vand.vv v8, v8, v16
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+ %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+ %vc = shl <vscale x 8 x i64> %splat, %vb
+ %vd = urem <vscale x 8 x i64> %va, %vc
+ ret <vscale x 8 x i64> %vd
+}
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