[PATCH] D108091: [AggressiveInstCombine] Add shift left instruction to `TruncInstCombine` DAG

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


================
Comment at: llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp:282
+    Instruction *I = Itr.first;
+    if (I->getOpcode() == Instruction::Shl) {
+      KnownBits KnownRHS = computeKnownBits(I->getOperand(1), DL);
----------------
This logic is getting more complicated in D108201, so I want to step back to this patch to check my understanding:
Can SrcBitWidth be different than OrigBitWidth?
If so, can we write a test for that?
If not, then assert that I->getOperand(1)->getType()->getScalarSizeInBits == OrigBitWidth. Then simplify this code to something like:
      KnownBits KnownRHS = computeKnownBits(I->getOperand(1), DL);
      unsigned MinBitWidth = KnownRHS.getMaxValue()
                                 .uadd_sat(APInt(OrigBitWidth, 1))
                                 .getZExtValue();
      if (MinBitWidth >= OrigBitWidth)
        return nullptr;



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108091/new/

https://reviews.llvm.org/D108091