[llvm] 8f6cea4 - [RISCV] Use RISCV::RVVBitsPerBlock for RGK_ScalableVector in getRegisterBitWidth.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-08-17T11:13:15-07:00
New Revision: 8f6cea43e7455ff223eb1eb8f52c386802a9605d

URL: https://github.com/llvm/llvm-project/commit/8f6cea43e7455ff223eb1eb8f52c386802a9605d
DIFF: https://github.com/llvm/llvm-project/commit/8f6cea43e7455ff223eb1eb8f52c386802a9605d.diff

LOG: [RISCV] Use RISCV::RVVBitsPerBlock for RGK_ScalableVector in getRegisterBitWidth.

I might be wrong, but I think this is should be width of the known
min size we use for scalable vectors. It shouldn't scale with
minimum vlen.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D107945

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 95dacb1e6285..7be85cf09d5f 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -66,7 +66,7 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
           ST->hasStdExtV() ? ST->getMinRVVVectorSizeInBits() : 0);
     case TargetTransformInfo::RGK_ScalableVector:
       return TypeSize::getScalable(
-          ST->hasStdExtV() ? ST->getMinRVVVectorSizeInBits() : 0);
+          ST->hasStdExtV() ? RISCV::RVVBitsPerBlock : 0);
     }
 
     llvm_unreachable("Unsupported register kind");