[PATCH] D108137: [AArch64][Global ISel] Add sext/zext improvements

Tue Aug 17 07:11:51 PDT 2021

dmgreen added inline comments.

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Comment at: llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp:3215
+      if (mi_match(I.getOperand(1).getReg(), MRI,
+                   m_Copy(m_GExtVecElt(m_Reg(Src0), m_SpecificICst(1))))) {
+        const LLT &VecTy = MRI.getType(Src0);
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I think this needs to be matching any Integer, not the specific index of 1

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Comment at: llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp:3226

-      ExtI = MIB.buildInstr(IsSigned ? AArch64::SBFMXri : AArch64::UBFMXri,
-                             {DefReg}, {SrcReg})
-                  .addImm(0)
-                  .addImm(SrcSize - 1);
+        ExtI = MIB.buildInstr(AArch64::UMOVvi16, {DefReg}, {Src0}).addImm(0);
+      } else
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And then this needs to use that index found above, not 0.

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Comment at: llvm/test/CodeGen/AArch64/GlobalISel/legalise-sext-zext.mir:2
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-- -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
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This should maybe be running -run-pass=instruction-select, not legalizer?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108137/new/

https://reviews.llvm.org/D108137