[PATCH] D108200: [llvm][sve] Lowering for VLS masked extending loads

[David Truby via Phabricator via llvm-commits]

DavidTruby created this revision.
Herald added subscribers: ctetreau, ecnelises, psnobl, hiraditya, tschuett.
Herald added a reviewer: efriedma.
DavidTruby requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

This extends the custom lowering for extending loads on
fixed length vectors in SVE to support masked extending loads.

The existing tests for correct behaviour of masked extending loads
exhibit bad code generation due to the legalistaion of i1 vectors.
They have been left as-is and new tests have been added that do not
exhibit this behaviour.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108200

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D108200.366857.patch
Type: text/x-patch
Size: 23022 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210817/225933f7/attachment-0001.bin>