[PATCH] D108187: [RISCV] Rename FeatureStdExtZvlsseg to FeatureExtZvlsseg
Jim Lin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 16 23:02:58 PDT 2021
Jim created this revision.
Herald added subscribers: vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
Jim requested review of this revision.
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Prefix of other sub-extensions are FeatureExt*. Rename it for consistency.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D108187
Files:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
llvm/lib/Target/RISCV/RISCV.td
Index: llvm/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -173,12 +173,12 @@
AssemblerPredicate<(all_of FeatureStdExtV),
"'V' (Vector Instructions)">;
-def FeatureStdExtZvlsseg
+def FeatureExtZvlsseg
: SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true",
"'Zvlsseg' (Vector segment load/store instructions)",
[FeatureStdExtV]>;
def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">,
- AssemblerPredicate<(all_of FeatureStdExtZvlsseg),
+ AssemblerPredicate<(all_of FeatureExtZvlsseg),
"'Zvlsseg' (Vector segment load/store instructions)">;
def FeatureExtZvamo
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -90,7 +90,7 @@
Arch += "_zbt0p93";
if (STI.hasFeature(RISCV::FeatureExtZvamo))
Arch += "_zvamo0p10";
- if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
+ if (STI.hasFeature(RISCV::FeatureExtZvlsseg))
Arch += "_zvlsseg0p10";
emitTextAttribute(RISCVAttrs::ARCH, Arch);
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2057,7 +2057,7 @@
clearFeatureBits(RISCV::FeatureExtZbs, "experimental-zbs");
clearFeatureBits(RISCV::FeatureExtZbt, "experimental-zbt");
clearFeatureBits(RISCV::FeatureExtZvamo, "experimental-zvamo");
- clearFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg");
+ clearFeatureBits(RISCV::FeatureExtZvlsseg, "experimental-zvlsseg");
while (!Arch.empty()) {
bool DropFirst = true;
@@ -2117,7 +2117,7 @@
else if (Ext == "zvamo")
setFeatureBits(RISCV::FeatureExtZvamo, "experimental-zvamo");
else if (Ext == "zvlsseg")
- setFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg");
+ setFeatureBits(RISCV::FeatureExtZvlsseg, "experimental-zvlsseg");
else
return Error(ValueExprLoc, "bad arch string " + Ext);
Arch = Arch.drop_until([](char c) { return ::isdigit(c) || c == '_'; });
@@ -2190,7 +2190,7 @@
formalArchStr = (Twine(formalArchStr) + "_zbt0p93").str();
if (getFeatureBits(RISCV::FeatureExtZvamo))
formalArchStr = (Twine(formalArchStr) + "_zvamo0p10").str();
- if (getFeatureBits(RISCV::FeatureStdExtZvlsseg))
+ if (getFeatureBits(RISCV::FeatureExtZvlsseg))
formalArchStr = (Twine(formalArchStr) + "_zvlsseg0p10").str();
getTargetStreamer().emitTextAttribute(Tag, formalArchStr);
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