[PATCH] D107766: [AggressiveInstCombine] Add shift instructions to `TruncInstCombine` DAG

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/test/Transforms/SLPVectorizer/X86/pr50555.ll:3
 ; RUN: opt < %s -mtriple=x86_64-- -aggressive-instcombine -slp-vectorizer -dce -S | FileCheck %s --check-prefixes=SSE
 ; RUN: opt < %s -mtriple=x86_64-- -mcpu=corei7-avx -aggressive-instcombine -slp-vectorizer -dce -S | FileCheck %s --check-prefixes=AVX
 
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anton-afanasyev wrote:
> RKSimon wrote:
> > Should this be moved to be a phase ordering test do you think?
> Do you think it's more test that slp-vectorizer follows aggressive-instcombine? Ok, moved.
This should be in the X86 sub-directory - look at other tests in there for examples as we don't specify explicit passes:
e.g.
```
; RUN: opt -O2 -S < %s | FileCheck %s--check-prefixes=SSE
; RUN: opt -O2 -S -mattr=avx < %s | FileCheck %s--check-prefixes=AVX
; RUN: opt -passes='default<O2>' -S < %s | FileCheck %s--check-prefixes=SSE
; RUN: opt -passes='default<O2>' -S -mattr=avx < %s | FileCheck %s--check-prefixes=AVX
```


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D107766/new/

https://reviews.llvm.org/D107766