[PATCH] D108131: AMDGPU: During img instruction ret value construction cater for non int values
David Stuttard via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 16 07:45:46 PDT 2021
dstuttard created this revision.
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Make sure return type is int type.
Change-Id: I5b2076fd027bd1b0bd2c3494184a278eb04a538f
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D108131
Files:
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Index: llvm/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5948,6 +5948,9 @@
EVT LegalReqRetVT = ReqRetVT;
if (!ReqRetVT.isVector()) {
+ if (!Data.getValueType().isInteger())
+ Data = DAG.getNode(ISD::BITCAST, DL,
+ Data.getValueType().changeTypeToInteger(), Data);
Data = DAG.getNode(ISD::TRUNCATE, DL, ReqRetVT.changeTypeToInteger(), Data);
} else {
// We need to widen the return vector to a legal type
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