[PATCH] D108129: [DAGCombiner] Teach combineShiftToMULH to handle constant and const splat vector.

[Jianjian Guan via Phabricator via llvm-commits]

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Fold (srl (mul (zext i32:$a to i64), i64:c), 32) -> (mulhu $a, $b) if c can truncate to i32 without loss.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108129

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode-rv32.ll

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