[PATCH] D105721: [amdgpu] Add scope metadata support for noalias kernel arguments.

[Jeroen Dobbelaere via Phabricator via llvm-commits]

jeroen.dobbelaere added a comment.

Do not duplicate the logic from the inliner here, but refactor and reuse the `AddNoAliasScopeMetadata` from `InlineFunction.cpp`. That must allow the functionality to stay in sync with each other. It should also make it easier in preparation for the full restrict changes.



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Comment at: llvm/test/CodeGen/AMDGPU/lower-kernargs.ll:1262-1263
+; HSA-NEXT:    [[PTR1_LOAD:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(4)* [[PTR1_KERNARG_OFFSET_CAST]], align 8, !invariant.load !0
+; HSA-NEXT:    store volatile i8 addrspace(1)* [[PTR0_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8, !noalias !7
+; HSA-NEXT:    store volatile i8 addrspace(1)* [[PTR1_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8, !noalias !7
 ; HSA-NEXT:    ret void
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I am also wondering why those two stores are referring to the same noalias set ? In the current noalias scope handling, I would expect something like:
   ; HSA-NEXT:    store volatile i8 addrspace(1)* [[PTR0_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8, !alias.scope !42, !noalias !43
   ; HSA-NEXT:    store volatile i8 addrspace(1)* [[PTR1_LOAD]], i8 addrspace(1)* addrspace(1)* undef, align 8, !alias.scope !43, !noalias !42

indicating that the two stores are exclusive ?



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Comment at: llvm/test/CodeGen/AMDGPU/lower-kernargs.ll:1937
 ; GCN: !2 = !{i64 128}
 ; GCN: !3 = !{i64 1024}
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Also add the `HSA`/`MESA` checks for the noalias-scope related metadata.


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https://reviews.llvm.org/D105721