[PATCH] D108103: [DAGCombiner] Add one use restriction for the pattern (and (add x, c1), (lshr y, c2))

[weiwei via Phabricator via llvm-commits]

wwei created this revision.
wwei added reviewers: MatzeB, RKSimon, lebedev.ri, craig.topper, spatel.
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If the output of `(add x, c1)` happens to be the input(that is, y) of `(lshr y, c2)`, the fold for `(and (add x, c1), (lshr y, c2))` may get a wrong result.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108103

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/combine-and-like.ll


Index: llvm/test/CodeGen/AArch64/combine-and-like.ll
===================================================================
--- llvm/test/CodeGen/AArch64/combine-and-like.ll
+++ llvm/test/CodeGen/AArch64/combine-and-like.ll
@@ -11,3 +11,16 @@
   %3 = and i32 %2, %1
   ret i32 %3
 }
+
+define i32 @f1(i32 %a0) {
+; CHECK-LABEL: f1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #65535
+; CHECK-NEXT:    add w8, w0, w8
+; CHECK-NEXT:    and w0, w8, w8, lsr #16
+; CHECK-NEXT:    ret
+  %1 = add i32 %a0, 65535
+  %2 = lshr i32 %1, 16
+  %3 = and i32 %1, %2
+  ret i32 %3
+}
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -5149,8 +5149,8 @@
   if (SDValue V = foldLogicOfSetCCs(true, N0, N1, DL))
     return V;
 
-  if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
-      VT.getSizeInBits() <= 64) {
+  if (N0.getOpcode() == ISD::ADD && N0.hasOneUse() &&
+      N1.getOpcode() == ISD::SRL && VT.getSizeInBits() <= 64) {
     if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
       if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
         // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal


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