[llvm] f7e534c - [x86] add tests for fcmps with logic ops; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2021-08-13T17:03:22-04:00
New Revision: f7e534c174a446f9ecc7b369dc75f1ad6da5e0ef

URL: https://github.com/llvm/llvm-project/commit/f7e534c174a446f9ecc7b369dc75f1ad6da5e0ef
DIFF: https://github.com/llvm/llvm-project/commit/f7e534c174a446f9ecc7b369dc75f1ad6da5e0ef.diff

LOG: [x86] add tests for fcmps with logic ops; NFC

Added: 
    llvm/test/CodeGen/X86/fcmp-logic.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/fcmp-logic.ll b/llvm/test/CodeGen/X86/fcmp-logic.ll
new file mode 100644
index 0000000000000..54f7183ef3337
--- /dev/null
+++ b/llvm/test/CodeGen/X86/fcmp-logic.ll
@@ -0,0 +1,151 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
+
+define i1 @olt_ole_and_f32(float %w, float %x, float %y, float %z) {
+; CHECK-LABEL: olt_ole_and_f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ucomiss %xmm0, %xmm1
+; CHECK-NEXT:    seta %cl
+; CHECK-NEXT:    ucomiss %xmm2, %xmm3
+; CHECK-NEXT:    setae %al
+; CHECK-NEXT:    andb %cl, %al
+; CHECK-NEXT:    retq
+  %f1 = fcmp olt float %w, %x
+  %f2 = fcmp ole float %y, %z
+  %r = and i1 %f1, %f2
+  ret i1 %r
+}
+
+define i1 @oge_oeq_or_f32(float %w, float %x, float %y, float %z) {
+; CHECK-LABEL: oge_oeq_or_f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ucomiss %xmm1, %xmm0
+; CHECK-NEXT:    setae %cl
+; CHECK-NEXT:    ucomiss %xmm3, %xmm2
+; CHECK-NEXT:    setnp %dl
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    andb %dl, %al
+; CHECK-NEXT:    orb %cl, %al
+; CHECK-NEXT:    retq
+  %f1 = fcmp oge float %w, %x
+  %f2 = fcmp oeq float %y, %z
+  %r = or i1 %f1, %f2
+  ret i1 %r
+}
+
+define i1 @ord_one_xor_f32(float %w, float %x, float %y, float %z) {
+; CHECK-LABEL: ord_one_xor_f32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ucomiss %xmm1, %xmm0
+; CHECK-NEXT:    setnp %cl
+; CHECK-NEXT:    ucomiss %xmm3, %xmm2
+; CHECK-NEXT:    setne %al
+; CHECK-NEXT:    xorb %cl, %al
+; CHECK-NEXT:    retq
+  %f1 = fcmp ord float %w, %x
+  %f2 = fcmp one float %y, %z
+  %r = xor i1 %f1, %f2
+  ret i1 %r
+}
+
+define i1 @une_ugt_and_f64(double %w, double %x, double %y, double %z) {
+; CHECK-LABEL: une_ugt_and_f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ucomisd %xmm1, %xmm0
+; CHECK-NEXT:    setp %al
+; CHECK-NEXT:    setne %cl
+; CHECK-NEXT:    orb %al, %cl
+; CHECK-NEXT:    ucomisd %xmm2, %xmm3
+; CHECK-NEXT:    setb %al
+; CHECK-NEXT:    andb %cl, %al
+; CHECK-NEXT:    retq
+  %f1 = fcmp une double %w, %x
+  %f2 = fcmp ugt double %y, %z
+  %r = and i1 %f1, %f2
+  ret i1 %r
+}
+
+define i1 @ult_uge_or_f64(double %w, double %x, double %y, double %z) {
+; CHECK-LABEL: ult_uge_or_f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ucomisd %xmm1, %xmm0
+; CHECK-NEXT:    setb %cl
+; CHECK-NEXT:    ucomisd %xmm2, %xmm3
+; CHECK-NEXT:    setbe %al
+; CHECK-NEXT:    orb %cl, %al
+; CHECK-NEXT:    retq
+  %f1 = fcmp ult double %w, %x
+  %f2 = fcmp uge double %y, %z
+  %r = or i1 %f1, %f2
+  ret i1 %r
+}
+
+define i1 @une_uno_xor_f64(double %w, double %x, double %y, double %z) {
+; CHECK-LABEL: une_uno_xor_f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ucomisd %xmm1, %xmm0
+; CHECK-NEXT:    setp %al
+; CHECK-NEXT:    setne %cl
+; CHECK-NEXT:    orb %al, %cl
+; CHECK-NEXT:    ucomisd %xmm3, %xmm2
+; CHECK-NEXT:    setp %al
+; CHECK-NEXT:    xorb %cl, %al
+; CHECK-NEXT:    retq
+  %f1 = fcmp une double %w, %x
+  %f2 = fcmp uno double %y, %z
+  %r = xor i1 %f1, %f2
+  ret i1 %r
+}
+
+define i1 @olt_olt_and_f32_f64(float %w, float %x, double %y, double %z) {
+; CHECK-LABEL: olt_olt_and_f32_f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ucomiss %xmm0, %xmm1
+; CHECK-NEXT:    seta %cl
+; CHECK-NEXT:    ucomisd %xmm2, %xmm3
+; CHECK-NEXT:    seta %al
+; CHECK-NEXT:    andb %cl, %al
+; CHECK-NEXT:    retq
+  %f1 = fcmp olt float %w, %x
+  %f2 = fcmp olt double %y, %z
+  %r = and i1 %f1, %f2
+  ret i1 %r
+}
+
+define i1 @une_uno_xor_f64_use1(double %w, double %x, double %y, double %z, i1* %p) {
+; CHECK-LABEL: une_uno_xor_f64_use1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ucomisd %xmm1, %xmm0
+; CHECK-NEXT:    setp %al
+; CHECK-NEXT:    setne %cl
+; CHECK-NEXT:    orb %al, %cl
+; CHECK-NEXT:    movb %cl, (%rdi)
+; CHECK-NEXT:    ucomisd %xmm3, %xmm2
+; CHECK-NEXT:    setp %al
+; CHECK-NEXT:    xorb %cl, %al
+; CHECK-NEXT:    retq
+  %f1 = fcmp une double %w, %x
+  store i1 %f1, i1* %p
+  %f2 = fcmp uno double %y, %z
+  %r = xor i1 %f1, %f2
+  ret i1 %r
+}
+
+define i1 @une_uno_xor_f64_use2(double %w, double %x, double %y, double %z, i1* %p) {
+; CHECK-LABEL: une_uno_xor_f64_use2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ucomisd %xmm1, %xmm0
+; CHECK-NEXT:    setp %al
+; CHECK-NEXT:    setne %cl
+; CHECK-NEXT:    orb %al, %cl
+; CHECK-NEXT:    ucomisd %xmm3, %xmm2
+; CHECK-NEXT:    setp %al
+; CHECK-NEXT:    setp (%rdi)
+; CHECK-NEXT:    xorb %cl, %al
+; CHECK-NEXT:    retq
+  %f1 = fcmp une double %w, %x
+  %f2 = fcmp uno double %y, %z
+  store i1 %f2, i1* %p
+  %r = xor i1 %f1, %f2
+  ret i1 %r
+}