[PATCH] D107901: [hwasan] Prevent reordering of tag checks.

Florian Mayer via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Aug 13 07:16:17 PDT 2021


fmayer added a comment.

In D107901#2942065 <https://reviews.llvm.org/D107901#2942065>, @eugenis wrote:

> Another weird thing: even without this patch I see
>
>   { 561,        2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList4, ImplicitList5, OperandInfo65 },  // Inst #561 = HWASAN_CHECK_MEMACCESS
>   { 562,        2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList6, ImplicitList5, OperandInfo65 },  // Inst #562 = HWASAN_CHECK_MEMACCESS_SHORTGRANULES
>
> in `lib/Target/AArch64/AArch64GenInstrInfo.inc`, i.e. these instructions are already mayLoad | mayStore.

I tried to revert this part and it still solves the issues. I would still prefer to leave it as is to have it more explicit.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107901/new/

https://reviews.llvm.org/D107901



More information about the llvm-commits mailing list