[PATCH] D105853: [ISel] Expand saddsat and ssubsat via asr and xor

[Dave Green via Phabricator via llvm-commits]

dmgreen updated this revision to Diff 366230.
dmgreen added a comment.

After trying custom lowering a couple of times, I've decided I don't know the X86 architecture well enough to make good decisions about when it should be custom lowering, and what it should lower to.

Although it's a little ugly, this adds a target hook to pick between the two options and chooses the old method for X86 ssub.sat, where it appeared to be increasing instruction count with the ashr xor version. Does that sound OK to folks?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105853/new/

https://reviews.llvm.org/D105853

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/test/CodeGen/AArch64/sadd_sat.ll
  llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
  llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/ssub_sat.ll
  llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
  llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
  llvm/test/CodeGen/AMDGPU/saddsat.ll
  llvm/test/CodeGen/AMDGPU/ssubsat.ll
  llvm/test/CodeGen/ARM/qdadd.ll
  llvm/test/CodeGen/ARM/sadd_sat.ll
  llvm/test/CodeGen/ARM/sadd_sat_plus.ll
  llvm/test/CodeGen/ARM/ssub_sat.ll
  llvm/test/CodeGen/ARM/ssub_sat_plus.ll
  llvm/test/CodeGen/PowerPC/sat-add.ll
  llvm/test/CodeGen/RISCV/sadd_sat.ll
  llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
  llvm/test/CodeGen/RISCV/ssub_sat.ll
  llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
  llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
  llvm/test/CodeGen/X86/combine-add-ssat.ll
  llvm/test/CodeGen/X86/sadd_sat.ll
  llvm/test/CodeGen/X86/sadd_sat_plus.ll
  llvm/test/CodeGen/X86/sadd_sat_vec.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D105853.366230.patch
Type: text/x-patch
Size: 231088 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210813/793e2bd2/attachment-0001.bin>