[PATCH] D107901: [hwasan] Prevent reordering of tag checks.

Thu Aug 12 11:59:06 PDT 2021

eugenis added a comment.

It would be nice to have a test for this, maybe something like test/CodeGen/AArch64/irg-nomem.mir (but the opposite - you'd want store merging to not happen).

Another weird thing: even without this patch I see

  { 561,        2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList4, ImplicitList5, OperandInfo65 },  // Inst #561 = HWASAN_CHECK_MEMACCESS
  { 562,        2,      0,      0,      0,      0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList6, ImplicitList5, OperandInfo65 },  // Inst #562 = HWASAN_CHECK_MEMACCESS_SHORTGRANULES

in `lib/Target/AArch64/AArch64GenInstrInfo.inc`, i.e. these instructions are already mayLoad | mayStore.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D107901/new/

https://reviews.llvm.org/D107901