[PATCH] D106601: [RISCV] Teach vsetvli insertion pass that it doesn't need to insert vsetvli for unit-stride or strided loads/stores in some cases.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 12 10:06:08 PDT 2021
This revision was automatically updated to reflect the committed changes.
Closed by commit rG79fbddbea0c6: [RISCV] Teach vsetvli insertion pass that it doesn't need to insert vsetvli for… (authored by craig.topper).
Changed prior to commit:
https://reviews.llvm.org/D106601?vs=362432&id=366025#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D106601/new/
https://reviews.llvm.org/D106601
Files:
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
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