[PATCH] D107957: [LegalizeTypes][VP] Add splitting support for binary VP ops

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck created this revision.
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This patch extends D107904 <https://reviews.llvm.org/D107904>'s introduction of vector-predicated (VP)
operation legalization to include vector splitting.

When the result of a binary VP operation needs splitting, all of its
operands are split in kind. The two operands and the mask are split as
usual, and the vector-length parameter EVL is "split" such that the low
and high halves each execute the correct number of elements.

Tests have been added to the RISC-V target to show splitting several
scenarios for fixed- and scalable-vector types. Without support for
`umax` (e.g. in the `B` extension) the generated code starts to branch.
Ideally a cost model would prevent their insertion in the first place.

Through these tests many opportunities for better codegen can be seen:
combining known-undef VP operations and for constant-folding operations
on `ISD::VSCALE`, to name but a few.

I believe one bug in the RISC-V backend can be observed where we
generate an incorrect `vsetvli`. In this case, the vector length is fed
through a `select_cc` which just selects between `0` and `0`. This is
then lowered as a `Select_GPR_Using_CC_GPR` with two `x0`s which is
selected as a `%0:gpr = COPY x0` and fed into the original `vsetvli`.
At this point I believe the code is correct. However, unfortunately the
COPY is later register-coalesced into the `vsetvli` itself, incorrectly
changing the semantics of the operation.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D107957

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll

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