[llvm] 8f359a8 - [llvm][sve] Fix erroneous tests for fixed length extending loads

[David Truby via llvm-commits]

Author: David Truby
Date: 2021-08-12T10:31:43Z
New Revision: 8f359a80e466f221e3b3d93e65587d74f9ba2fda

URL: https://github.com/llvm/llvm-project/commit/8f359a80e466f221e3b3d93e65587d74f9ba2fda
DIFF: https://github.com/llvm/llvm-project/commit/8f359a80e466f221e3b3d93e65587d74f9ba2fda.diff

LOG: [llvm][sve] Fix erroneous tests for fixed length extending loads

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll
index 20178a98ca4f..9b833e408fa9 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-ext-loads.ll
@@ -54,11 +54,10 @@ define <16 x i32> @load_zext_v16i16i32(<16 x i16>* %ap) #0 {
   ; VBITS_EQ_256-DAG: mov x9, sp
   ; VBITS_EQ_256-DAG: st1h { [[Z0]].h }, [[PG]], [x9]
   ; VBITS_EQ_256-DAG: ldp q[[R0:[0-9]+]], q[[R1:[0-9]+]], [sp]
-  ; VBITS_EQ_256-DAG: add x9, x8, #32
   ; VBITS_EQ_256-DAG: ptrue [[PG1:p[0-9]+]].s, vl8
   ; VBITS_EQ_256-DAG: uunpklo z[[R0]].s, z[[R0]].h
   ; VBITS_EQ_256-DAG: uunpklo z[[R1]].s, z[[R1]].h
-  ; VBITS_EQ_256-DAG: st1w { z[[R1]].s }, [[PG1]], [x9]
+  ; VBITS_EQ_256-DAG: st1w { z[[R1]].s }, [[PG1]], [x8, x9, lsl #2]
   ; VBITS_EQ_256-DAG: st1w { z[[R0]].s }, [[PG1]], [x8]
   ; VBITS_EQ_256-DAG: ret
   %a = load <16 x i16>, <16 x i16>* %ap
@@ -122,11 +121,10 @@ define <16 x i32> @load_sext_v16i16i32(<16 x i16>* %ap) #0 {
   ; VBITS_EQ_256-DAG: mov x9, sp
   ; VBITS_EQ_256-DAG: st1h { [[Z0]].h }, [[PG]], [x9]
   ; VBITS_EQ_256-DAG: ldp q[[R0:[0-9]+]], q[[R1:[0-9]+]], [sp]
-  ; VBITS_EQ_256-DAG: add x9, x8, #32
   ; VBITS_EQ_256-DAG: ptrue [[PG1:p[0-9]+]].s, vl8
   ; VBITS_EQ_256-DAG: sunpklo z[[R0]].s, z[[R0]].h
   ; VBITS_EQ_256-DAG: sunpklo z[[R1]].s, z[[R1]].h
-  ; VBITS_EQ_256-DAG: st1w { z[[R1]].s }, [[PG1]], [x9]
+  ; VBITS_EQ_256-DAG: st1w { z[[R1]].s }, [[PG1]], [x8, x9, lsl #2]
   ; VBITS_EQ_256-DAG: st1w { z[[R0]].s }, [[PG1]], [x8]
   ; VBITS_EQ_256-DAG: ret
   %a = load <16 x i16>, <16 x i16>* %ap