[PATCH] D107929: [GlobalISel] Narrow binops feeding into G_AND with a mask

[Amara Emerson via Phabricator via llvm-commits]

aemerson added inline comments.


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Comment at: llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp:4361
+  // add_64(x, y) & 65535 == zext(add_16(trunc(x), trunc(y))) & 65535
+  MachineInstr &LHSInst = *MRI.getVRegDef(AndLHS);
+  unsigned LHSOpc = LHSInst.getOpcode();
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`getDefIgnoringCopies()`?


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Comment at: llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp:4386-4387
+  unsigned NarrowWidth = Mask.countTrailingOnes();
+  assert(NarrowWidth != WideTy.getSizeInBits() &&
+         "No-op AND should have already been eliminated!");
+  LLT NarrowTy = LLT::scalar(NarrowWidth);
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I don't think we should be making assumptions about combine ordering. Targets may choose to define their own combine configs by picking and choosing.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107929/new/

https://reviews.llvm.org/D107929