[PATCH] D107902: [AArch64][SME] Disable NEON on generic CPU for streaming mode

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes created this revision.
c-rhodes added reviewers: paulwalker-arm, david-arm.
Herald added subscribers: ctetreau, hiraditya, kristof.beyls.
c-rhodes requested review of this revision.
Herald added a project: LLVM.

In streaming mode most of the NEON instruction set is illegal, but if no
CPU is specified the default is generic, which implies NEON. This patch
disables NEON when it is implied by the generic CPU if streaming mode is
enabled (+streaming-sve).

Subsequent patches will add support for the small subset of NEON
instructions that are legal in streaming mode.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D107902

Files:
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
  llvm/test/MC/AArch64/SME/feature-negative.s
  llvm/test/MC/AArch64/SME/feature.s


Index: llvm/test/MC/AArch64/SME/feature.s
===================================================================
--- llvm/test/MC/AArch64/SME/feature.s
+++ llvm/test/MC/AArch64/SME/feature.s
@@ -8,4 +8,12 @@
 
 // Verify +sme flags imply +bf16
 bfdot z0.s, z1.h, z2.h
-// CHECK-INST: bfdot z0.s, z1.h, z2.h
+// CHECK: bfdot z0.s, z1.h, z2.h
+
+// Most of the NEON instruction set is illegal in streaming mode. If no CPU is
+// specified the default is generic which implies NEON, but if streaming-sve
+// (implied by +sme) is enabled it's disabled, only if it's not explicitly
+// enabled, verify this.
+.arch_extension simd
+dup b0, v0.b[0]
+// CHECK: dup b0, v0.b[0]
Index: llvm/test/MC/AArch64/SME/feature-negative.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/SME/feature-negative.s
@@ -0,0 +1,5 @@
+// RUN: not llvm-mc -triple=aarch64 -mattr=+streaming-sve < %s 2>&1 | FileCheck %s
+
+// Verify NEON is disabled when targeting streaming mode.
+dup b0, v0.b[0]
+// CHECK: error: instruction requires: neon
Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
===================================================================
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
@@ -57,7 +57,18 @@
       CPU = "apple-a12";
   }
 
-  return createAArch64MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
+  // Most of the NEON instruction set isn't supported in streaming mode on SME
+  // targets, but if no CPU is specified the default is "generic", which
+  // implies NEON. If streaming mode is enabled and the CPU is generic, disable
+  // NEON, only if it isn't explicitly specified in the feature flags.
+  bool HasNEON = FS.contains("neon");
+  MCSubtargetInfo *STI =
+      createAArch64MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
+  if (CPU.equals("generic") && !HasNEON &&
+      STI->hasFeature(AArch64::FeatureNEON) &&
+      STI->hasFeature(AArch64::FeatureStreamingSVE))
+    STI->ToggleFeature(AArch64::FeatureNEON);
+  return STI;
 }
 
 void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {


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