[llvm] 7ec4ce1 - [AArch64][GlobalISel] Relax oneuse restriction for PTR_ADD chain combining to check addressing legality.
Amara Emerson via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 10 16:41:34 PDT 2021
Author: Amara Emerson
Date: 2021-08-10T16:41:18-07:00
New Revision: 7ec4ce157b5e5f48a3f69c32a062b5e64165da3f
URL: https://github.com/llvm/llvm-project/commit/7ec4ce157b5e5f48a3f69c32a062b5e64165da3f
DIFF: https://github.com/llvm/llvm-project/commit/7ec4ce157b5e5f48a3f69c32a062b5e64165da3f.diff
LOG: [AArch64][GlobalISel] Relax oneuse restriction for PTR_ADD chain combining to check addressing legality.
With contributions by Sebastian Neubauer
Differential Revision: https://reviews.llvm.org/D105676
Added:
Modified:
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-reassociation.mir
llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ptradd-chain.mir
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index e873e237068d..23ff22fe3aa6 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -1710,13 +1710,6 @@ bool CombinerHelper::matchPtrAddImmedChain(MachineInstr &MI,
if (!MaybeImmVal)
return false;
- // Don't do this combine if there multiple uses of the first PTR_ADD,
- // since we may be able to compute the second PTR_ADD as an immediate
- // offset anyway. Folding the first offset into the second may cause us
- // to go beyond the bounds of our legal addressing modes.
- if (!MRI.hasOneNonDBGUse(Add2))
- return false;
-
MachineInstr *Add2Def = MRI.getUniqueVRegDef(Add2);
if (!Add2Def || Add2Def->getOpcode() != TargetOpcode::G_PTR_ADD)
return false;
@@ -1727,8 +1720,36 @@ bool CombinerHelper::matchPtrAddImmedChain(MachineInstr &MI,
if (!MaybeImm2Val)
return false;
+ // Check if the new combined immediate forms an illegal addressing mode.
+ // Do not combine if it was legal before but would get illegal.
+ // To do so, we need to find a load/store user of the pointer to get
+ // the access type.
+ Type *AccessTy = nullptr;
+ auto &MF = *MI.getMF();
+ for (auto &UseMI : MRI.use_nodbg_instructions(MI.getOperand(0).getReg())) {
+ if (auto *LdSt = dyn_cast<GLoadStore>(&UseMI)) {
+ AccessTy = getTypeForLLT(MRI.getType(LdSt->getReg(0)),
+ MF.getFunction().getContext());
+ break;
+ }
+ }
+ TargetLoweringBase::AddrMode AMNew;
+ APInt CombinedImm = MaybeImmVal->Value + MaybeImm2Val->Value;
+ AMNew.BaseOffs = CombinedImm.getSExtValue();
+ if (AccessTy) {
+ AMNew.HasBaseReg = true;
+ TargetLoweringBase::AddrMode AMOld;
+ AMOld.BaseOffs = MaybeImm2Val->Value.getSExtValue();
+ AMOld.HasBaseReg = true;
+ unsigned AS = MRI.getType(Add2).getAddressSpace();
+ const auto &TLI = *MF.getSubtarget().getTargetLowering();
+ if (TLI.isLegalAddressingMode(MF.getDataLayout(), AMOld, AccessTy, AS) &&
+ !TLI.isLegalAddressingMode(MF.getDataLayout(), AMNew, AccessTy, AS))
+ return false;
+ }
+
// Pass the combined immediate to the apply function.
- MatchInfo.Imm = (MaybeImmVal->Value + MaybeImm2Val->Value).getSExtValue();
+ MatchInfo.Imm = AMNew.BaseOffs;
MatchInfo.Base = Base;
return true;
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-reassociation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-reassociation.mir
index 436270a09552..1936473f15eb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-reassociation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-ptradd-reassociation.mir
@@ -13,7 +13,7 @@ body: |
; CHECK-LABEL: name: test1_noreassoc_legal_already_new_is_illegal
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4777
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1600
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
@@ -23,7 +23,7 @@ body: |
; CHECK: $w0 = COPY [[LOAD]](s32)
; CHECK: RET_ReallyLR implicit $w0
%0:_(p0) = COPY $x0
- %2:_(s64) = G_CONSTANT i64 4777
+ %2:_(s64) = G_CONSTANT i64 1600
%4:_(s64) = G_CONSTANT i64 6
%9:_(s32) = G_CONSTANT i32 0
%10:_(p0) = G_PTR_ADD %0, %2(s64)
@@ -161,7 +161,7 @@ body: |
; CHECK-LABEL: name: walk_through_inttoptr
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4777
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1600
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
@@ -173,7 +173,7 @@ body: |
; CHECK: $w0 = COPY [[LOAD]](s32)
; CHECK: RET_ReallyLR implicit $w0
%0:_(p0) = COPY $x0
- %2:_(s64) = G_CONSTANT i64 4777
+ %2:_(s64) = G_CONSTANT i64 1600
%4:_(s64) = G_CONSTANT i64 6
%9:_(s32) = G_CONSTANT i32 0
%10:_(p0) = G_PTR_ADD %0, %2(s64)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ptradd-chain.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ptradd-chain.mir
index 6459f21cd03a..4fe7a1817fde 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ptradd-chain.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ptradd-chain.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple aarch64-apple-ios -run-pass=aarch64-prelegalizer-combiner %s -o - -verify-machineinstrs | FileCheck %s
+# RUN: llc -mtriple aarch64-apple-ios -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombinerhelper-only-enable-rule="ptr_add_immed_chain" %s -o - -verify-machineinstrs | FileCheck %s
+# REQUIRES: asserts
# Check that we fold two adds of constant offsets with G_PTR_ADD into a single G_PTR_ADD.
---
@@ -70,3 +71,33 @@ body: |
$x0 = COPY %5(p0)
RET_ReallyLR implicit $x0
...
+---
+name: ptradd_would_form_illegal_load_addressing
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $x0
+
+ ; CHECK-LABEL: name: ptradd_would_form_illegal_load_addressing
+ ; CHECK: liveins: $x0
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4096
+ ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C1]](s64)
+ ; CHECK: %ld:_(s64) = G_LOAD [[PTR_ADD1]](p0) :: (load (s64))
+ ; CHECK: %ld_other:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (load (s64))
+ ; CHECK: $x0 = COPY %ld(s64)
+ ; CHECK: $x1 = COPY %ld_other(s64)
+ ; CHECK: RET_ReallyLR implicit $x0
+ %0:_(p0) = COPY $x0
+ %1:_(s64) = G_CONSTANT i64 4
+ %2:_(s64) = G_CONSTANT i64 4096
+ %3:_(p0) = G_PTR_ADD %0(p0), %1
+ %4:_(p0) = G_PTR_ADD %3(p0), %2
+ %ld:_(s64) = G_LOAD %4(p0) :: (load 8)
+ %ld_other:_(s64) = G_LOAD %3(p0) :: (load 8)
+ $x0 = COPY %ld(s64)
+ $x1 = COPY %ld_other(s64)
+ RET_ReallyLR implicit $x0
+...
More information about the llvm-commits
mailing list