[PATCH] D107820: [RISCV] Optimize mul in the zba extension with SH*ADD

[Ben Shi via Phabricator via llvm-commits]

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This patch does the following optimization of mul with a constant in RV64.

(sext_inreg (mul x, 3 * power_of_2), i32) -> (SLLIW (SH1ADD x, x), bits)
(sext_inreg (mul x, 5 * power_of_2), i32) -> (SLLIW (SH2ADD x, x), bits)
(sext_inreg (mul x, 9 * power_of_2), i32) -> (SLLIW (SH3ADD x, x), bits)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D107820

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv64zba.ll


Index: llvm/test/CodeGen/RISCV/rv64zba.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64zba.ll
+++ llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -1254,14 +1254,14 @@
 ;
 ; RV64IB-LABEL: mulw192:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a1, zero, 192
-; RV64IB-NEXT:    mulw a0, a0, a1
+; RV64IB-NEXT:    sh1add a0, a0, a0
+; RV64IB-NEXT:    slliw a0, a0, 6
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: mulw192:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a1, zero, 192
-; RV64IBA-NEXT:    mulw a0, a0, a1
+; RV64IBA-NEXT:    sh1add a0, a0, a0
+; RV64IBA-NEXT:    slliw a0, a0, 6
 ; RV64IBA-NEXT:    ret
   %c = mul i32 %a, 192
   ret i32 %c
@@ -1276,14 +1276,14 @@
 ;
 ; RV64IB-LABEL: mulw320:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a1, zero, 320
-; RV64IB-NEXT:    mulw a0, a0, a1
+; RV64IB-NEXT:    sh2add a0, a0, a0
+; RV64IB-NEXT:    slliw a0, a0, 6
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: mulw320:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a1, zero, 320
-; RV64IBA-NEXT:    mulw a0, a0, a1
+; RV64IBA-NEXT:    sh2add a0, a0, a0
+; RV64IBA-NEXT:    slliw a0, a0, 6
 ; RV64IBA-NEXT:    ret
   %c = mul i32 %a, 320
   ret i32 %c
@@ -1298,14 +1298,14 @@
 ;
 ; RV64IB-LABEL: mulw576:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a1, zero, 576
-; RV64IB-NEXT:    mulw a0, a0, a1
+; RV64IB-NEXT:    sh3add a0, a0, a0
+; RV64IB-NEXT:    slliw a0, a0, 6
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: mulw576:
 ; RV64IBA:       # %bb.0:
-; RV64IBA-NEXT:    addi a1, zero, 576
-; RV64IBA-NEXT:    mulw a0, a0, a1
+; RV64IBA-NEXT:    sh3add a0, a0, a0
+; RV64IBA-NEXT:    slliw a0, a0, 6
 ; RV64IBA-NEXT:    ret
   %c = mul i32 %a, 576
   ret i32 %c
Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -1065,6 +1065,16 @@
           (SH2ADDUW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(i64 (add (and (shl GPR:$rs1, (i64 3)), 0x7FFFFFFFF), non_imm12:$rs2)),
           (SH3ADDUW GPR:$rs1, GPR:$rs2)>;
+
+def : Pat<(i64 (sext_inreg (mul GPR:$r, C3LeftShift:$i), i32)),
+          (SLLIW (SH1ADD GPR:$r, GPR:$r),
+                 (TrailingZerosXForm C3LeftShift:$i))>;
+def : Pat<(i64 (sext_inreg (mul GPR:$r, C5LeftShift:$i), i32)),
+          (SLLIW (SH2ADD GPR:$r, GPR:$r),
+                 (TrailingZerosXForm C5LeftShift:$i))>;
+def : Pat<(i64 (sext_inreg (mul GPR:$r, C9LeftShift:$i), i32)),
+          (SLLIW (SH3ADD GPR:$r, GPR:$r),
+                 (TrailingZerosXForm C9LeftShift:$i))>;
 } // Predicates = [HasStdExtZba, IsRV64]
 
 let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {


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